mpc8569mds.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2010 Freescale Semiconductor.
  4. *
  5. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. */
  7. #include <common.h>
  8. #include <console.h>
  9. #include <flash.h>
  10. #include <hwconfig.h>
  11. #include <init.h>
  12. #include <pci.h>
  13. #include <asm/processor.h>
  14. #include <asm/mmu.h>
  15. #include <asm/cache.h>
  16. #include <asm/immap_85xx.h>
  17. #include <asm/fsl_pci.h>
  18. #include <fsl_ddr_sdram.h>
  19. #include <asm/fsl_serdes.h>
  20. #include <asm/io.h>
  21. #include <spd_sdram.h>
  22. #include <i2c.h>
  23. #include <ioports.h>
  24. #include <linux/libfdt.h>
  25. #include <fdt_support.h>
  26. #include <fsl_esdhc.h>
  27. #include <phy.h>
  28. #include "bcsr.h"
  29. #if defined(CONFIG_PQ_MDS_PIB)
  30. #include "../common/pq-mds-pib.h"
  31. #endif
  32. const qe_iop_conf_t qe_iop_conf_tab[] = {
  33. /* QE_MUX_MDC */
  34. {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
  35. /* QE_MUX_MDIO */
  36. {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
  37. #if defined(CONFIG_SYS_UCC_RGMII_MODE)
  38. /* UCC_1_RGMII */
  39. {2, 11, 2, 0, 1}, /* CLK12 */
  40. {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
  41. {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
  42. {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
  43. {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
  44. {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
  45. {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
  46. {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
  47. {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
  48. {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  49. {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
  50. {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
  51. {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
  52. /* UCC_2_RGMII */
  53. {2, 16, 2, 0, 3}, /* CLK17 */
  54. {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
  55. {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
  56. {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
  57. {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
  58. {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
  59. {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
  60. {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
  61. {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
  62. {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
  63. {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
  64. {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
  65. {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
  66. /* UCC_3_RGMII */
  67. {2, 11, 2, 0, 1}, /* CLK12 */
  68. {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
  69. {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
  70. {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
  71. {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
  72. {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
  73. {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
  74. {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
  75. {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
  76. {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
  77. {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
  78. {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
  79. {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
  80. /* UCC_4_RGMII */
  81. {2, 16, 2, 0, 3}, /* CLK17 */
  82. {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
  83. {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
  84. {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
  85. {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
  86. {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
  87. {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
  88. {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
  89. {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
  90. {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
  91. {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
  92. {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
  93. {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
  94. #elif defined(CONFIG_SYS_UCC_RMII_MODE)
  95. /* UCC_1_RMII */
  96. {2, 15, 2, 0, 1}, /* CLK16 */
  97. {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
  98. {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
  99. {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
  100. {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
  101. {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
  102. {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
  103. /* UCC_2_RMII */
  104. {2, 15, 2, 0, 1}, /* CLK16 */
  105. {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
  106. {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
  107. {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
  108. {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
  109. {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
  110. {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
  111. /* UCC_3_RMII */
  112. {2, 15, 2, 0, 1}, /* CLK16 */
  113. {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
  114. {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
  115. {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
  116. {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
  117. {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
  118. {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
  119. /* UCC_4_RMII */
  120. {2, 15, 2, 0, 1}, /* CLK16 */
  121. {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
  122. {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
  123. {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
  124. {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
  125. {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
  126. {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
  127. #endif
  128. /* UART1 is muxed with QE PortF bit [9-12].*/
  129. {5, 12, 2, 0, 3}, /* UART1_SIN */
  130. {5, 9, 1, 0, 3}, /* UART1_SOUT */
  131. {5, 10, 2, 0, 3}, /* UART1_CTS_B */
  132. {5, 11, 1, 0, 2}, /* UART1_RTS_B */
  133. /* QE UART */
  134. {0, 19, 1, 0, 2}, /* QEUART_TX */
  135. {1, 17, 2, 0, 3}, /* QEUART_RX */
  136. {0, 25, 1, 0, 1}, /* QEUART_RTS */
  137. {1, 23, 2, 0, 1}, /* QEUART_CTS */
  138. /* QE USB */
  139. {5, 3, 1, 0, 1}, /* USB_OE */
  140. {5, 4, 1, 0, 2}, /* USB_TP */
  141. {5, 5, 1, 0, 2}, /* USB_TN */
  142. {5, 6, 2, 0, 2}, /* USB_RP */
  143. {5, 7, 2, 0, 1}, /* USB_RX */
  144. {5, 8, 2, 0, 1}, /* USB_RN */
  145. {2, 4, 2, 0, 2}, /* CLK5 */
  146. /* SPI Flash, M25P40 */
  147. {4, 27, 3, 0, 1}, /* SPI_MOSI */
  148. {4, 28, 3, 0, 1}, /* SPI_MISO */
  149. {4, 29, 3, 0, 1}, /* SPI_CLK */
  150. {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
  151. {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
  152. };
  153. void local_bus_init(void);
  154. int board_early_init_f (void)
  155. {
  156. /*
  157. * Initialize local bus.
  158. */
  159. local_bus_init ();
  160. enable_8569mds_flash_write();
  161. #ifdef CONFIG_QE
  162. enable_8569mds_qe_uec();
  163. #endif
  164. #if CONFIG_SYS_I2C2_OFFSET
  165. /* Enable I2C2 signals instead of SD signals */
  166. volatile struct ccsr_gur *gur;
  167. gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
  168. gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
  169. gur->plppar1 |= PLPPAR1_I2C2_VAL;
  170. gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
  171. gur->plpdir1 |= PLPDIR1_I2C2_VAL;
  172. disable_8569mds_brd_eeprom_write_protect();
  173. #endif
  174. return 0;
  175. }
  176. int board_early_init_r(void)
  177. {
  178. const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
  179. const u8 flash_esel = 0;
  180. /*
  181. * Remap Boot flash to caching-inhibited
  182. * so that flash can be erased properly.
  183. */
  184. /* Flush d-cache and invalidate i-cache of any FLASH data */
  185. flush_dcache();
  186. invalidate_icache();
  187. /* invalidate existing TLB entry for flash */
  188. disable_tlb(flash_esel);
  189. set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
  190. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  191. 0, flash_esel, /* ts, esel */
  192. BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
  193. return 0;
  194. }
  195. int checkboard (void)
  196. {
  197. printf ("Board: 8569 MDS\n");
  198. return 0;
  199. }
  200. #if !defined(CONFIG_SPD_EEPROM)
  201. phys_size_t fixed_sdram(void)
  202. {
  203. struct ccsr_ddr __iomem *ddr =
  204. (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  205. uint d_init;
  206. out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
  207. out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
  208. out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  209. out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  210. out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  211. out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  212. out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  213. out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
  214. out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
  215. out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
  216. out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
  217. out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
  218. out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
  219. out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
  220. out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
  221. out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
  222. out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
  223. out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
  224. #if defined (CONFIG_DDR_ECC)
  225. out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
  226. out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
  227. out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
  228. #endif
  229. udelay(500);
  230. out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
  231. #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  232. d_init = 1;
  233. debug("DDR - 1st controller: memory initializing\n");
  234. /*
  235. * Poll until memory is initialized.
  236. * 512 Meg at 400 might hit this 200 times or so.
  237. */
  238. while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
  239. udelay(1000);
  240. }
  241. debug("DDR: memory initialized\n\n");
  242. udelay(500);
  243. #endif
  244. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  245. }
  246. #endif
  247. /*
  248. * Initialize Local Bus
  249. */
  250. void
  251. local_bus_init(void)
  252. {
  253. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  254. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  255. uint clkdiv;
  256. sys_info_t sysinfo;
  257. get_sys_info(&sysinfo);
  258. clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
  259. out_be32(&gur->lbiuiplldcr1, 0x00078080);
  260. if (clkdiv == 16)
  261. out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
  262. else if (clkdiv == 8)
  263. out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
  264. else if (clkdiv == 4)
  265. out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
  266. out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
  267. }
  268. static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
  269. {
  270. const char *status = "disabled";
  271. int off;
  272. int err;
  273. off = fdt_path_offset(blob, alias);
  274. if (off < 0) {
  275. printf("WARNING: could not find %s alias: %s.\n", alias,
  276. fdt_strerror(off));
  277. return;
  278. }
  279. err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
  280. if (err) {
  281. printf("WARNING: could not set status for serial0: %s.\n",
  282. fdt_strerror(err));
  283. return;
  284. }
  285. }
  286. /*
  287. * Because of an erratum in prototype boards it is impossible to use eSDHC
  288. * without disabling UART0 (which makes it quite easy to 'brick' the board
  289. * by simply issung 'setenv hwconfig esdhc', and not able to interact with
  290. * U-Boot anylonger).
  291. *
  292. * So, but default we assume that the board is a prototype, which is a most
  293. * safe assumption. There is no way to determine board revision from a
  294. * register, so we use hwconfig.
  295. */
  296. static int prototype_board(void)
  297. {
  298. if (hwconfig_subarg("board", "rev", NULL))
  299. return hwconfig_subarg_cmp("board", "rev", "prototype");
  300. return 1;
  301. }
  302. static int esdhc_disables_uart0(void)
  303. {
  304. return prototype_board() ||
  305. hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
  306. }
  307. static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
  308. {
  309. u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  310. const char *devtype = "serial";
  311. const char *compat = "ucc_uart";
  312. const char *clk = "brg9";
  313. u32 portnum = 0;
  314. int off = -1;
  315. if (!hwconfig("qe_uart"))
  316. return;
  317. if (hwconfig("esdhc") && esdhc_disables_uart0()) {
  318. printf("QE UART: won't enable with esdhc.\n");
  319. return;
  320. }
  321. fdt_board_disable_serial(blob, bd, "serial1");
  322. while (1) {
  323. const u32 *idx;
  324. int len;
  325. off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
  326. if (off < 0) {
  327. printf("WARNING: unable to fixup device tree for "
  328. "QE UART\n");
  329. return;
  330. }
  331. idx = fdt_getprop(blob, off, "cell-index", &len);
  332. if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
  333. continue;
  334. break;
  335. }
  336. fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
  337. fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
  338. fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
  339. fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
  340. fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
  341. setbits_8(&bcsr[15], BCSR15_QEUART_EN);
  342. }
  343. #ifdef CONFIG_FSL_ESDHC
  344. int board_mmc_init(bd_t *bd)
  345. {
  346. struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  347. u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  348. u8 bcsr6 = BCSR6_SD_CARD_1BIT;
  349. if (!hwconfig("esdhc"))
  350. return 0;
  351. printf("Enabling eSDHC...\n"
  352. " For eSDHC to function, I2C2 ");
  353. if (esdhc_disables_uart0()) {
  354. printf("and UART0 should be disabled.\n");
  355. printf(" Redirecting stderr, stdout and stdin to UART1...\n");
  356. console_assign(stderr, "eserial1");
  357. console_assign(stdout, "eserial1");
  358. console_assign(stdin, "eserial1");
  359. printf("Switched to UART1 (initial log has been printed to "
  360. "UART0).\n");
  361. clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
  362. PLPPAR1_ESDHC_4BITS_VAL);
  363. clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
  364. PLPDIR1_ESDHC_4BITS_VAL);
  365. bcsr6 |= BCSR6_SD_CARD_4BITS;
  366. } else {
  367. printf("should be disabled.\n");
  368. }
  369. /* Assign I2C2 signals to eSDHC. */
  370. clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
  371. PLPPAR1_ESDHC_VAL);
  372. clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
  373. PLPDIR1_ESDHC_VAL);
  374. /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
  375. setbits_8(&bcsr[6], bcsr6);
  376. return fsl_esdhc_mmc_init(bd);
  377. }
  378. static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
  379. {
  380. const char *status = "disabled";
  381. int off = -1;
  382. if (!hwconfig("esdhc"))
  383. return;
  384. if (esdhc_disables_uart0())
  385. fdt_board_disable_serial(blob, bd, "serial0");
  386. while (1) {
  387. const u32 *idx;
  388. int len;
  389. off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
  390. if (off < 0)
  391. break;
  392. idx = fdt_getprop(blob, off, "cell-index", &len);
  393. if (!idx || len != sizeof(*idx))
  394. continue;
  395. if (*idx == 1) {
  396. fdt_setprop(blob, off, "status", status,
  397. strlen(status) + 1);
  398. break;
  399. }
  400. }
  401. if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
  402. off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
  403. if (off < 0) {
  404. printf("WARNING: could not find esdhc node\n");
  405. return;
  406. }
  407. fdt_delprop(blob, off, "sdhci,1-bit-only");
  408. }
  409. }
  410. #else
  411. static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
  412. #endif
  413. static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
  414. {
  415. u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
  416. if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
  417. clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
  418. else
  419. setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
  420. if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
  421. clrbits_8(&bcsr[17], BCSR17_USBVCC);
  422. clrbits_8(&bcsr[17], BCSR17_USBMODE);
  423. do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
  424. "peripheral", sizeof("peripheral"), 1);
  425. } else {
  426. setbits_8(&bcsr[17], BCSR17_USBVCC);
  427. setbits_8(&bcsr[17], BCSR17_USBMODE);
  428. }
  429. clrbits_8(&bcsr[17], BCSR17_nUSBEN);
  430. }
  431. #ifdef CONFIG_PCI
  432. void pci_init_board(void)
  433. {
  434. #if defined(CONFIG_PQ_MDS_PIB)
  435. pib_init();
  436. #endif
  437. fsl_pcie_init_board(0);
  438. }
  439. #endif /* CONFIG_PCI */
  440. #if defined(CONFIG_OF_BOARD_SETUP)
  441. int ft_board_setup(void *blob, bd_t *bd)
  442. {
  443. #if defined(CONFIG_SYS_UCC_RMII_MODE)
  444. int nodeoff, off, err;
  445. unsigned int val;
  446. const u32 *ph;
  447. const u32 *index;
  448. /* fixup device tree for supporting rmii mode */
  449. nodeoff = -1;
  450. while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
  451. "ucc_geth")) >= 0) {
  452. err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
  453. "clk16");
  454. if (err < 0) {
  455. printf("WARNING: could not set tx-clock-name %s.\n",
  456. fdt_strerror(err));
  457. break;
  458. }
  459. err = fdt_fixup_phy_connection(blob, nodeoff,
  460. PHY_INTERFACE_MODE_RMII);
  461. if (err < 0) {
  462. printf("WARNING: could not set phy-connection-type "
  463. "%s.\n", fdt_strerror(err));
  464. break;
  465. }
  466. index = fdt_getprop(blob, nodeoff, "cell-index", 0);
  467. if (index == NULL) {
  468. printf("WARNING: could not get cell-index of ucc\n");
  469. break;
  470. }
  471. ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
  472. if (ph == NULL) {
  473. printf("WARNING: could not get phy-handle of ucc\n");
  474. break;
  475. }
  476. off = fdt_node_offset_by_phandle(blob, *ph);
  477. if (off < 0) {
  478. printf("WARNING: could not get phy node %s.\n",
  479. fdt_strerror(err));
  480. break;
  481. }
  482. val = 0x7 + *index; /* RMII phy address starts from 0x8 */
  483. err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
  484. if (err < 0) {
  485. printf("WARNING: could not set reg for phy-handle "
  486. "%s.\n", fdt_strerror(err));
  487. break;
  488. }
  489. }
  490. #endif
  491. ft_cpu_setup(blob, bd);
  492. FT_FSL_PCI_SETUP;
  493. fdt_board_fixup_esdhc(blob, bd);
  494. fdt_board_fixup_qe_uart(blob, bd);
  495. fdt_board_fixup_qe_usb(blob, bd);
  496. return 0;
  497. }
  498. #endif