mpc8568mds.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. */
  7. #include <common.h>
  8. #include <flash.h>
  9. #include <init.h>
  10. #include <pci.h>
  11. #include <asm/processor.h>
  12. #include <asm/mmu.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_pci.h>
  15. #include <fsl_ddr_sdram.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <spd_sdram.h>
  18. #include <i2c.h>
  19. #include <ioports.h>
  20. #include <linux/libfdt.h>
  21. #include <fdt_support.h>
  22. #include "bcsr.h"
  23. const qe_iop_conf_t qe_iop_conf_tab[] = {
  24. /* GETH1 */
  25. {4, 10, 1, 0, 2}, /* TxD0 */
  26. {4, 9, 1, 0, 2}, /* TxD1 */
  27. {4, 8, 1, 0, 2}, /* TxD2 */
  28. {4, 7, 1, 0, 2}, /* TxD3 */
  29. {4, 23, 1, 0, 2}, /* TxD4 */
  30. {4, 22, 1, 0, 2}, /* TxD5 */
  31. {4, 21, 1, 0, 2}, /* TxD6 */
  32. {4, 20, 1, 0, 2}, /* TxD7 */
  33. {4, 15, 2, 0, 2}, /* RxD0 */
  34. {4, 14, 2, 0, 2}, /* RxD1 */
  35. {4, 13, 2, 0, 2}, /* RxD2 */
  36. {4, 12, 2, 0, 2}, /* RxD3 */
  37. {4, 29, 2, 0, 2}, /* RxD4 */
  38. {4, 28, 2, 0, 2}, /* RxD5 */
  39. {4, 27, 2, 0, 2}, /* RxD6 */
  40. {4, 26, 2, 0, 2}, /* RxD7 */
  41. {4, 11, 1, 0, 2}, /* TX_EN */
  42. {4, 24, 1, 0, 2}, /* TX_ER */
  43. {4, 16, 2, 0, 2}, /* RX_DV */
  44. {4, 30, 2, 0, 2}, /* RX_ER */
  45. {4, 17, 2, 0, 2}, /* RX_CLK */
  46. {4, 19, 1, 0, 2}, /* GTX_CLK */
  47. {1, 31, 2, 0, 3}, /* GTX125 */
  48. /* GETH2 */
  49. {5, 10, 1, 0, 2}, /* TxD0 */
  50. {5, 9, 1, 0, 2}, /* TxD1 */
  51. {5, 8, 1, 0, 2}, /* TxD2 */
  52. {5, 7, 1, 0, 2}, /* TxD3 */
  53. {5, 23, 1, 0, 2}, /* TxD4 */
  54. {5, 22, 1, 0, 2}, /* TxD5 */
  55. {5, 21, 1, 0, 2}, /* TxD6 */
  56. {5, 20, 1, 0, 2}, /* TxD7 */
  57. {5, 15, 2, 0, 2}, /* RxD0 */
  58. {5, 14, 2, 0, 2}, /* RxD1 */
  59. {5, 13, 2, 0, 2}, /* RxD2 */
  60. {5, 12, 2, 0, 2}, /* RxD3 */
  61. {5, 29, 2, 0, 2}, /* RxD4 */
  62. {5, 28, 2, 0, 2}, /* RxD5 */
  63. {5, 27, 2, 0, 3}, /* RxD6 */
  64. {5, 26, 2, 0, 2}, /* RxD7 */
  65. {5, 11, 1, 0, 2}, /* TX_EN */
  66. {5, 24, 1, 0, 2}, /* TX_ER */
  67. {5, 16, 2, 0, 2}, /* RX_DV */
  68. {5, 30, 2, 0, 2}, /* RX_ER */
  69. {5, 17, 2, 0, 2}, /* RX_CLK */
  70. {5, 19, 1, 0, 2}, /* GTX_CLK */
  71. {1, 31, 2, 0, 3}, /* GTX125 */
  72. {4, 6, 3, 0, 2}, /* MDIO */
  73. {4, 5, 1, 0, 2}, /* MDC */
  74. /* UART1 */
  75. {2, 0, 1, 0, 2}, /* UART_SOUT1 */
  76. {2, 1, 1, 0, 2}, /* UART_RTS1 */
  77. {2, 2, 2, 0, 2}, /* UART_CTS1 */
  78. {2, 3, 2, 0, 2}, /* UART_SIN1 */
  79. {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  80. };
  81. void local_bus_init(void);
  82. int board_early_init_f (void)
  83. {
  84. /*
  85. * Initialize local bus.
  86. */
  87. local_bus_init ();
  88. enable_8568mds_duart();
  89. enable_8568mds_flash_write();
  90. #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
  91. reset_8568mds_uccs();
  92. #endif
  93. #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
  94. enable_8568mds_qe_mdio();
  95. #endif
  96. #ifdef CONFIG_SYS_I2C2_OFFSET
  97. /* Enable I2C2_SCL and I2C2_SDA */
  98. volatile struct par_io *port_c;
  99. port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
  100. port_c->cpdir2 |= 0x0f000000;
  101. port_c->cppar2 &= ~0x0f000000;
  102. port_c->cppar2 |= 0x0a000000;
  103. #endif
  104. return 0;
  105. }
  106. int checkboard (void)
  107. {
  108. printf ("Board: 8568 MDS\n");
  109. return 0;
  110. }
  111. /*
  112. * Initialize Local Bus
  113. */
  114. void
  115. local_bus_init(void)
  116. {
  117. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  118. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  119. uint clkdiv;
  120. sys_info_t sysinfo;
  121. get_sys_info(&sysinfo);
  122. clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
  123. gur->lbiuiplldcr1 = 0x00078080;
  124. if (clkdiv == 16) {
  125. gur->lbiuiplldcr0 = 0x7c0f1bf0;
  126. } else if (clkdiv == 8) {
  127. gur->lbiuiplldcr0 = 0x6c0f1bf0;
  128. } else if (clkdiv == 4) {
  129. gur->lbiuiplldcr0 = 0x5c0f1bf0;
  130. }
  131. lbc->lcrr |= 0x00030000;
  132. asm("sync;isync;msync");
  133. }
  134. /*
  135. * Initialize SDRAM memory on the Local Bus.
  136. */
  137. void lbc_sdram_init(void)
  138. {
  139. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  140. uint idx;
  141. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  142. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  143. uint lsdmr_common;
  144. puts("LBC SDRAM: ");
  145. print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
  146. "\n ");
  147. /*
  148. * Setup SDRAM Base and Option Registers
  149. */
  150. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  151. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  152. asm("msync");
  153. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  154. asm("msync");
  155. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  156. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  157. asm("msync");
  158. /*
  159. * MPC8568 uses "new" 15-16 style addressing.
  160. */
  161. lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
  162. lsdmr_common |= LSDMR_BSMA1516;
  163. /*
  164. * Issue PRECHARGE ALL command.
  165. */
  166. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  167. asm("sync;msync");
  168. *sdram_addr = 0xff;
  169. ppcDcbf((unsigned long) sdram_addr);
  170. udelay(100);
  171. /*
  172. * Issue 8 AUTO REFRESH commands.
  173. */
  174. for (idx = 0; idx < 8; idx++) {
  175. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  176. asm("sync;msync");
  177. *sdram_addr = 0xff;
  178. ppcDcbf((unsigned long) sdram_addr);
  179. udelay(100);
  180. }
  181. /*
  182. * Issue 8 MODE-set command.
  183. */
  184. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  185. asm("sync;msync");
  186. *sdram_addr = 0xff;
  187. ppcDcbf((unsigned long) sdram_addr);
  188. udelay(100);
  189. /*
  190. * Issue NORMAL OP command.
  191. */
  192. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  193. asm("sync;msync");
  194. *sdram_addr = 0xff;
  195. ppcDcbf((unsigned long) sdram_addr);
  196. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  197. #endif /* enable SDRAM init */
  198. }
  199. #if defined(CONFIG_PCI)
  200. #ifndef CONFIG_PCI_PNP
  201. static struct pci_config_table pci_mpc8568mds_config_table[] = {
  202. {
  203. PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  204. pci_cfgfunc_config_device,
  205. {PCI_ENET0_IOADDR,
  206. PCI_ENET0_MEMADDR,
  207. PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
  208. },
  209. {}
  210. };
  211. #endif
  212. static struct pci_controller pci1_hose;
  213. #endif /* CONFIG_PCI */
  214. /*
  215. * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
  216. */
  217. void
  218. pib_init(void)
  219. {
  220. u8 val8, orig_i2c_bus;
  221. /*
  222. * Assign PIB PMC2/3 to PCI bus
  223. */
  224. /*switch temporarily to I2C bus #2 */
  225. orig_i2c_bus = i2c_get_bus_num();
  226. i2c_set_bus_num(1);
  227. val8 = 0x00;
  228. i2c_write(0x23, 0x6, 1, &val8, 1);
  229. i2c_write(0x23, 0x7, 1, &val8, 1);
  230. val8 = 0xff;
  231. i2c_write(0x23, 0x2, 1, &val8, 1);
  232. i2c_write(0x23, 0x3, 1, &val8, 1);
  233. val8 = 0x00;
  234. i2c_write(0x26, 0x6, 1, &val8, 1);
  235. val8 = 0x34;
  236. i2c_write(0x26, 0x7, 1, &val8, 1);
  237. val8 = 0xf9;
  238. i2c_write(0x26, 0x2, 1, &val8, 1);
  239. val8 = 0xff;
  240. i2c_write(0x26, 0x3, 1, &val8, 1);
  241. val8 = 0x00;
  242. i2c_write(0x27, 0x6, 1, &val8, 1);
  243. i2c_write(0x27, 0x7, 1, &val8, 1);
  244. val8 = 0xff;
  245. i2c_write(0x27, 0x2, 1, &val8, 1);
  246. val8 = 0xef;
  247. i2c_write(0x27, 0x3, 1, &val8, 1);
  248. asm("eieio");
  249. i2c_set_bus_num(orig_i2c_bus);
  250. }
  251. #ifdef CONFIG_PCI
  252. void pci_init_board(void)
  253. {
  254. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  255. int first_free_busno = 0;
  256. #ifdef CONFIG_PCI1
  257. struct fsl_pci_info pci_info;
  258. u32 devdisr, pordevsr, io_sel;
  259. u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
  260. devdisr = in_be32(&gur->devdisr);
  261. pordevsr = in_be32(&gur->pordevsr);
  262. porpllsr = in_be32(&gur->porpllsr);
  263. io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
  264. debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
  265. pci_speed = 66666000;
  266. pci_32 = 1;
  267. pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  268. pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  269. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  270. SET_STD_PCI_INFO(pci_info, 1);
  271. set_next_law(pci_info.mem_phys,
  272. law_size_bits(pci_info.mem_size), pci_info.law);
  273. set_next_law(pci_info.io_phys,
  274. law_size_bits(pci_info.io_size), pci_info.law);
  275. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  276. printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  277. (pci_32) ? 32 : 64,
  278. (pci_speed == 33333000) ? "33" :
  279. (pci_speed == 66666000) ? "66" : "unknown",
  280. pci_clk_sel ? "sync" : "async",
  281. pci_agent ? "agent" : "host",
  282. pci_arb ? "arbiter" : "external-arbiter",
  283. pci_info.regs);
  284. #ifndef CONFIG_PCI_PNP
  285. pci1_hose.config_table = pci_mpc8568mds_config_table;
  286. #endif
  287. first_free_busno = fsl_pci_init_port(&pci_info,
  288. &pci1_hose, first_free_busno);
  289. } else {
  290. printf("PCI: disabled\n");
  291. }
  292. puts("\n");
  293. #else
  294. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  295. #endif
  296. fsl_pcie_init_board(first_free_busno);
  297. }
  298. #endif /* CONFIG_PCI */
  299. #if defined(CONFIG_OF_BOARD_SETUP)
  300. int ft_board_setup(void *blob, bd_t *bd)
  301. {
  302. ft_cpu_setup(blob, bd);
  303. FT_FSL_PCI_SETUP;
  304. return 0;
  305. }
  306. #endif