at91sam9263ek.c 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. */
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <flash.h>
  10. #include <init.h>
  11. #include <net.h>
  12. #include <vsprintf.h>
  13. #include <linux/sizes.h>
  14. #include <asm/arch/at91sam9263.h>
  15. #include <asm/arch/at91sam9_smc.h>
  16. #include <asm/arch/at91_common.h>
  17. #include <asm/arch/at91_matrix.h>
  18. #include <asm/arch/at91_pio.h>
  19. #include <asm/arch/clk.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/hardware.h>
  23. #include <lcd.h>
  24. #include <atmel_lcdc.h>
  25. #include <asm/mach-types.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* ------------------------------------------------------------------------- */
  28. /*
  29. * Miscelaneous platform dependent initialisations
  30. */
  31. #ifdef CONFIG_CMD_NAND
  32. static void at91sam9263ek_nand_hw_init(void)
  33. {
  34. unsigned long csa;
  35. at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
  36. at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  37. /* Enable CS3 */
  38. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  39. writel(csa, &matrix->csa[0]);
  40. /* Enable CS3 */
  41. /* Configure SMC CS3 for NAND/SmartMedia */
  42. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  43. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  44. &smc->cs[3].setup);
  45. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  46. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  47. &smc->cs[3].pulse);
  48. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  49. &smc->cs[3].cycle);
  50. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  51. AT91_SMC_MODE_EXNW_DISABLE |
  52. #ifdef CONFIG_SYS_NAND_DBW_16
  53. AT91_SMC_MODE_DBW_16 |
  54. #else /* CONFIG_SYS_NAND_DBW_8 */
  55. AT91_SMC_MODE_DBW_8 |
  56. #endif
  57. AT91_SMC_MODE_TDF_CYCLE(2),
  58. &smc->cs[3].mode);
  59. at91_periph_clk_enable(ATMEL_ID_PIOA);
  60. at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  61. /* Configure RDY/BSY */
  62. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  63. /* Enable NandFlash */
  64. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  65. }
  66. #endif
  67. #ifdef CONFIG_LCD
  68. vidinfo_t panel_info = {
  69. .vl_col = 240,
  70. .vl_row = 320,
  71. .vl_clk = 4965000,
  72. .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
  73. ATMEL_LCDC_INVFRAME_INVERTED,
  74. .vl_bpix = 3,
  75. .vl_tft = 1,
  76. .vl_hsync_len = 5,
  77. .vl_left_margin = 1,
  78. .vl_right_margin = 33,
  79. .vl_vsync_len = 1,
  80. .vl_upper_margin = 1,
  81. .vl_lower_margin = 0,
  82. .mmio = ATMEL_BASE_LCDC,
  83. };
  84. void lcd_enable(void)
  85. {
  86. at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
  87. }
  88. void lcd_disable(void)
  89. {
  90. at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
  91. }
  92. static void at91sam9263ek_lcd_hw_init(void)
  93. {
  94. at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
  95. at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
  96. at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
  97. at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
  98. at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
  99. at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
  100. at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
  101. at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
  102. at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
  103. at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
  104. at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
  105. at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
  106. at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
  107. at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
  108. at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
  109. at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
  110. at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
  111. at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
  112. at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
  113. at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
  114. at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
  115. at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
  116. at91_periph_clk_enable(ATMEL_ID_LCDC);
  117. gd->fb_base = ATMEL_BASE_SRAM0;
  118. }
  119. #ifdef CONFIG_LCD_INFO
  120. #include <nand.h>
  121. #include <version.h>
  122. #ifdef CONFIG_MTD_NOR_FLASH
  123. extern flash_info_t flash_info[];
  124. #endif
  125. void lcd_show_board_info(void)
  126. {
  127. ulong dram_size, nand_size;
  128. #ifdef CONFIG_MTD_NOR_FLASH
  129. ulong flash_size;
  130. #endif
  131. int i;
  132. char temp[32];
  133. lcd_printf ("%s\n", U_BOOT_VERSION);
  134. lcd_printf ("(C) 2008 ATMEL Corp\n");
  135. lcd_printf ("at91support@atmel.com\n");
  136. lcd_printf ("%s CPU at %s MHz\n",
  137. ATMEL_CPU_NAME,
  138. strmhz(temp, get_cpu_clk_rate()));
  139. dram_size = 0;
  140. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  141. dram_size += gd->bd->bi_dram[i].size;
  142. nand_size = 0;
  143. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  144. nand_size += get_nand_dev_by_index(i)->size;
  145. #ifdef CONFIG_MTD_NOR_FLASH
  146. flash_size = 0;
  147. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
  148. flash_size += flash_info[i].size;
  149. #endif
  150. lcd_printf (" %ld MB SDRAM, %ld MB NAND",
  151. dram_size >> 20,
  152. nand_size >> 20 );
  153. #ifdef CONFIG_MTD_NOR_FLASH
  154. lcd_printf (",\n %ld MB NOR",
  155. flash_size >> 20);
  156. #endif
  157. lcd_puts ("\n");
  158. }
  159. #endif /* CONFIG_LCD_INFO */
  160. #endif
  161. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  162. void board_debug_uart_init(void)
  163. {
  164. at91_seriald_hw_init();
  165. }
  166. #endif
  167. #ifdef CONFIG_BOARD_EARLY_INIT_F
  168. int board_early_init_f(void)
  169. {
  170. #ifdef CONFIG_DEBUG_UART
  171. debug_uart_init();
  172. #endif
  173. return 0;
  174. }
  175. #endif
  176. int board_init(void)
  177. {
  178. /* arch number of AT91SAM9263EK-Board */
  179. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
  180. /* adress of boot parameters */
  181. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  182. #ifdef CONFIG_CMD_NAND
  183. at91sam9263ek_nand_hw_init();
  184. #endif
  185. #ifdef CONFIG_USB_OHCI_NEW
  186. at91_uhp_hw_init();
  187. #endif
  188. #ifdef CONFIG_LCD
  189. at91sam9263ek_lcd_hw_init();
  190. #endif
  191. return 0;
  192. }
  193. int dram_init(void)
  194. {
  195. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  196. CONFIG_SYS_SDRAM_SIZE);
  197. return 0;
  198. }
  199. #ifdef CONFIG_RESET_PHY_R
  200. void reset_phy(void)
  201. {
  202. }
  203. #endif