stm32mp157c-ed1-u-boot.dtsi 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp15-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  8. / {
  9. aliases {
  10. i2c3 = &i2c4;
  11. };
  12. config {
  13. u-boot,boot-led = "heartbeat";
  14. u-boot,error-led = "error";
  15. u-boot,mmc-env-partition = "fip";
  16. st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  17. st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  18. };
  19. #ifdef CONFIG_STM32MP15x_STM32IMAGE
  20. config {
  21. u-boot,mmc-env-partition = "ssbl";
  22. };
  23. /* only needed for boot with TF-A, witout FIP support */
  24. firmware {
  25. optee {
  26. compatible = "linaro,optee-tz";
  27. method = "smc";
  28. };
  29. };
  30. reserved-memory {
  31. optee@fe000000 {
  32. reg = <0xfe000000 0x02000000>;
  33. no-map;
  34. };
  35. };
  36. #endif
  37. led {
  38. red {
  39. label = "error";
  40. gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  41. default-state = "off";
  42. status = "okay";
  43. };
  44. };
  45. };
  46. &clk_hse {
  47. st,digbypass;
  48. };
  49. &i2c4 {
  50. u-boot,dm-pre-reloc;
  51. };
  52. &i2c4_pins_a {
  53. u-boot,dm-pre-reloc;
  54. pins {
  55. u-boot,dm-pre-reloc;
  56. };
  57. };
  58. &pmic {
  59. u-boot,dm-pre-reloc;
  60. };
  61. &rcc {
  62. st,clksrc = <
  63. CLK_MPU_PLL1P
  64. CLK_AXI_PLL2P
  65. CLK_MCU_PLL3P
  66. CLK_PLL12_HSE
  67. CLK_PLL3_HSE
  68. CLK_PLL4_HSE
  69. CLK_RTC_LSE
  70. CLK_MCO1_DISABLED
  71. CLK_MCO2_DISABLED
  72. >;
  73. st,clkdiv = <
  74. 1 /*MPU*/
  75. 0 /*AXI*/
  76. 0 /*MCU*/
  77. 1 /*APB1*/
  78. 1 /*APB2*/
  79. 1 /*APB3*/
  80. 1 /*APB4*/
  81. 2 /*APB5*/
  82. 23 /*RTC*/
  83. 0 /*MCO1*/
  84. 0 /*MCO2*/
  85. >;
  86. st,pkcs = <
  87. CLK_CKPER_HSE
  88. CLK_FMC_ACLK
  89. CLK_QSPI_ACLK
  90. CLK_ETH_DISABLED
  91. CLK_SDMMC12_PLL4P
  92. CLK_DSI_DSIPLL
  93. CLK_STGEN_HSE
  94. CLK_USBPHY_HSE
  95. CLK_SPI2S1_PLL3Q
  96. CLK_SPI2S23_PLL3Q
  97. CLK_SPI45_HSI
  98. CLK_SPI6_HSI
  99. CLK_I2C46_HSI
  100. CLK_SDMMC3_PLL4P
  101. CLK_USBO_USBPHY
  102. CLK_ADC_CKPER
  103. CLK_CEC_LSE
  104. CLK_I2C12_HSI
  105. CLK_I2C35_HSI
  106. CLK_UART1_HSI
  107. CLK_UART24_HSI
  108. CLK_UART35_HSI
  109. CLK_UART6_HSI
  110. CLK_UART78_HSI
  111. CLK_SPDIF_PLL4P
  112. CLK_FDCAN_PLL4R
  113. CLK_SAI1_PLL3Q
  114. CLK_SAI2_PLL3Q
  115. CLK_SAI3_PLL3Q
  116. CLK_SAI4_PLL3Q
  117. CLK_RNG1_LSI
  118. CLK_RNG2_LSI
  119. CLK_LPTIM1_PCLK1
  120. CLK_LPTIM23_PCLK3
  121. CLK_LPTIM45_LSE
  122. >;
  123. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  124. pll2: st,pll@1 {
  125. compatible = "st,stm32mp1-pll";
  126. reg = <1>;
  127. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  128. frac = < 0x1400 >;
  129. u-boot,dm-pre-reloc;
  130. };
  131. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  132. pll3: st,pll@2 {
  133. compatible = "st,stm32mp1-pll";
  134. reg = <2>;
  135. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  136. frac = < 0x1a04 >;
  137. u-boot,dm-pre-reloc;
  138. };
  139. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  140. pll4: st,pll@3 {
  141. compatible = "st,stm32mp1-pll";
  142. reg = <3>;
  143. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  144. u-boot,dm-pre-reloc;
  145. };
  146. };
  147. &sdmmc1 {
  148. u-boot,dm-spl;
  149. };
  150. &sdmmc1_b4_pins_a {
  151. u-boot,dm-spl;
  152. pins1 {
  153. u-boot,dm-spl;
  154. };
  155. pins2 {
  156. u-boot,dm-spl;
  157. };
  158. };
  159. &sdmmc1_dir_pins_a {
  160. u-boot,dm-spl;
  161. pins1 {
  162. u-boot,dm-spl;
  163. };
  164. pins2 {
  165. u-boot,dm-spl;
  166. };
  167. };
  168. &sdmmc2 {
  169. u-boot,dm-spl;
  170. };
  171. &sdmmc2_b4_pins_a {
  172. u-boot,dm-spl;
  173. pins1 {
  174. u-boot,dm-spl;
  175. };
  176. pins2 {
  177. u-boot,dm-spl;
  178. };
  179. };
  180. &sdmmc2_d47_pins_a {
  181. u-boot,dm-spl;
  182. pins {
  183. u-boot,dm-spl;
  184. };
  185. };
  186. &uart4 {
  187. u-boot,dm-pre-reloc;
  188. };
  189. &uart4_pins_a {
  190. u-boot,dm-pre-reloc;
  191. pins1 {
  192. u-boot,dm-pre-reloc;
  193. };
  194. pins2 {
  195. u-boot,dm-pre-reloc;
  196. /* pull-up on rx to avoid floating level */
  197. bias-pull-up;
  198. };
  199. };