stm32mp157a-dk1-u-boot.dtsi 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp15-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
  8. / {
  9. aliases {
  10. i2c3 = &i2c4;
  11. usb0 = &usbotg_hs;
  12. };
  13. config {
  14. u-boot,boot-led = "heartbeat";
  15. u-boot,error-led = "error";
  16. u-boot,mmc-env-partition = "fip";
  17. st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
  18. st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  19. st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  20. };
  21. #ifdef CONFIG_STM32MP15x_STM32IMAGE
  22. config {
  23. u-boot,mmc-env-partition = "ssbl";
  24. };
  25. /* only needed for boot with TF-A, witout FIP support */
  26. firmware {
  27. optee {
  28. compatible = "linaro,optee-tz";
  29. method = "smc";
  30. };
  31. };
  32. reserved-memory {
  33. u-boot,dm-spl;
  34. optee@de000000 {
  35. reg = <0xde000000 0x02000000>;
  36. no-map;
  37. u-boot,dm-spl;
  38. };
  39. };
  40. #endif
  41. led {
  42. red {
  43. label = "error";
  44. gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  45. default-state = "off";
  46. status = "okay";
  47. };
  48. };
  49. };
  50. &adc {
  51. status = "okay";
  52. };
  53. &clk_hse {
  54. st,digbypass;
  55. };
  56. &i2c4 {
  57. u-boot,dm-pre-reloc;
  58. };
  59. &i2c4_pins_a {
  60. u-boot,dm-pre-reloc;
  61. pins {
  62. u-boot,dm-pre-reloc;
  63. };
  64. };
  65. &pmic {
  66. u-boot,dm-pre-reloc;
  67. };
  68. &rcc {
  69. st,clksrc = <
  70. CLK_MPU_PLL1P
  71. CLK_AXI_PLL2P
  72. CLK_MCU_PLL3P
  73. CLK_PLL12_HSE
  74. CLK_PLL3_HSE
  75. CLK_PLL4_HSE
  76. CLK_RTC_LSE
  77. CLK_MCO1_DISABLED
  78. CLK_MCO2_DISABLED
  79. >;
  80. st,clkdiv = <
  81. 1 /*MPU*/
  82. 0 /*AXI*/
  83. 0 /*MCU*/
  84. 1 /*APB1*/
  85. 1 /*APB2*/
  86. 1 /*APB3*/
  87. 1 /*APB4*/
  88. 2 /*APB5*/
  89. 23 /*RTC*/
  90. 0 /*MCO1*/
  91. 0 /*MCO2*/
  92. >;
  93. st,pkcs = <
  94. CLK_CKPER_HSE
  95. CLK_FMC_ACLK
  96. CLK_QSPI_ACLK
  97. CLK_ETH_DISABLED
  98. CLK_SDMMC12_PLL4P
  99. CLK_DSI_DSIPLL
  100. CLK_STGEN_HSE
  101. CLK_USBPHY_HSE
  102. CLK_SPI2S1_PLL3Q
  103. CLK_SPI2S23_PLL3Q
  104. CLK_SPI45_HSI
  105. CLK_SPI6_HSI
  106. CLK_I2C46_HSI
  107. CLK_SDMMC3_PLL4P
  108. CLK_USBO_USBPHY
  109. CLK_ADC_CKPER
  110. CLK_CEC_LSE
  111. CLK_I2C12_HSI
  112. CLK_I2C35_HSI
  113. CLK_UART1_HSI
  114. CLK_UART24_HSI
  115. CLK_UART35_HSI
  116. CLK_UART6_HSI
  117. CLK_UART78_HSI
  118. CLK_SPDIF_PLL4P
  119. CLK_FDCAN_PLL4R
  120. CLK_SAI1_PLL3Q
  121. CLK_SAI2_PLL3Q
  122. CLK_SAI3_PLL3Q
  123. CLK_SAI4_PLL3Q
  124. CLK_RNG1_LSI
  125. CLK_RNG2_LSI
  126. CLK_LPTIM1_PCLK1
  127. CLK_LPTIM23_PCLK3
  128. CLK_LPTIM45_LSE
  129. >;
  130. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  131. pll2: st,pll@1 {
  132. compatible = "st,stm32mp1-pll";
  133. reg = <1>;
  134. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  135. frac = < 0x1400 >;
  136. u-boot,dm-pre-reloc;
  137. };
  138. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  139. pll3: st,pll@2 {
  140. compatible = "st,stm32mp1-pll";
  141. reg = <2>;
  142. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  143. frac = < 0x1a04 >;
  144. u-boot,dm-pre-reloc;
  145. };
  146. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  147. pll4: st,pll@3 {
  148. compatible = "st,stm32mp1-pll";
  149. reg = <3>;
  150. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  151. u-boot,dm-pre-reloc;
  152. };
  153. };
  154. &sdmmc1 {
  155. u-boot,dm-spl;
  156. };
  157. &sdmmc1_b4_pins_a {
  158. u-boot,dm-spl;
  159. pins1 {
  160. u-boot,dm-spl;
  161. };
  162. pins2 {
  163. u-boot,dm-spl;
  164. };
  165. };
  166. &uart4 {
  167. u-boot,dm-pre-reloc;
  168. };
  169. &uart4_pins_a {
  170. u-boot,dm-pre-reloc;
  171. pins1 {
  172. u-boot,dm-pre-reloc;
  173. };
  174. pins2 {
  175. u-boot,dm-pre-reloc;
  176. /* pull-up on rx to avoid floating level */
  177. bias-pull-up;
  178. };
  179. };
  180. &usbotg_hs {
  181. u-boot,force-b-session-valid;
  182. };