armada-37xx-wdt.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell Armada 37xx SoC Watchdog Driver
  4. *
  5. * Marek Behun <marek.behun@nic.cz>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <wdt.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <dm/device_compat.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct a37xx_wdt {
  17. void __iomem *sel_reg;
  18. void __iomem *reg;
  19. ulong clk_rate;
  20. u64 timeout;
  21. };
  22. /*
  23. * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
  24. */
  25. #define CNTR_CTRL(id) ((id) * 0x10)
  26. #define CNTR_CTRL_ENABLE 0x0001
  27. #define CNTR_CTRL_ACTIVE 0x0002
  28. #define CNTR_CTRL_MODE_MASK 0x000c
  29. #define CNTR_CTRL_MODE_ONESHOT 0x0000
  30. #define CNTR_CTRL_MODE_HWSIG 0x000c
  31. #define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
  32. #define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
  33. #define CNTR_CTRL_PRESCALE_MASK 0xff00
  34. #define CNTR_CTRL_PRESCALE_MIN 2
  35. #define CNTR_CTRL_PRESCALE_SHIFT 8
  36. #define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
  37. #define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
  38. static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val)
  39. {
  40. writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id));
  41. writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id));
  42. }
  43. static void counter_enable(struct a37xx_wdt *priv, int id)
  44. {
  45. setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
  46. }
  47. static void counter_disable(struct a37xx_wdt *priv, int id)
  48. {
  49. clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
  50. }
  51. static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
  52. {
  53. u32 reg;
  54. reg = readl(priv->reg + CNTR_CTRL(id));
  55. if (reg & CNTR_CTRL_ACTIVE)
  56. return -EBUSY;
  57. reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
  58. CNTR_CTRL_TRIG_SRC_MASK);
  59. /* set mode */
  60. reg |= mode;
  61. /* set prescaler to the min value */
  62. reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
  63. /* set trigger source */
  64. reg |= trig_src;
  65. writel(reg, priv->reg + CNTR_CTRL(id));
  66. return 0;
  67. }
  68. static int a37xx_wdt_reset(struct udevice *dev)
  69. {
  70. struct a37xx_wdt *priv = dev_get_priv(dev);
  71. if (!priv->timeout)
  72. return -EINVAL;
  73. /* counter 1 is retriggered by forcing end count on counter 0 */
  74. counter_disable(priv, 0);
  75. counter_enable(priv, 0);
  76. return 0;
  77. }
  78. static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)
  79. {
  80. struct a37xx_wdt *priv = dev_get_priv(dev);
  81. /* first we set timeout to 0 */
  82. counter_disable(priv, 1);
  83. set_counter_value(priv, 1, 0);
  84. counter_enable(priv, 1);
  85. /* and then we start counter 1 by forcing end count on counter 0 */
  86. counter_disable(priv, 0);
  87. counter_enable(priv, 0);
  88. return 0;
  89. }
  90. static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
  91. {
  92. struct a37xx_wdt *priv = dev_get_priv(dev);
  93. int err;
  94. err = init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
  95. if (err < 0)
  96. return err;
  97. err = init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG,
  98. CNTR_CTRL_TRIG_SRC_PREV_CNTR);
  99. if (err < 0)
  100. return err;
  101. priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
  102. set_counter_value(priv, 0, 0);
  103. set_counter_value(priv, 1, priv->timeout);
  104. counter_enable(priv, 1);
  105. /* we have to force end count on counter 0 to start counter 1 */
  106. counter_enable(priv, 0);
  107. return 0;
  108. }
  109. static int a37xx_wdt_stop(struct udevice *dev)
  110. {
  111. struct a37xx_wdt *priv = dev_get_priv(dev);
  112. counter_disable(priv, 1);
  113. counter_disable(priv, 0);
  114. writel(0, priv->sel_reg);
  115. return 0;
  116. }
  117. static int a37xx_wdt_probe(struct udevice *dev)
  118. {
  119. struct a37xx_wdt *priv = dev_get_priv(dev);
  120. fdt_addr_t addr;
  121. addr = dev_read_addr_index(dev, 0);
  122. if (addr == FDT_ADDR_T_NONE)
  123. goto err;
  124. priv->sel_reg = (void __iomem *)addr;
  125. addr = dev_read_addr_index(dev, 1);
  126. if (addr == FDT_ADDR_T_NONE)
  127. goto err;
  128. priv->reg = (void __iomem *)addr;
  129. priv->clk_rate = (ulong)get_ref_clk() * 1000000;
  130. /*
  131. * We use counter 1 as watchdog timer, therefore we only set bit
  132. * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on
  133. * counter 1.
  134. */
  135. writel(1 << 1, priv->sel_reg);
  136. return 0;
  137. err:
  138. dev_err(dev, "no io address\n");
  139. return -ENODEV;
  140. }
  141. static const struct wdt_ops a37xx_wdt_ops = {
  142. .start = a37xx_wdt_start,
  143. .reset = a37xx_wdt_reset,
  144. .stop = a37xx_wdt_stop,
  145. .expire_now = a37xx_wdt_expire_now,
  146. };
  147. static const struct udevice_id a37xx_wdt_ids[] = {
  148. { .compatible = "marvell,armada-3700-wdt" },
  149. {}
  150. };
  151. U_BOOT_DRIVER(a37xx_wdt) = {
  152. .name = "armada_37xx_wdt",
  153. .id = UCLASS_WDT,
  154. .of_match = a37xx_wdt_ids,
  155. .probe = a37xx_wdt_probe,
  156. .priv_auto = sizeof(struct a37xx_wdt),
  157. .ops = &a37xx_wdt_ops,
  158. };