imx_tmu.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017~2020 NXP
  4. *
  5. */
  6. #include <config.h>
  7. #include <common.h>
  8. #include <asm/global_data.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/device.h>
  15. #include <errno.h>
  16. #include <fuse.h>
  17. #include <linux/delay.h>
  18. #include <malloc.h>
  19. #include <thermal.h>
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #define SITES_MAX 16
  22. #define FLAGS_VER2 0x1
  23. #define FLAGS_VER3 0x2
  24. #define TMR_DISABLE 0x0
  25. #define TMR_ME 0x80000000
  26. #define TMR_ALPF 0x0c000000
  27. #define TMTMIR_DEFAULT 0x00000002
  28. #define TIER_DISABLE 0x0
  29. #define TER_EN 0x80000000
  30. #define TER_ADC_PD 0x40000000
  31. #define TER_ALPF 0x3
  32. /*
  33. * i.MX TMU Registers
  34. */
  35. struct imx_tmu_site_regs {
  36. u32 tritsr; /* Immediate Temperature Site Register */
  37. u32 tratsr; /* Average Temperature Site Register */
  38. u8 res0[0x8];
  39. };
  40. struct imx_tmu_regs {
  41. u32 tmr; /* Mode Register */
  42. u32 tsr; /* Status Register */
  43. u32 tmtmir; /* Temperature measurement interval Register */
  44. u8 res0[0x14];
  45. u32 tier; /* Interrupt Enable Register */
  46. u32 tidr; /* Interrupt Detect Register */
  47. u32 tiscr; /* Interrupt Site Capture Register */
  48. u32 ticscr; /* Interrupt Critical Site Capture Register */
  49. u8 res1[0x10];
  50. u32 tmhtcrh; /* High Temperature Capture Register */
  51. u32 tmhtcrl; /* Low Temperature Capture Register */
  52. u8 res2[0x8];
  53. u32 tmhtitr; /* High Temperature Immediate Threshold */
  54. u32 tmhtatr; /* High Temperature Average Threshold */
  55. u32 tmhtactr; /* High Temperature Average Crit Threshold */
  56. u8 res3[0x24];
  57. u32 ttcfgr; /* Temperature Configuration Register */
  58. u32 tscfgr; /* Sensor Configuration Register */
  59. u8 res4[0x78];
  60. struct imx_tmu_site_regs site[SITES_MAX];
  61. u8 res5[0x9f8];
  62. u32 ipbrr0; /* IP Block Revision Register 0 */
  63. u32 ipbrr1; /* IP Block Revision Register 1 */
  64. u8 res6[0x310];
  65. u32 ttr0cr; /* Temperature Range 0 Control Register */
  66. u32 ttr1cr; /* Temperature Range 1 Control Register */
  67. u32 ttr2cr; /* Temperature Range 2 Control Register */
  68. u32 ttr3cr; /* Temperature Range 3 Control Register */
  69. };
  70. struct imx_tmu_regs_v2 {
  71. u32 ter; /* TMU enable Register */
  72. u32 tsr; /* Status Register */
  73. u32 tier; /* Interrupt enable register */
  74. u32 tidr; /* Interrupt detect register */
  75. u32 tmhtitr; /* Monitor high temperature immediate threshold register */
  76. u32 tmhtatr; /* Monitor high temperature average threshold register */
  77. u32 tmhtactr; /* TMU monitor high temperature average critical threshold register */
  78. u32 tscr; /* Sensor value capture register */
  79. u32 tritsr; /* Report immediate temperature site register 0 */
  80. u32 tratsr; /* Report average temperature site register 0 */
  81. u32 tasr; /* Amplifier setting register */
  82. u32 ttmc; /* Test MUX control */
  83. u32 tcaliv;
  84. };
  85. struct imx_tmu_regs_v3 {
  86. u32 ter; /* TMU enable Register */
  87. u32 tps; /* Status Register */
  88. u32 tier; /* Interrupt enable register */
  89. u32 tidr; /* Interrupt detect register */
  90. u32 tmhtitr; /* Monitor high temperature immediate threshold register */
  91. u32 tmhtatr; /* Monitor high temperature average threshold register */
  92. u32 tmhtactr; /* TMU monitor high temperature average critical threshold register */
  93. u32 tscr; /* Sensor value capture register */
  94. u32 tritsr; /* Report immediate temperature site register 0 */
  95. u32 tratsr; /* Report average temperature site register 0 */
  96. u32 tasr; /* Amplifier setting register */
  97. u32 ttmc; /* Test MUX control */
  98. u32 tcaliv0;
  99. u32 tcaliv1;
  100. u32 tcaliv_m40;
  101. u32 trim;
  102. };
  103. union tmu_regs {
  104. struct imx_tmu_regs regs_v1;
  105. struct imx_tmu_regs_v2 regs_v2;
  106. struct imx_tmu_regs_v3 regs_v3;
  107. };
  108. struct imx_tmu_plat {
  109. int critical;
  110. int alert;
  111. int polling_delay;
  112. int id;
  113. bool zone_node;
  114. union tmu_regs *regs;
  115. };
  116. static int read_temperature(struct udevice *dev, int *temp)
  117. {
  118. struct imx_tmu_plat *pdata = dev_get_plat(dev);
  119. ulong drv_data = dev_get_driver_data(dev);
  120. u32 val;
  121. u32 retry = 10;
  122. u32 valid = 0;
  123. do {
  124. mdelay(100);
  125. retry--;
  126. if (drv_data & FLAGS_VER3) {
  127. val = readl(&pdata->regs->regs_v3.tritsr);
  128. valid = val & (1 << (30 + pdata->id));
  129. } else if (drv_data & FLAGS_VER2) {
  130. val = readl(&pdata->regs->regs_v2.tritsr);
  131. /*
  132. * Check if TEMP is in valid range, the V bit in TRITSR
  133. * only reflects the RAW uncalibrated data
  134. */
  135. valid = ((val & 0xff) < 10 || (val & 0xff) > 125) ? 0 : 1;
  136. } else {
  137. val = readl(&pdata->regs->regs_v1.site[pdata->id].tritsr);
  138. valid = val & 0x80000000;
  139. }
  140. } while (!valid && retry > 0);
  141. if (retry > 0) {
  142. if (drv_data & FLAGS_VER3) {
  143. val = (val >> (pdata->id * 16)) & 0xff;
  144. if (val & 0x80) /* Negative */
  145. val = (~(val & 0x7f) + 1);
  146. *temp = val;
  147. if (*temp < -40 || *temp > 125) /* Check the range */
  148. return -EINVAL;
  149. *temp *= 1000;
  150. } else {
  151. *temp = (val & 0xff) * 1000;
  152. }
  153. } else {
  154. return -EINVAL;
  155. }
  156. return 0;
  157. }
  158. int imx_tmu_get_temp(struct udevice *dev, int *temp)
  159. {
  160. struct imx_tmu_plat *pdata = dev_get_plat(dev);
  161. int cpu_tmp = 0;
  162. int ret;
  163. ret = read_temperature(dev, &cpu_tmp);
  164. if (ret)
  165. return ret;
  166. while (cpu_tmp >= pdata->alert) {
  167. printf("CPU Temperature (%dC) has beyond alert (%dC), close to critical (%dC)", cpu_tmp, pdata->alert, pdata->critical);
  168. puts(" waiting...\n");
  169. mdelay(pdata->polling_delay);
  170. ret = read_temperature(dev, &cpu_tmp);
  171. if (ret)
  172. return ret;
  173. }
  174. *temp = cpu_tmp / 1000;
  175. return 0;
  176. }
  177. static const struct dm_thermal_ops imx_tmu_ops = {
  178. .get_temp = imx_tmu_get_temp,
  179. };
  180. static int imx_tmu_calibration(struct udevice *dev)
  181. {
  182. int i, val, len, ret;
  183. u32 range[4];
  184. const fdt32_t *calibration;
  185. struct imx_tmu_plat *pdata = dev_get_plat(dev);
  186. ulong drv_data = dev_get_driver_data(dev);
  187. debug("%s\n", __func__);
  188. if (drv_data & (FLAGS_VER2 | FLAGS_VER3))
  189. return 0;
  190. ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
  191. if (ret) {
  192. printf("TMU: missing calibration range, ret = %d.\n", ret);
  193. return ret;
  194. }
  195. /* Init temperature range registers */
  196. writel(range[0], &pdata->regs->regs_v1.ttr0cr);
  197. writel(range[1], &pdata->regs->regs_v1.ttr1cr);
  198. writel(range[2], &pdata->regs->regs_v1.ttr2cr);
  199. writel(range[3], &pdata->regs->regs_v1.ttr3cr);
  200. calibration = dev_read_prop(dev, "fsl,tmu-calibration", &len);
  201. if (!calibration || len % 8) {
  202. printf("TMU: invalid calibration data.\n");
  203. return -ENODEV;
  204. }
  205. for (i = 0; i < len; i += 8, calibration += 2) {
  206. val = fdt32_to_cpu(*calibration);
  207. writel(val, &pdata->regs->regs_v1.ttcfgr);
  208. val = fdt32_to_cpu(*(calibration + 1));
  209. writel(val, &pdata->regs->regs_v1.tscfgr);
  210. }
  211. return 0;
  212. }
  213. void __weak imx_tmu_arch_init(void *reg_base)
  214. {
  215. }
  216. static void imx_tmu_init(struct udevice *dev)
  217. {
  218. struct imx_tmu_plat *pdata = dev_get_plat(dev);
  219. ulong drv_data = dev_get_driver_data(dev);
  220. debug("%s\n", __func__);
  221. if (drv_data & FLAGS_VER3) {
  222. /* Disable monitoring */
  223. writel(0x0, &pdata->regs->regs_v3.ter);
  224. /* Disable interrupt, using polling instead */
  225. writel(0x0, &pdata->regs->regs_v3.tier);
  226. } else if (drv_data & FLAGS_VER2) {
  227. /* Disable monitoring */
  228. writel(0x0, &pdata->regs->regs_v2.ter);
  229. /* Disable interrupt, using polling instead */
  230. writel(0x0, &pdata->regs->regs_v2.tier);
  231. } else {
  232. /* Disable monitoring */
  233. writel(TMR_DISABLE, &pdata->regs->regs_v1.tmr);
  234. /* Disable interrupt, using polling instead */
  235. writel(TIER_DISABLE, &pdata->regs->regs_v1.tier);
  236. /* Set update_interval */
  237. writel(TMTMIR_DEFAULT, &pdata->regs->regs_v1.tmtmir);
  238. }
  239. imx_tmu_arch_init((void *)pdata->regs);
  240. }
  241. static int imx_tmu_enable_msite(struct udevice *dev)
  242. {
  243. struct imx_tmu_plat *pdata = dev_get_plat(dev);
  244. ulong drv_data = dev_get_driver_data(dev);
  245. u32 reg;
  246. debug("%s\n", __func__);
  247. if (!pdata->regs)
  248. return -EIO;
  249. if (drv_data & FLAGS_VER3) {
  250. reg = readl(&pdata->regs->regs_v3.ter);
  251. reg &= ~TER_EN;
  252. writel(reg, &pdata->regs->regs_v3.ter);
  253. writel(pdata->id << 30, &pdata->regs->regs_v3.tps);
  254. reg &= ~TER_ALPF;
  255. reg |= 0x1;
  256. reg &= ~TER_ADC_PD;
  257. writel(reg, &pdata->regs->regs_v3.ter);
  258. /* Enable monitor */
  259. reg |= TER_EN;
  260. writel(reg, &pdata->regs->regs_v3.ter);
  261. } else if (drv_data & FLAGS_VER2) {
  262. reg = readl(&pdata->regs->regs_v2.ter);
  263. reg &= ~TER_EN;
  264. writel(reg, &pdata->regs->regs_v2.ter);
  265. reg &= ~TER_ALPF;
  266. reg |= 0x1;
  267. writel(reg, &pdata->regs->regs_v2.ter);
  268. /* Enable monitor */
  269. reg |= TER_EN;
  270. writel(reg, &pdata->regs->regs_v2.ter);
  271. } else {
  272. /* Clear the ME before setting MSITE and ALPF*/
  273. reg = readl(&pdata->regs->regs_v1.tmr);
  274. reg &= ~TMR_ME;
  275. writel(reg, &pdata->regs->regs_v1.tmr);
  276. reg |= 1 << (15 - pdata->id);
  277. reg |= TMR_ALPF;
  278. writel(reg, &pdata->regs->regs_v1.tmr);
  279. /* Enable ME */
  280. reg |= TMR_ME;
  281. writel(reg, &pdata->regs->regs_v1.tmr);
  282. }
  283. return 0;
  284. }
  285. static int imx_tmu_bind(struct udevice *dev)
  286. {
  287. struct imx_tmu_plat *pdata = dev_get_plat(dev);
  288. int ret;
  289. ofnode node, offset;
  290. const char *name;
  291. const void *prop;
  292. int minc, maxc;
  293. debug("%s dev name %s\n", __func__, dev->name);
  294. prop = dev_read_prop(dev, "compatible", NULL);
  295. if (!prop)
  296. return 0;
  297. pdata->zone_node = 1;
  298. /* default alert/crit temps based on temp grade */
  299. get_cpu_temp_grade(&minc, &maxc);
  300. pdata->critical = maxc * 1000;
  301. pdata->alert = (maxc - 10) * 1000;
  302. node = ofnode_path("/thermal-zones");
  303. ofnode_for_each_subnode(offset, node) {
  304. /* Bind the subnode to this driver */
  305. name = ofnode_get_name(offset);
  306. ret = device_bind_with_driver_data(dev, dev->driver, name,
  307. dev->driver_data, offset,
  308. NULL);
  309. if (ret)
  310. printf("Error binding driver '%s': %d\n",
  311. dev->driver->name, ret);
  312. }
  313. return 0;
  314. }
  315. static int imx_tmu_parse_fdt(struct udevice *dev)
  316. {
  317. struct imx_tmu_plat *pdata = dev_get_plat(dev), *p_parent_data;
  318. struct ofnode_phandle_args args;
  319. ofnode trips_np;
  320. int ret;
  321. debug("%s dev name %s\n", __func__, dev->name);
  322. if (pdata->zone_node) {
  323. pdata->regs = (union tmu_regs *)dev_read_addr_ptr(dev);
  324. if (!pdata->regs)
  325. return -EINVAL;
  326. return 0;
  327. }
  328. p_parent_data = dev_get_plat(dev->parent);
  329. if (p_parent_data->zone_node)
  330. pdata->regs = p_parent_data->regs;
  331. ret = dev_read_phandle_with_args(dev, "thermal-sensors",
  332. "#thermal-sensor-cells",
  333. 0, 0, &args);
  334. if (ret)
  335. return ret;
  336. if (!ofnode_equal(args.node, dev_ofnode(dev->parent)))
  337. return -EFAULT;
  338. if (args.args_count >= 1)
  339. pdata->id = args.args[0];
  340. else
  341. pdata->id = 0;
  342. debug("args.args_count %d, id %d\n", args.args_count, pdata->id);
  343. pdata->polling_delay = dev_read_u32_default(dev, "polling-delay", 1000);
  344. trips_np = ofnode_path("/thermal-zones/cpu-thermal/trips");
  345. ofnode_for_each_subnode(trips_np, trips_np) {
  346. const char *type;
  347. type = ofnode_get_property(trips_np, "type", NULL);
  348. if (!type)
  349. continue;
  350. if (!strcmp(type, "critical"))
  351. pdata->critical = ofnode_read_u32_default(trips_np, "temperature", 85);
  352. else if (strcmp(type, "passive") == 0)
  353. pdata->alert = ofnode_read_u32_default(trips_np, "temperature", 80);
  354. else
  355. continue;
  356. }
  357. debug("id %d polling_delay %d, critical %d, alert %d\n",
  358. pdata->id, pdata->polling_delay, pdata->critical, pdata->alert);
  359. return 0;
  360. }
  361. static int imx_tmu_probe(struct udevice *dev)
  362. {
  363. struct imx_tmu_plat *pdata = dev_get_plat(dev);
  364. int ret;
  365. ret = imx_tmu_parse_fdt(dev);
  366. if (ret) {
  367. printf("Error in parsing TMU FDT %d\n", ret);
  368. return ret;
  369. }
  370. if (pdata->zone_node) {
  371. imx_tmu_init(dev);
  372. imx_tmu_calibration(dev);
  373. imx_tmu_enable_msite(dev);
  374. } else {
  375. imx_tmu_enable_msite(dev);
  376. }
  377. return 0;
  378. }
  379. static const struct udevice_id imx_tmu_ids[] = {
  380. { .compatible = "fsl,imx8mq-tmu", },
  381. { .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, },
  382. { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, },
  383. { }
  384. };
  385. U_BOOT_DRIVER(imx_tmu) = {
  386. .name = "imx_tmu",
  387. .id = UCLASS_THERMAL,
  388. .ops = &imx_tmu_ops,
  389. .of_match = imx_tmu_ids,
  390. .bind = imx_tmu_bind,
  391. .probe = imx_tmu_probe,
  392. .plat_auto = sizeof(struct imx_tmu_plat),
  393. .flags = DM_FLAG_PRE_RELOC,
  394. };