lpddr4.h 2.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273
  1. /* SPDX-License-Identifier: BSD-3-Clause */
  2. /*
  3. * Cadence DDR Driver
  4. *
  5. * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
  6. * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
  7. */
  8. #ifndef LPDDR4_H
  9. #define LPDDR4_H
  10. #include "lpddr4_ctl_regs.h"
  11. #include "lpddr4_sanity.h"
  12. #ifdef CONFIG_K3_AM64_DDRSS
  13. #include "lpddr4_16bit.h"
  14. #include "lpddr4_16bit_sanity.h"
  15. #else
  16. #include "lpddr4_32bit.h"
  17. #include "lpddr4_32bit_sanity.h"
  18. #endif
  19. #ifdef REG_WRITE_VERIF
  20. #include "lpddr4_ctl_regs_rw_masks.h"
  21. #endif
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. #define PRODUCT_ID (0x1046U)
  26. #define LPDDR4_BIT_MASK (0x1U)
  27. #define BYTE_MASK (0xffU)
  28. #define NIBBLE_MASK (0xfU)
  29. #define WORD_SHIFT (32U)
  30. #define WORD_MASK (0xffffffffU)
  31. #define SLICE_WIDTH (0x100)
  32. #define CTL_OFFSET 0
  33. #define PI_OFFSET (((u32)1) << 11)
  34. #define PHY_OFFSET (((u32)1) << 12)
  35. #define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT)
  36. #define PLL_READY (0x3U)
  37. #define IO_CALIB_DONE ((u32)0x1U << 23U)
  38. #define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U)
  39. #define IO_CALIB_STATE ((u32)0xBU << 28U)
  40. #define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U)
  41. #define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U))
  42. #define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U)
  43. #define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U))
  44. #define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U))
  45. #define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U))
  46. #define CDN_TRUE 1U
  47. #define CDN_FALSE 0U
  48. void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
  49. volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
  50. u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
  51. bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound);
  52. void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr);
  53. u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
  54. void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
  55. u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
  56. u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
  57. #ifdef __cplusplus
  58. }
  59. #endif
  60. #endif /* LPDDR4_H */