meson-axg-mipi-dphy.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson AXG MIPI DPHY driver
  4. *
  5. * Copyright (C) 2018 Amlogic, Inc. All rights reserved
  6. * Copyright (C) 2020 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstrong@baylibre.com>
  8. */
  9. #include <common.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <asm/io.h>
  13. #include <bitfield.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <generic-phy.h>
  17. #include <regmap.h>
  18. #include <linux/delay.h>
  19. #include <power/regulator.h>
  20. #include <reset.h>
  21. #include <clk.h>
  22. #include <phy-mipi-dphy.h>
  23. #include <linux/bitops.h>
  24. #include <linux/compat.h>
  25. #include <linux/bitfield.h>
  26. /* [31] soft reset for the phy.
  27. * 1: reset. 0: dessert the reset.
  28. * [30] clock lane soft reset.
  29. * [29] data byte lane 3 soft reset.
  30. * [28] data byte lane 2 soft reset.
  31. * [27] data byte lane 1 soft reset.
  32. * [26] data byte lane 0 soft reset.
  33. * [25] mipi dsi pll clock selection.
  34. * 1: clock from fixed 850Mhz clock source. 0: from VID2 PLL.
  35. * [12] mipi HSbyteclk enable.
  36. * [11] mipi divider clk selection.
  37. * 1: select the mipi DDRCLKHS from clock divider.
  38. * 0: from PLL clock.
  39. * [10] mipi clock divider control.
  40. * 1: /4. 0: /2.
  41. * [9] mipi divider output enable.
  42. * [8] mipi divider counter enable.
  43. * [7] PLL clock enable.
  44. * [5] LPDT data endian.
  45. * 1 = transfer the high bit first. 0 : transfer the low bit first.
  46. * [4] HS data endian.
  47. * [3] force data byte lane in stop mode.
  48. * [2] force data byte lane 0 in receiver mode.
  49. * [1] write 1 to sync the txclkesc input. the internal logic have to
  50. * use txclkesc to decide Txvalid and Txready.
  51. * [0] enalbe the MIPI DPHY TxDDRClk.
  52. */
  53. #define MIPI_DSI_PHY_CTRL 0x0
  54. /* [31] clk lane tx_hs_en control selection.
  55. * 1: from register. 0: use clk lane state machine.
  56. * [30] register bit for clock lane tx_hs_en.
  57. * [29] clk lane tx_lp_en contrl selection.
  58. * 1: from register. 0: from clk lane state machine.
  59. * [28] register bit for clock lane tx_lp_en.
  60. * [27] chan0 tx_hs_en control selection.
  61. * 1: from register. 0: from chan0 state machine.
  62. * [26] register bit for chan0 tx_hs_en.
  63. * [25] chan0 tx_lp_en control selection.
  64. * 1: from register. 0: from chan0 state machine.
  65. * [24] register bit from chan0 tx_lp_en.
  66. * [23] chan0 rx_lp_en control selection.
  67. * 1: from register. 0: from chan0 state machine.
  68. * [22] register bit from chan0 rx_lp_en.
  69. * [21] chan0 contention detection enable control selection.
  70. * 1: from register. 0: from chan0 state machine.
  71. * [20] register bit from chan0 contention dectection enable.
  72. * [19] chan1 tx_hs_en control selection.
  73. * 1: from register. 0: from chan0 state machine.
  74. * [18] register bit for chan1 tx_hs_en.
  75. * [17] chan1 tx_lp_en control selection.
  76. * 1: from register. 0: from chan0 state machine.
  77. * [16] register bit from chan1 tx_lp_en.
  78. * [15] chan2 tx_hs_en control selection.
  79. * 1: from register. 0: from chan0 state machine.
  80. * [14] register bit for chan2 tx_hs_en.
  81. * [13] chan2 tx_lp_en control selection.
  82. * 1: from register. 0: from chan0 state machine.
  83. * [12] register bit from chan2 tx_lp_en.
  84. * [11] chan3 tx_hs_en control selection.
  85. * 1: from register. 0: from chan0 state machine.
  86. * [10] register bit for chan3 tx_hs_en.
  87. * [9] chan3 tx_lp_en control selection.
  88. * 1: from register. 0: from chan0 state machine.
  89. * [8] register bit from chan3 tx_lp_en.
  90. * [4] clk chan power down. this bit is also used as the power down
  91. * of the whole MIPI_DSI_PHY.
  92. * [3] chan3 power down.
  93. * [2] chan2 power down.
  94. * [1] chan1 power down.
  95. * [0] chan0 power down.
  96. */
  97. #define MIPI_DSI_CHAN_CTRL 0x4
  98. /* [24] rx turn watch dog triggered.
  99. * [23] rx esc watchdog triggered.
  100. * [22] mbias ready.
  101. * [21] txclkesc synced and ready.
  102. * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
  103. * [16:13] chan3 state{0, tx_stop, tx_ulps, tx_hs_active}
  104. * [12:9] chan2 state.{0, tx_stop, tx_ulps, tx_hs_active}
  105. * [8:5] chan1 state. {0, tx_stop, tx_ulps, tx_hs_active}
  106. * [4:0] chan0 state. {TX_STOP, tx_ULPS, hs_active, direction, rxulpsesc}
  107. */
  108. #define MIPI_DSI_CHAN_STS 0x8
  109. /* [31:24] TCLK_PREPARE.
  110. * [23:16] TCLK_ZERO.
  111. * [15:8] TCLK_POST.
  112. * [7:0] TCLK_TRAIL.
  113. */
  114. #define MIPI_DSI_CLK_TIM 0xc
  115. /* [31:24] THS_PREPARE.
  116. * [23:16] THS_ZERO.
  117. * [15:8] THS_TRAIL.
  118. * [7:0] THS_EXIT.
  119. */
  120. #define MIPI_DSI_HS_TIM 0x10
  121. /* [31:24] tTA_GET.
  122. * [23:16] tTA_GO.
  123. * [15:8] tTA_SURE.
  124. * [7:0] tLPX.
  125. */
  126. #define MIPI_DSI_LP_TIM 0x14
  127. /* wait time to MIPI DIS analog ready. */
  128. #define MIPI_DSI_ANA_UP_TIM 0x18
  129. /* TINIT. */
  130. #define MIPI_DSI_INIT_TIM 0x1c
  131. /* TWAKEUP. */
  132. #define MIPI_DSI_WAKEUP_TIM 0x20
  133. /* when in RxULPS check state, after the the logic enable the analog,
  134. * how long we should wait to check the lP state .
  135. */
  136. #define MIPI_DSI_LPOK_TIM 0x24
  137. /* Watchdog for RX low power state no finished. */
  138. #define MIPI_DSI_LP_WCHDOG 0x28
  139. /* tMBIAS, after send power up signals to analog,
  140. * how long we should wait for analog powered up.
  141. */
  142. #define MIPI_DSI_ANA_CTRL 0x2c
  143. /* [31:8] reserved for future.
  144. * [7:0] tCLK_PRE.
  145. */
  146. #define MIPI_DSI_CLK_TIM1 0x30
  147. /* watchdog for turn around waiting time. */
  148. #define MIPI_DSI_TURN_WCHDOG 0x34
  149. /* When in RxULPS state, how frequency we should to check
  150. * if the TX side out of ULPS state.
  151. */
  152. #define MIPI_DSI_ULPS_CHECK 0x38
  153. #define MIPI_DSI_TEST_CTRL0 0x3c
  154. #define MIPI_DSI_TEST_CTRL1 0x40
  155. #define NSEC_PER_MSEC 1000000L
  156. struct phy_meson_axg_mipi_dphy_priv {
  157. struct regmap *regmap;
  158. #if CONFIG_IS_ENABLED(CLK)
  159. struct clk clk;
  160. #endif
  161. struct reset_ctl reset;
  162. struct phy analog;
  163. struct phy_configure_opts_mipi_dphy config;
  164. };
  165. static int phy_meson_axg_mipi_dphy_configure(struct phy *phy, void *params)
  166. {
  167. struct udevice *dev = phy->dev;
  168. struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
  169. struct phy_configure_opts_mipi_dphy *config = params;
  170. int ret;
  171. ret = phy_mipi_dphy_config_validate(config);
  172. if (ret)
  173. return ret;
  174. ret = generic_phy_configure(&priv->analog, config);
  175. if (ret)
  176. return ret;
  177. memcpy(&priv->config, config, sizeof(priv->config));
  178. return 0;
  179. }
  180. static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy)
  181. {
  182. struct udevice *dev = phy->dev;
  183. struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
  184. unsigned long temp;
  185. int ret;
  186. ret = generic_phy_power_on(&priv->analog);
  187. if (ret)
  188. return ret;
  189. /* enable phy clock */
  190. regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, 0x1);
  191. regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,
  192. BIT(0) | /* enable the DSI PLL clock . */
  193. BIT(7) | /* enable pll clock which connected to DDR clock path */
  194. BIT(8)); /* enable the clock divider counter */
  195. /* enable the divider clock out */
  196. regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9));
  197. /* enable the byte clock generation. */
  198. regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12));
  199. regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31));
  200. regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0);
  201. /* Calculate lanebyteclk period in ps */
  202. temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000);
  203. temp = temp * 8 * 10;
  204. regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,
  205. DIV_ROUND_UP(priv->config.clk_trail, temp) |
  206. (DIV_ROUND_UP(priv->config.clk_post +
  207. priv->config.hs_trail, temp) << 8) |
  208. (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
  209. (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
  210. regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
  211. DIV_ROUND_UP(priv->config.clk_pre, temp));
  212. regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
  213. DIV_ROUND_UP(priv->config.hs_exit, temp) |
  214. (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) |
  215. (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) |
  216. (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24));
  217. regmap_write(priv->regmap, MIPI_DSI_LP_TIM,
  218. DIV_ROUND_UP(priv->config.lpx, temp) |
  219. (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) |
  220. (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) |
  221. (DIV_ROUND_UP(priv->config.ta_get, temp) << 24));
  222. regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);
  223. regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,
  224. DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp));
  225. regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,
  226. DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp));
  227. regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C);
  228. regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C);
  229. regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000);
  230. regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000);
  231. /* Powerup the analog circuit */
  232. switch (priv->config.lanes) {
  233. case 1:
  234. regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe);
  235. break;
  236. case 2:
  237. regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc);
  238. break;
  239. case 3:
  240. regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8);
  241. break;
  242. case 4:
  243. default:
  244. regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0);
  245. break;
  246. }
  247. /* Trigger a sync active for esc_clk */
  248. regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1));
  249. return 0;
  250. }
  251. static int phy_meson_axg_mipi_dphy_power_off(struct phy *phy)
  252. {
  253. struct udevice *dev = phy->dev;
  254. struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
  255. regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf);
  256. regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31));
  257. return generic_phy_power_off(&priv->analog);
  258. }
  259. static int phy_meson_axg_mipi_dphy_init(struct phy *phy)
  260. {
  261. struct udevice *dev = phy->dev;
  262. struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
  263. int ret;
  264. ret = generic_phy_init(&priv->analog);
  265. if (ret)
  266. return ret;
  267. ret = reset_assert(&priv->reset);
  268. udelay(1);
  269. ret |= reset_deassert(&priv->reset);
  270. if (ret)
  271. return ret;
  272. return 0;
  273. }
  274. static int phy_meson_axg_mipi_dphy_exit(struct phy *phy)
  275. {
  276. struct udevice *dev = phy->dev;
  277. struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
  278. int ret;
  279. ret = generic_phy_exit(&priv->analog);
  280. if (ret)
  281. return ret;
  282. return reset_assert(&priv->reset);
  283. }
  284. struct phy_ops meson_axg_mipi_dphy_ops = {
  285. .init = phy_meson_axg_mipi_dphy_init,
  286. .exit = phy_meson_axg_mipi_dphy_exit,
  287. .power_on = phy_meson_axg_mipi_dphy_power_on,
  288. .power_off = phy_meson_axg_mipi_dphy_power_off,
  289. .configure = phy_meson_axg_mipi_dphy_configure,
  290. };
  291. int meson_axg_mipi_dphy_probe(struct udevice *dev)
  292. {
  293. struct phy_meson_axg_mipi_dphy_priv *priv = dev_get_priv(dev);
  294. int ret;
  295. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  296. if (ret)
  297. return ret;
  298. ret = generic_phy_get_by_index(dev, 0, &priv->analog);
  299. if (ret)
  300. return ret;
  301. ret = reset_get_by_index(dev, 0, &priv->reset);
  302. if (ret == -ENOTSUPP)
  303. return 0;
  304. else if (ret)
  305. return ret;
  306. ret = reset_deassert(&priv->reset);
  307. if (ret) {
  308. reset_release_all(&priv->reset, 1);
  309. return ret;
  310. }
  311. #if CONFIG_IS_ENABLED(CLK)
  312. ret = clk_get_by_index(dev, 0, &priv->clk);
  313. if (ret < 0)
  314. return ret;
  315. ret = clk_enable(&priv->clk);
  316. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  317. pr_err("failed to enable PHY clock\n");
  318. clk_free(&priv->clk);
  319. return ret;
  320. }
  321. #endif
  322. return 0;
  323. }
  324. static const struct udevice_id meson_axg_mipi_dphy_ids[] = {
  325. { .compatible = "amlogic,axg-mipi-dphy" },
  326. { }
  327. };
  328. U_BOOT_DRIVER(meson_axg_mipi_dphy) = {
  329. .name = "meson_axg_mipi_dphy",
  330. .id = UCLASS_PHY,
  331. .of_match = meson_axg_mipi_dphy_ids,
  332. .probe = meson_axg_mipi_dphy_probe,
  333. .ops = &meson_axg_mipi_dphy_ops,
  334. .priv_auto = sizeof(struct phy_meson_axg_mipi_dphy_priv),
  335. };