xilinx_axi_mrmac.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xilinx Multirate Ethernet MAC(MRMAC) driver
  4. *
  5. * Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
  6. * Michal Simek <michal.simek@xilinx.com>
  7. *
  8. * Copyright (C) 2021 Xilinx, Inc. All rights reserved.
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <log.h>
  15. #include <net.h>
  16. #include <malloc.h>
  17. #include <wait_bit.h>
  18. #include <asm/io.h>
  19. #include <linux/delay.h>
  20. #include <linux/ethtool.h>
  21. #include "xilinx_axi_mrmac.h"
  22. static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc)
  23. {
  24. if (IS_ENABLED(CONFIG_PHYS_64BIT))
  25. writeq((unsigned long)bd, desc);
  26. else
  27. writel((uintptr_t)bd, desc);
  28. }
  29. /**
  30. * axi_mrmac_ethernet_init - MRMAC init function
  31. * @priv: MRMAC private structure
  32. *
  33. * Return: 0 on success, negative value on errors
  34. *
  35. * This function is called to reset and initialize MRMAC core. This is
  36. * typically called during initialization. It does a reset of MRMAC Rx/Tx
  37. * channels and Rx/Tx SERDES. It configures MRMAC speed based on mrmac_rate
  38. * which is read from DT. This function waits for block lock bit to get set,
  39. * if it is not set within 100ms time returns a timeout error.
  40. */
  41. static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv)
  42. {
  43. struct mrmac_regs *regs = priv->iobase;
  44. u32 reg;
  45. u32 ret;
  46. /* Perform all the RESET's required */
  47. setbits_le32(&regs->reset, MRMAC_RX_SERDES_RST_MASK | MRMAC_RX_RST_MASK
  48. | MRMAC_TX_SERDES_RST_MASK | MRMAC_TX_RST_MASK);
  49. mdelay(MRMAC_RESET_DELAY);
  50. /* Configure Mode register */
  51. reg = readl(&regs->mode);
  52. log_debug("Configuring MRMAC speed to %d\n", priv->mrmac_rate);
  53. if (priv->mrmac_rate == SPEED_25000) {
  54. reg &= ~MRMAC_CTL_RATE_CFG_MASK;
  55. reg |= MRMAC_CTL_DATA_RATE_25G;
  56. reg |= (MRMAC_CTL_AXIS_CFG_25G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
  57. reg |= (MRMAC_CTL_SERDES_WIDTH_25G <<
  58. MRMAC_CTL_SERDES_WIDTH_SHIFT);
  59. } else {
  60. reg &= ~MRMAC_CTL_RATE_CFG_MASK;
  61. reg |= MRMAC_CTL_DATA_RATE_10G;
  62. reg |= (MRMAC_CTL_AXIS_CFG_10G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
  63. reg |= (MRMAC_CTL_SERDES_WIDTH_10G <<
  64. MRMAC_CTL_SERDES_WIDTH_SHIFT);
  65. }
  66. /* For tick reg */
  67. reg |= MRMAC_CTL_PM_TICK_MASK;
  68. writel(reg, &regs->mode);
  69. clrbits_le32(&regs->reset, MRMAC_RX_SERDES_RST_MASK | MRMAC_RX_RST_MASK
  70. | MRMAC_TX_SERDES_RST_MASK | MRMAC_TX_RST_MASK);
  71. mdelay(MRMAC_RESET_DELAY);
  72. /* Setup MRMAC hardware options */
  73. setbits_le32(&regs->rx_config, MRMAC_RX_DEL_FCS_MASK);
  74. setbits_le32(&regs->tx_config, MRMAC_TX_INS_FCS_MASK);
  75. setbits_le32(&regs->tx_config, MRMAC_TX_EN_MASK);
  76. setbits_le32(&regs->rx_config, MRMAC_RX_EN_MASK);
  77. /* Check for block lock bit to be set. This ensures that
  78. * MRMAC ethernet IP is functioning normally.
  79. */
  80. writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
  81. MRMAC_TX_STS_OFFSET);
  82. writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
  83. MRMAC_RX_STS_OFFSET);
  84. writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
  85. MRMAC_STATRX_BLKLCK_OFFSET);
  86. ret = wait_for_bit_le32((u32 *)((phys_addr_t)priv->iobase +
  87. MRMAC_STATRX_BLKLCK_OFFSET),
  88. MRMAC_RX_BLKLCK_MASK, true,
  89. MRMAC_BLKLCK_TIMEOUT, true);
  90. if (ret) {
  91. log_warning("Error: MRMAC block lock not complete!\n");
  92. return -EIO;
  93. }
  94. writel(MRMAC_TICK_TRIGGER, &regs->tick_reg);
  95. return 0;
  96. }
  97. /**
  98. * axi_mcdma_init - Reset MCDMA engine
  99. * @priv: MRMAC private structure
  100. *
  101. * Return: 0 on success, negative value on timeouts
  102. *
  103. * This function is called to reset and initialize MCDMA engine
  104. */
  105. static int axi_mcdma_init(struct axi_mrmac_priv *priv)
  106. {
  107. u32 ret;
  108. /* Reset the engine so the hardware starts from a known state */
  109. writel(XMCDMA_CR_RESET, &priv->mm2s_cmn->control);
  110. writel(XMCDMA_CR_RESET, &priv->s2mm_cmn->control);
  111. /* Check Tx/Rx MCDMA.RST. Reset is done when the reset bit is low */
  112. ret = wait_for_bit_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RESET,
  113. false, MRMAC_DMARST_TIMEOUT, true);
  114. if (ret) {
  115. log_warning("Tx MCDMA reset Timeout\n");
  116. return -ETIMEDOUT;
  117. }
  118. ret = wait_for_bit_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RESET,
  119. false, MRMAC_DMARST_TIMEOUT, true);
  120. if (ret) {
  121. log_warning("Rx MCDMA reset Timeout\n");
  122. return -ETIMEDOUT;
  123. }
  124. /* Enable channel 1 for Tx and Rx */
  125. writel(XMCDMA_CHANNEL_1, &priv->mm2s_cmn->chen);
  126. writel(XMCDMA_CHANNEL_1, &priv->s2mm_cmn->chen);
  127. return 0;
  128. }
  129. /**
  130. * axi_mrmac_start - MRMAC start
  131. * @dev: udevice structure
  132. *
  133. * Return: 0 on success, negative value on errors
  134. *
  135. * This is a initialization function of MRMAC. Call MCDMA initialization
  136. * function and setup Rx buffer descriptors for starting reception of packets.
  137. * Enable Tx and Rx channels and trigger Rx channel fetch.
  138. */
  139. static int axi_mrmac_start(struct udevice *dev)
  140. {
  141. struct axi_mrmac_priv *priv = dev_get_priv(dev);
  142. struct mrmac_regs *regs = priv->iobase;
  143. /*
  144. * Initialize MCDMA engine. MCDMA engine must be initialized before
  145. * MRMAC. During MCDMA engine initialization, MCDMA hardware is reset,
  146. * since MCDMA reset line is connected to MRMAC, this would ensure a
  147. * reset of MRMAC.
  148. */
  149. axi_mcdma_init(priv);
  150. /* Initialize MRMAC hardware */
  151. if (axi_mrmac_ethernet_init(priv))
  152. return -EIO;
  153. /* Disable all Rx interrupts before RxBD space setup */
  154. clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
  155. /* Update current descriptor */
  156. axi_mrmac_dma_write(priv->rx_bd[0], &priv->mcdma_rx->current);
  157. /* Setup Rx BD. MRMAC needs atleast two descriptors */
  158. memset(priv->rx_bd[0], 0, RX_BD_TOTAL_SIZE);
  159. priv->rx_bd[0]->next_desc = lower_32_bits((u64)priv->rx_bd[1]);
  160. priv->rx_bd[0]->buf_addr = lower_32_bits((u64)net_rx_packets[0]);
  161. priv->rx_bd[1]->next_desc = lower_32_bits((u64)priv->rx_bd[0]);
  162. priv->rx_bd[1]->buf_addr = lower_32_bits((u64)net_rx_packets[1]);
  163. if (IS_ENABLED(CONFIG_PHYS_64BIT)) {
  164. priv->rx_bd[0]->next_desc_msb = upper_32_bits((u64)priv->rx_bd[1]);
  165. priv->rx_bd[0]->buf_addr_msb = upper_32_bits((u64)net_rx_packets[0]);
  166. priv->rx_bd[1]->next_desc_msb = upper_32_bits((u64)priv->rx_bd[0]);
  167. priv->rx_bd[1]->buf_addr_msb = upper_32_bits((u64)net_rx_packets[1]);
  168. }
  169. priv->rx_bd[0]->cntrl = PKTSIZE_ALIGN;
  170. priv->rx_bd[1]->cntrl = PKTSIZE_ALIGN;
  171. /* Flush the last BD so DMA core could see the updates */
  172. flush_cache((phys_addr_t)priv->rx_bd[0], RX_BD_TOTAL_SIZE);
  173. /* It is necessary to flush rx buffers because if you don't do it
  174. * then cache can contain uninitialized data
  175. */
  176. flush_cache((phys_addr_t)priv->rx_bd[0]->buf_addr, RX_BUFF_TOTAL_SIZE);
  177. /* Start the hardware */
  178. setbits_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RUNSTOP_MASK);
  179. setbits_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RUNSTOP_MASK);
  180. setbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
  181. /* Channel fetch */
  182. setbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
  183. /* Update tail descriptor. Now it's ready to receive data */
  184. axi_mrmac_dma_write(priv->rx_bd[1], &priv->mcdma_rx->tail);
  185. /* Enable Tx */
  186. setbits_le32(&regs->tx_config, MRMAC_TX_EN_MASK);
  187. /* Enable Rx */
  188. setbits_le32(&regs->rx_config, MRMAC_RX_EN_MASK);
  189. return 0;
  190. }
  191. /**
  192. * axi_mrmac_send - MRMAC Tx function
  193. * @dev: udevice structure
  194. * @ptr: pointer to Tx buffer
  195. * @len: transfer length
  196. *
  197. * Return: 0 on success, negative value on errors
  198. *
  199. * This is a Tx send function of MRMAC. Setup Tx buffer descriptors and trigger
  200. * transfer. Wait till the data is transferred.
  201. */
  202. static int axi_mrmac_send(struct udevice *dev, void *ptr, int len)
  203. {
  204. struct axi_mrmac_priv *priv = dev_get_priv(dev);
  205. u32 ret;
  206. #ifdef DEBUG
  207. print_buffer(ptr, ptr, 1, len, 16);
  208. #endif
  209. if (len > PKTSIZE_ALIGN)
  210. len = PKTSIZE_ALIGN;
  211. /* If size is less than min packet size, pad to min size */
  212. if (len < MIN_PKT_SIZE) {
  213. memset(priv->txminframe, 0, MIN_PKT_SIZE);
  214. memcpy(priv->txminframe, ptr, len);
  215. len = MIN_PKT_SIZE;
  216. ptr = priv->txminframe;
  217. }
  218. writel(XMCDMA_IRQ_ALL_MASK, &priv->mcdma_tx->status);
  219. clrbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK);
  220. /* Flush packet to main memory to be trasfered by DMA */
  221. flush_cache((phys_addr_t)ptr, len);
  222. /* Setup Tx BD. MRMAC needs atleast two descriptors */
  223. memset(priv->tx_bd[0], 0, TX_BD_TOTAL_SIZE);
  224. priv->tx_bd[0]->next_desc = lower_32_bits((u64)priv->tx_bd[1]);
  225. priv->tx_bd[0]->buf_addr = lower_32_bits((u64)ptr);
  226. /* At the end of the ring, link the last BD back to the top */
  227. priv->tx_bd[1]->next_desc = lower_32_bits((u64)priv->tx_bd[0]);
  228. priv->tx_bd[1]->buf_addr = lower_32_bits((u64)ptr + len / 2);
  229. if (IS_ENABLED(CONFIG_PHYS_64BIT)) {
  230. priv->tx_bd[0]->next_desc_msb = upper_32_bits((u64)priv->tx_bd[1]);
  231. priv->tx_bd[0]->buf_addr_msb = upper_32_bits((u64)ptr);
  232. priv->tx_bd[1]->next_desc_msb = upper_32_bits((u64)priv->tx_bd[0]);
  233. priv->tx_bd[1]->buf_addr_msb = upper_32_bits((u64)ptr + len / 2);
  234. }
  235. /* Split Tx data in to half and send in two descriptors */
  236. priv->tx_bd[0]->cntrl = (len / 2) | XMCDMA_BD_CTRL_TXSOF_MASK;
  237. priv->tx_bd[1]->cntrl = (len - len / 2) | XMCDMA_BD_CTRL_TXEOF_MASK;
  238. /* Flush the last BD so DMA core could see the updates */
  239. flush_cache((phys_addr_t)priv->tx_bd[0], TX_BD_TOTAL_SIZE);
  240. if (readl(&priv->mcdma_tx->status) & XMCDMA_CH_IDLE) {
  241. axi_mrmac_dma_write(priv->tx_bd[0], &priv->mcdma_tx->current);
  242. /* Channel fetch */
  243. setbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK);
  244. } else {
  245. log_warning("Error: current desc is not updated\n");
  246. return -EIO;
  247. }
  248. setbits_le32(&priv->mcdma_tx->control, XMCDMA_IRQ_ALL_MASK);
  249. /* Start transfer */
  250. axi_mrmac_dma_write(priv->tx_bd[1], &priv->mcdma_tx->tail);
  251. /* Wait for transmission to complete */
  252. ret = wait_for_bit_le32(&priv->mcdma_tx->status, XMCDMA_IRQ_IOC_MASK,
  253. true, 1, true);
  254. if (ret) {
  255. log_warning("%s: Timeout\n", __func__);
  256. return -ETIMEDOUT;
  257. }
  258. /* Clear status */
  259. priv->tx_bd[0]->sband_stats = 0;
  260. priv->tx_bd[1]->sband_stats = 0;
  261. log_debug("Sending complete\n");
  262. return 0;
  263. }
  264. static bool isrxready(struct axi_mrmac_priv *priv)
  265. {
  266. u32 status;
  267. /* Read pending interrupts */
  268. status = readl(&priv->mcdma_rx->status);
  269. /* Acknowledge pending interrupts */
  270. writel(status & XMCDMA_IRQ_ALL_MASK, &priv->mcdma_rx->status);
  271. /*
  272. * If Reception done interrupt is asserted, call Rx call back function
  273. * to handle the processed BDs and then raise the according flag.
  274. */
  275. if (status & (XMCDMA_IRQ_IOC_MASK | XMCDMA_IRQ_DELAY_MASK))
  276. return 1;
  277. return 0;
  278. }
  279. /**
  280. * axi_mrmac_recv - MRMAC Rx function
  281. * @dev: udevice structure
  282. * @flags: flags from network stack
  283. * @packetp pointer to received data
  284. *
  285. * Return: received data length on success, negative value on errors
  286. *
  287. * This is a Rx function of MRMAC. Check if any data is received on MCDMA.
  288. * Copy buffer pointer to packetp and return received data length.
  289. */
  290. static int axi_mrmac_recv(struct udevice *dev, int flags, uchar **packetp)
  291. {
  292. struct axi_mrmac_priv *priv = dev_get_priv(dev);
  293. u32 rx_bd_end;
  294. u32 length;
  295. /* Wait for an incoming packet */
  296. if (!isrxready(priv))
  297. return -EAGAIN;
  298. /* Clear all interrupts */
  299. writel(XMCDMA_IRQ_ALL_MASK, &priv->mcdma_rx->status);
  300. /* Disable IRQ for a moment till packet is handled */
  301. clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
  302. /* Disable channel fetch */
  303. clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
  304. rx_bd_end = (ulong)priv->rx_bd[0] + roundup(RX_BD_TOTAL_SIZE,
  305. ARCH_DMA_MINALIGN);
  306. /* Invalidate Rx descriptors to see proper Rx length */
  307. invalidate_dcache_range((phys_addr_t)priv->rx_bd[0], rx_bd_end);
  308. length = priv->rx_bd[0]->status & XMCDMA_BD_STS_ACTUAL_LEN_MASK;
  309. *packetp = (uchar *)(ulong)priv->rx_bd[0]->buf_addr;
  310. if (!length) {
  311. length = priv->rx_bd[1]->status & XMCDMA_BD_STS_ACTUAL_LEN_MASK;
  312. *packetp = (uchar *)(ulong)priv->rx_bd[1]->buf_addr;
  313. }
  314. #ifdef DEBUG
  315. print_buffer(*packetp, *packetp, 1, length, 16);
  316. #endif
  317. /* Clear status */
  318. priv->rx_bd[0]->status = 0;
  319. priv->rx_bd[1]->status = 0;
  320. return length;
  321. }
  322. /**
  323. * axi_mrmac_free_pkt - MRMAC free packet function
  324. * @dev: udevice structure
  325. * @packet: receive buffer pointer
  326. * @length received data length
  327. *
  328. * Return: 0 on success, negative value on errors
  329. *
  330. * This is Rx free packet function of MRMAC. Prepare MRMAC for reception of
  331. * data again. Invalidate previous data from Rx buffers and set Rx buffer
  332. * descriptors. Trigger reception by updating tail descriptor.
  333. */
  334. static int axi_mrmac_free_pkt(struct udevice *dev, uchar *packet, int length)
  335. {
  336. struct axi_mrmac_priv *priv = dev_get_priv(dev);
  337. #ifdef DEBUG
  338. /* It is useful to clear buffer to be sure that it is consistent */
  339. memset(priv->rx_bd[0]->buf_addr, 0, RX_BUFF_TOTAL_SIZE);
  340. #endif
  341. /* Disable all Rx interrupts before RxBD space setup */
  342. clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
  343. /* Disable channel fetch */
  344. clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
  345. /* Update current descriptor */
  346. axi_mrmac_dma_write(priv->rx_bd[0], &priv->mcdma_rx->current);
  347. /* Write bd to HW */
  348. flush_cache((phys_addr_t)priv->rx_bd[0], RX_BD_TOTAL_SIZE);
  349. /* It is necessary to flush rx buffers because if you don't do it
  350. * then cache will contain previous packet
  351. */
  352. flush_cache((phys_addr_t)priv->rx_bd[0]->buf_addr, RX_BUFF_TOTAL_SIZE);
  353. /* Enable all IRQ */
  354. setbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
  355. /* Channel fetch */
  356. setbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
  357. /* Update tail descriptor. Now it's ready to receive data */
  358. axi_mrmac_dma_write(priv->rx_bd[1], &priv->mcdma_rx->tail);
  359. log_debug("Rx completed, framelength = %x\n", length);
  360. return 0;
  361. }
  362. /**
  363. * axi_mrmac_stop - Stop MCDMA transfers
  364. * @dev: udevice structure
  365. *
  366. * Return: 0 on success, negative value on errors
  367. *
  368. * Stop MCDMA engine for both Tx and Rx transfers.
  369. */
  370. static void axi_mrmac_stop(struct udevice *dev)
  371. {
  372. struct axi_mrmac_priv *priv = dev_get_priv(dev);
  373. /* Stop the hardware */
  374. clrbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK);
  375. clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
  376. log_debug("Halted\n");
  377. }
  378. static int axi_mrmac_probe(struct udevice *dev)
  379. {
  380. struct axi_mrmac_plat *plat = dev_get_plat(dev);
  381. struct eth_pdata *pdata = &plat->eth_pdata;
  382. struct axi_mrmac_priv *priv = dev_get_priv(dev);
  383. priv->iobase = (struct mrmac_regs *)pdata->iobase;
  384. priv->mm2s_cmn = plat->mm2s_cmn;
  385. priv->mcdma_tx = (struct mcdma_chan_reg *)((phys_addr_t)priv->mm2s_cmn
  386. + XMCDMA_CHAN_OFFSET);
  387. priv->s2mm_cmn = (struct mcdma_common_regs *)((phys_addr_t)priv->mm2s_cmn
  388. + XMCDMA_RX_OFFSET);
  389. priv->mcdma_rx = (struct mcdma_chan_reg *)((phys_addr_t)priv->s2mm_cmn
  390. + XMCDMA_CHAN_OFFSET);
  391. priv->mrmac_rate = plat->mrmac_rate;
  392. /* Align buffers to ARCH_DMA_MINALIGN */
  393. priv->tx_bd[0] = memalign(ARCH_DMA_MINALIGN, TX_BD_TOTAL_SIZE);
  394. priv->tx_bd[1] = (struct mcdma_bd *)((ulong)priv->tx_bd[0] +
  395. sizeof(struct mcdma_bd));
  396. priv->rx_bd[0] = memalign(ARCH_DMA_MINALIGN, RX_BD_TOTAL_SIZE);
  397. priv->rx_bd[1] = (struct mcdma_bd *)((ulong)priv->rx_bd[0] +
  398. sizeof(struct mcdma_bd));
  399. priv->txminframe = memalign(ARCH_DMA_MINALIGN, MIN_PKT_SIZE);
  400. return 0;
  401. }
  402. static int axi_mrmac_remove(struct udevice *dev)
  403. {
  404. struct axi_mrmac_priv *priv = dev_get_priv(dev);
  405. /* Free buffer descriptors */
  406. free(priv->tx_bd[0]);
  407. free(priv->rx_bd[0]);
  408. free(priv->txminframe);
  409. return 0;
  410. }
  411. static int axi_mrmac_of_to_plat(struct udevice *dev)
  412. {
  413. struct axi_mrmac_plat *plat = dev_get_plat(dev);
  414. struct eth_pdata *pdata = &plat->eth_pdata;
  415. struct ofnode_phandle_args phandle_args;
  416. int ret = 0;
  417. pdata->iobase = dev_read_addr(dev);
  418. ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0,
  419. &phandle_args);
  420. if (ret) {
  421. log_debug("axistream not found\n");
  422. return -EINVAL;
  423. }
  424. plat->mm2s_cmn = (struct mcdma_common_regs *)ofnode_read_u64_default
  425. (phandle_args.node, "reg", -1);
  426. if (!plat->mm2s_cmn) {
  427. log_warning("MRMAC dma register space not found\n");
  428. return -EINVAL;
  429. }
  430. /* Set default MRMAC rate to 10000 */
  431. plat->mrmac_rate = dev_read_u32_default(dev, "xlnx,mrmac-rate", 10000);
  432. return 0;
  433. }
  434. static const struct eth_ops axi_mrmac_ops = {
  435. .start = axi_mrmac_start,
  436. .send = axi_mrmac_send,
  437. .recv = axi_mrmac_recv,
  438. .free_pkt = axi_mrmac_free_pkt,
  439. .stop = axi_mrmac_stop,
  440. };
  441. static const struct udevice_id axi_mrmac_ids[] = {
  442. { .compatible = "xlnx,mrmac-ethernet-1.0" },
  443. { }
  444. };
  445. U_BOOT_DRIVER(axi_mrmac) = {
  446. .name = "axi_mrmac",
  447. .id = UCLASS_ETH,
  448. .of_match = axi_mrmac_ids,
  449. .of_to_plat = axi_mrmac_of_to_plat,
  450. .probe = axi_mrmac_probe,
  451. .remove = axi_mrmac_remove,
  452. .ops = &axi_mrmac_ops,
  453. .priv_auto = sizeof(struct axi_mrmac_priv),
  454. .plat_auto = sizeof(struct axi_mrmac_plat),
  455. };