tsec.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale Three Speed Ethernet Controller driver
  4. *
  5. * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
  6. * (C) Copyright 2003, Motorola, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <command.h>
  15. #include <tsec.h>
  16. #include <fsl_mdio.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <miiphy.h>
  21. #include <asm/processor.h>
  22. #include <asm/io.h>
  23. #ifndef CONFIG_DM_ETH
  24. /* Default initializations for TSEC controllers. */
  25. static struct tsec_info_struct tsec_info[] = {
  26. #ifdef CONFIG_TSEC1
  27. STD_TSEC_INFO(1), /* TSEC1 */
  28. #endif
  29. #ifdef CONFIG_TSEC2
  30. STD_TSEC_INFO(2), /* TSEC2 */
  31. #endif
  32. #ifdef CONFIG_MPC85XX_FEC
  33. {
  34. .regs = TSEC_GET_REGS(2, 0x2000),
  35. .devname = CONFIG_MPC85XX_FEC_NAME,
  36. .phyaddr = FEC_PHY_ADDR,
  37. .flags = FEC_FLAGS,
  38. .mii_devname = DEFAULT_MII_NAME
  39. }, /* FEC */
  40. #endif
  41. #ifdef CONFIG_TSEC3
  42. STD_TSEC_INFO(3), /* TSEC3 */
  43. #endif
  44. #ifdef CONFIG_TSEC4
  45. STD_TSEC_INFO(4), /* TSEC4 */
  46. #endif
  47. };
  48. #endif /* CONFIG_DM_ETH */
  49. #define TBIANA_SETTINGS ( \
  50. TBIANA_ASYMMETRIC_PAUSE \
  51. | TBIANA_SYMMETRIC_PAUSE \
  52. | TBIANA_FULL_DUPLEX \
  53. )
  54. /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  55. #ifndef CONFIG_TSEC_TBICR_SETTINGS
  56. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  57. TBICR_PHY_RESET \
  58. | TBICR_ANEG_ENABLE \
  59. | TBICR_FULL_DUPLEX \
  60. | TBICR_SPEED1_SET \
  61. )
  62. #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  63. /* Configure the TBI for SGMII operation */
  64. static void tsec_configure_serdes(struct tsec_private *priv)
  65. {
  66. /*
  67. * Access TBI PHY registers at given TSEC register offset as opposed
  68. * to the register offset used for external PHY accesses
  69. */
  70. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  71. 0, TBI_ANA, TBIANA_SETTINGS);
  72. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  73. 0, TBI_TBICON, TBICON_CLK_SELECT);
  74. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  75. 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  76. }
  77. /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
  78. * and this is the ethernet-crc method needed for TSEC -- and perhaps
  79. * some other adapter -- hash tables
  80. */
  81. #define CRCPOLY_LE 0xedb88320
  82. static u32 ether_crc(size_t len, unsigned char const *p)
  83. {
  84. int i;
  85. u32 crc;
  86. crc = ~0;
  87. while (len--) {
  88. crc ^= *p++;
  89. for (i = 0; i < 8; i++)
  90. crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
  91. }
  92. /* an reverse the bits, cuz of way they arrive -- last-first */
  93. crc = (crc >> 16) | (crc << 16);
  94. crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
  95. crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
  96. crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
  97. crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
  98. return crc;
  99. }
  100. /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  101. /* Set the appropriate hash bit for the given addr */
  102. /*
  103. * The algorithm works like so:
  104. * 1) Take the Destination Address (ie the multicast address), and
  105. * do a CRC on it (little endian), and reverse the bits of the
  106. * result.
  107. * 2) Use the 8 most significant bits as a hash into a 256-entry
  108. * table. The table is controlled through 8 32-bit registers:
  109. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
  110. * 255. This means that the 3 most significant bits in the
  111. * hash index which gaddr register to use, and the 5 other bits
  112. * indicate which bit (assuming an IBM numbering scheme, which
  113. * for PowerPC (tm) is usually the case) in the register holds
  114. * the entry.
  115. */
  116. #ifndef CONFIG_DM_ETH
  117. static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
  118. int join)
  119. #else
  120. static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
  121. #endif
  122. {
  123. struct tsec_private *priv;
  124. struct tsec __iomem *regs;
  125. u32 result, value;
  126. u8 whichbit, whichreg;
  127. #ifndef CONFIG_DM_ETH
  128. priv = (struct tsec_private *)dev->priv;
  129. #else
  130. priv = dev_get_priv(dev);
  131. #endif
  132. regs = priv->regs;
  133. result = ether_crc(MAC_ADDR_LEN, mcast_mac);
  134. whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
  135. whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
  136. value = BIT(31 - whichbit);
  137. if (join)
  138. setbits_be32(&regs->hash.gaddr0 + whichreg, value);
  139. else
  140. clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
  141. return 0;
  142. }
  143. /*
  144. * Initialized required registers to appropriate values, zeroing
  145. * those we don't care about (unless zero is bad, in which case,
  146. * choose a more appropriate value)
  147. */
  148. static void init_registers(struct tsec __iomem *regs)
  149. {
  150. /* Clear IEVENT */
  151. out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
  152. out_be32(&regs->imask, IMASK_INIT_CLEAR);
  153. out_be32(&regs->hash.iaddr0, 0);
  154. out_be32(&regs->hash.iaddr1, 0);
  155. out_be32(&regs->hash.iaddr2, 0);
  156. out_be32(&regs->hash.iaddr3, 0);
  157. out_be32(&regs->hash.iaddr4, 0);
  158. out_be32(&regs->hash.iaddr5, 0);
  159. out_be32(&regs->hash.iaddr6, 0);
  160. out_be32(&regs->hash.iaddr7, 0);
  161. out_be32(&regs->hash.gaddr0, 0);
  162. out_be32(&regs->hash.gaddr1, 0);
  163. out_be32(&regs->hash.gaddr2, 0);
  164. out_be32(&regs->hash.gaddr3, 0);
  165. out_be32(&regs->hash.gaddr4, 0);
  166. out_be32(&regs->hash.gaddr5, 0);
  167. out_be32(&regs->hash.gaddr6, 0);
  168. out_be32(&regs->hash.gaddr7, 0);
  169. out_be32(&regs->rctrl, 0x00000000);
  170. /* Init RMON mib registers */
  171. memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
  172. out_be32(&regs->rmon.cam1, 0xffffffff);
  173. out_be32(&regs->rmon.cam2, 0xffffffff);
  174. out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
  175. out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
  176. out_be32(&regs->attr, ATTR_INIT_SETTINGS);
  177. out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
  178. }
  179. /*
  180. * Configure maccfg2 based on negotiated speed and duplex
  181. * reported by PHY handling code
  182. */
  183. static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
  184. {
  185. struct tsec __iomem *regs = priv->regs;
  186. u32 ecntrl, maccfg2;
  187. if (!phydev->link) {
  188. printf("%s: No link.\n", phydev->dev->name);
  189. return;
  190. }
  191. /* clear all bits relative with interface mode */
  192. ecntrl = in_be32(&regs->ecntrl);
  193. ecntrl &= ~ECNTRL_R100;
  194. maccfg2 = in_be32(&regs->maccfg2);
  195. maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
  196. if (phydev->duplex)
  197. maccfg2 |= MACCFG2_FULL_DUPLEX;
  198. switch (phydev->speed) {
  199. case 1000:
  200. maccfg2 |= MACCFG2_GMII;
  201. break;
  202. case 100:
  203. case 10:
  204. maccfg2 |= MACCFG2_MII;
  205. /*
  206. * Set R100 bit in all modes although
  207. * it is only used in RGMII mode
  208. */
  209. if (phydev->speed == 100)
  210. ecntrl |= ECNTRL_R100;
  211. break;
  212. default:
  213. printf("%s: Speed was bad\n", phydev->dev->name);
  214. break;
  215. }
  216. out_be32(&regs->ecntrl, ecntrl);
  217. out_be32(&regs->maccfg2, maccfg2);
  218. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  219. (phydev->duplex) ? "full" : "half",
  220. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  221. }
  222. /*
  223. * This returns the status bits of the device. The return value
  224. * is never checked, and this is what the 8260 driver did, so we
  225. * do the same. Presumably, this would be zero if there were no
  226. * errors
  227. */
  228. #ifndef CONFIG_DM_ETH
  229. static int tsec_send(struct eth_device *dev, void *packet, int length)
  230. #else
  231. static int tsec_send(struct udevice *dev, void *packet, int length)
  232. #endif
  233. {
  234. struct tsec_private *priv;
  235. struct tsec __iomem *regs;
  236. int result = 0;
  237. u16 status;
  238. int i;
  239. #ifndef CONFIG_DM_ETH
  240. priv = (struct tsec_private *)dev->priv;
  241. #else
  242. priv = dev_get_priv(dev);
  243. #endif
  244. regs = priv->regs;
  245. /* Find an empty buffer descriptor */
  246. for (i = 0;
  247. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  248. i++) {
  249. if (i >= TOUT_LOOP) {
  250. printf("%s: tsec: tx buffers full\n", dev->name);
  251. return result;
  252. }
  253. }
  254. out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
  255. out_be16(&priv->txbd[priv->tx_idx].length, length);
  256. status = in_be16(&priv->txbd[priv->tx_idx].status);
  257. out_be16(&priv->txbd[priv->tx_idx].status, status |
  258. (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
  259. /* Tell the DMA to go */
  260. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  261. /* Wait for buffer to be transmitted */
  262. for (i = 0;
  263. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  264. i++) {
  265. if (i >= TOUT_LOOP) {
  266. printf("%s: tsec: tx error\n", dev->name);
  267. return result;
  268. }
  269. }
  270. priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
  271. result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
  272. return result;
  273. }
  274. #ifndef CONFIG_DM_ETH
  275. static int tsec_recv(struct eth_device *dev)
  276. {
  277. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  278. struct tsec __iomem *regs = priv->regs;
  279. while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  280. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  281. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  282. uchar *packet = net_rx_packets[priv->rx_idx];
  283. /* Send the packet up if there were no errors */
  284. if (!(status & RXBD_STATS))
  285. net_process_received_packet(packet, length - 4);
  286. else
  287. printf("Got error %x\n", (status & RXBD_STATS));
  288. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  289. status = RXBD_EMPTY;
  290. /* Set the wrap bit if this is the last element in the list */
  291. if ((priv->rx_idx + 1) == PKTBUFSRX)
  292. status |= RXBD_WRAP;
  293. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  294. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  295. }
  296. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  297. out_be32(&regs->ievent, IEVENT_BSY);
  298. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  299. }
  300. return -1;
  301. }
  302. #else
  303. static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
  304. {
  305. struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
  306. struct tsec __iomem *regs = priv->regs;
  307. int ret = -1;
  308. if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  309. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  310. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  311. u32 buf;
  312. /* Send the packet up if there were no errors */
  313. if (!(status & RXBD_STATS)) {
  314. buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
  315. *packetp = (uchar *)buf;
  316. ret = length - 4;
  317. } else {
  318. printf("Got error %x\n", (status & RXBD_STATS));
  319. }
  320. }
  321. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  322. out_be32(&regs->ievent, IEVENT_BSY);
  323. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  324. }
  325. return ret;
  326. }
  327. static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
  328. {
  329. struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
  330. u16 status;
  331. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  332. status = RXBD_EMPTY;
  333. /* Set the wrap bit if this is the last element in the list */
  334. if ((priv->rx_idx + 1) == PKTBUFSRX)
  335. status |= RXBD_WRAP;
  336. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  337. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  338. return 0;
  339. }
  340. #endif
  341. /* Stop the interface */
  342. #ifndef CONFIG_DM_ETH
  343. static void tsec_halt(struct eth_device *dev)
  344. #else
  345. static void tsec_halt(struct udevice *dev)
  346. #endif
  347. {
  348. struct tsec_private *priv;
  349. struct tsec __iomem *regs;
  350. #ifndef CONFIG_DM_ETH
  351. priv = (struct tsec_private *)dev->priv;
  352. #else
  353. priv = dev_get_priv(dev);
  354. #endif
  355. regs = priv->regs;
  356. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  357. setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  358. while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
  359. != (IEVENT_GRSC | IEVENT_GTSC))
  360. ;
  361. clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
  362. /* Shut down the PHY, as needed */
  363. phy_shutdown(priv->phydev);
  364. }
  365. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  366. /*
  367. * When MACCFG1[Rx_EN] is enabled during system boot as part
  368. * of the eTSEC port initialization sequence,
  369. * the eTSEC Rx logic may not be properly initialized.
  370. */
  371. void redundant_init(struct tsec_private *priv)
  372. {
  373. struct tsec __iomem *regs = priv->regs;
  374. uint t, count = 0;
  375. int fail = 1;
  376. static const u8 pkt[] = {
  377. 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
  378. 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
  379. 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
  380. 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
  381. 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
  382. 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
  383. 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
  384. 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
  385. 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
  386. 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  387. 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
  388. 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
  389. 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
  390. 0x71, 0x72};
  391. /* Enable promiscuous mode */
  392. setbits_be32(&regs->rctrl, 0x8);
  393. /* Enable loopback mode */
  394. setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  395. /* Enable transmit and receive */
  396. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  397. /* Tell the DMA it is clear to go */
  398. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  399. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  400. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  401. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  402. do {
  403. u16 status;
  404. tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
  405. /* Wait for buffer to be received */
  406. for (t = 0;
  407. in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
  408. t++) {
  409. if (t >= 10 * TOUT_LOOP) {
  410. printf("%s: tsec: rx error\n", priv->dev->name);
  411. break;
  412. }
  413. }
  414. if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
  415. fail = 0;
  416. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  417. status = RXBD_EMPTY;
  418. if ((priv->rx_idx + 1) == PKTBUFSRX)
  419. status |= RXBD_WRAP;
  420. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  421. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  422. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  423. out_be32(&regs->ievent, IEVENT_BSY);
  424. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  425. }
  426. if (fail) {
  427. printf("loopback recv packet error!\n");
  428. clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  429. udelay(1000);
  430. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  431. }
  432. } while ((count++ < 4) && (fail == 1));
  433. if (fail)
  434. panic("eTSEC init fail!\n");
  435. /* Disable promiscuous mode */
  436. clrbits_be32(&regs->rctrl, 0x8);
  437. /* Disable loopback mode */
  438. clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  439. }
  440. #endif
  441. /*
  442. * Set up the buffers and their descriptors, and bring up the
  443. * interface
  444. */
  445. static void startup_tsec(struct tsec_private *priv)
  446. {
  447. struct tsec __iomem *regs = priv->regs;
  448. u16 status;
  449. int i;
  450. /* reset the indices to zero */
  451. priv->rx_idx = 0;
  452. priv->tx_idx = 0;
  453. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  454. uint svr;
  455. #endif
  456. /* Point to the buffer descriptors */
  457. out_be32(&regs->tbase, (u32)&priv->txbd[0]);
  458. out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
  459. /* Initialize the Rx Buffer descriptors */
  460. for (i = 0; i < PKTBUFSRX; i++) {
  461. out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
  462. out_be16(&priv->rxbd[i].length, 0);
  463. out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
  464. }
  465. status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
  466. out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
  467. /* Initialize the TX Buffer Descriptors */
  468. for (i = 0; i < TX_BUF_CNT; i++) {
  469. out_be16(&priv->txbd[i].status, 0);
  470. out_be16(&priv->txbd[i].length, 0);
  471. out_be32(&priv->txbd[i].bufptr, 0);
  472. }
  473. status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
  474. out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
  475. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  476. svr = get_svr();
  477. if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
  478. redundant_init(priv);
  479. #endif
  480. /* Enable Transmit and Receive */
  481. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  482. /* Tell the DMA it is clear to go */
  483. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  484. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  485. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  486. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  487. }
  488. /*
  489. * Initializes data structures and registers for the controller,
  490. * and brings the interface up. Returns the link status, meaning
  491. * that it returns success if the link is up, failure otherwise.
  492. * This allows U-Boot to find the first active controller.
  493. */
  494. #ifndef CONFIG_DM_ETH
  495. static int tsec_init(struct eth_device *dev, struct bd_info *bd)
  496. #else
  497. static int tsec_init(struct udevice *dev)
  498. #endif
  499. {
  500. struct tsec_private *priv;
  501. struct tsec __iomem *regs;
  502. #ifdef CONFIG_DM_ETH
  503. struct eth_pdata *pdata = dev_get_plat(dev);
  504. #else
  505. struct eth_device *pdata = dev;
  506. #endif
  507. u32 tempval;
  508. int ret;
  509. #ifndef CONFIG_DM_ETH
  510. priv = (struct tsec_private *)dev->priv;
  511. #else
  512. priv = dev_get_priv(dev);
  513. #endif
  514. regs = priv->regs;
  515. /* Make sure the controller is stopped */
  516. tsec_halt(dev);
  517. /* Init MACCFG2. Defaults to GMII */
  518. out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  519. /* Init ECNTRL */
  520. out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  521. /*
  522. * Copy the station address into the address registers.
  523. * For a station address of 0x12345678ABCD in transmission
  524. * order (BE), MACnADDR1 is set to 0xCDAB7856 and
  525. * MACnADDR2 is set to 0x34120000.
  526. */
  527. tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
  528. (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
  529. out_be32(&regs->macstnaddr1, tempval);
  530. tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
  531. out_be32(&regs->macstnaddr2, tempval);
  532. /* Clear out (for the most part) the other registers */
  533. init_registers(regs);
  534. /* Ready the device for tx/rx */
  535. startup_tsec(priv);
  536. /* Start up the PHY */
  537. ret = phy_startup(priv->phydev);
  538. if (ret) {
  539. printf("Could not initialize PHY %s\n",
  540. priv->phydev->dev->name);
  541. return ret;
  542. }
  543. adjust_link(priv, priv->phydev);
  544. /* If there's no link, fail */
  545. return priv->phydev->link ? 0 : -1;
  546. }
  547. static phy_interface_t tsec_get_interface(struct tsec_private *priv)
  548. {
  549. struct tsec __iomem *regs = priv->regs;
  550. u32 ecntrl;
  551. ecntrl = in_be32(&regs->ecntrl);
  552. if (ecntrl & ECNTRL_SGMII_MODE)
  553. return PHY_INTERFACE_MODE_SGMII;
  554. if (ecntrl & ECNTRL_TBI_MODE) {
  555. if (ecntrl & ECNTRL_REDUCED_MODE)
  556. return PHY_INTERFACE_MODE_RTBI;
  557. else
  558. return PHY_INTERFACE_MODE_TBI;
  559. }
  560. if (ecntrl & ECNTRL_REDUCED_MODE) {
  561. phy_interface_t interface;
  562. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  563. return PHY_INTERFACE_MODE_RMII;
  564. interface = priv->interface;
  565. /*
  566. * This isn't autodetected, so it must
  567. * be set by the platform code.
  568. */
  569. if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
  570. interface == PHY_INTERFACE_MODE_RGMII_TXID ||
  571. interface == PHY_INTERFACE_MODE_RGMII_RXID)
  572. return interface;
  573. return PHY_INTERFACE_MODE_RGMII;
  574. }
  575. if (priv->flags & TSEC_GIGABIT)
  576. return PHY_INTERFACE_MODE_GMII;
  577. return PHY_INTERFACE_MODE_MII;
  578. }
  579. /*
  580. * Discover which PHY is attached to the device, and configure it
  581. * properly. If the PHY is not recognized, then return 0
  582. * (failure). Otherwise, return 1
  583. */
  584. static int init_phy(struct tsec_private *priv)
  585. {
  586. struct phy_device *phydev;
  587. struct tsec __iomem *regs = priv->regs;
  588. u32 supported = (SUPPORTED_10baseT_Half |
  589. SUPPORTED_10baseT_Full |
  590. SUPPORTED_100baseT_Half |
  591. SUPPORTED_100baseT_Full);
  592. if (priv->flags & TSEC_GIGABIT)
  593. supported |= SUPPORTED_1000baseT_Full;
  594. /* Assign a Physical address to the TBI */
  595. out_be32(&regs->tbipa, priv->tbiaddr);
  596. priv->interface = tsec_get_interface(priv);
  597. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  598. tsec_configure_serdes(priv);
  599. #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
  600. phydev = dm_eth_phy_connect(priv->dev);
  601. #else
  602. phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
  603. priv->interface);
  604. #endif
  605. if (!phydev)
  606. return 0;
  607. phydev->supported &= supported;
  608. phydev->advertising = phydev->supported;
  609. priv->phydev = phydev;
  610. phy_config(phydev);
  611. return 1;
  612. }
  613. #ifndef CONFIG_DM_ETH
  614. /*
  615. * Initialize device structure. Returns success if PHY
  616. * initialization succeeded (i.e. if it recognizes the PHY)
  617. */
  618. static int tsec_initialize(struct bd_info *bis,
  619. struct tsec_info_struct *tsec_info)
  620. {
  621. struct tsec_private *priv;
  622. struct eth_device *dev;
  623. int i;
  624. dev = (struct eth_device *)malloc(sizeof(*dev));
  625. if (!dev)
  626. return 0;
  627. memset(dev, 0, sizeof(*dev));
  628. priv = (struct tsec_private *)malloc(sizeof(*priv));
  629. if (!priv) {
  630. free(dev);
  631. return 0;
  632. }
  633. priv->regs = tsec_info->regs;
  634. priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
  635. priv->phyaddr = tsec_info->phyaddr;
  636. priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  637. priv->flags = tsec_info->flags;
  638. strcpy(dev->name, tsec_info->devname);
  639. priv->interface = tsec_info->interface;
  640. priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
  641. priv->dev = dev;
  642. dev->iobase = 0;
  643. dev->priv = priv;
  644. dev->init = tsec_init;
  645. dev->halt = tsec_halt;
  646. dev->send = tsec_send;
  647. dev->recv = tsec_recv;
  648. dev->mcast = tsec_mcast_addr;
  649. /* Tell U-Boot to get the addr from the env */
  650. for (i = 0; i < 6; i++)
  651. dev->enetaddr[i] = 0;
  652. eth_register(dev);
  653. /* Reset the MAC */
  654. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  655. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  656. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  657. /* Try to initialize PHY here, and return */
  658. return init_phy(priv);
  659. }
  660. /*
  661. * Initialize all the TSEC devices
  662. *
  663. * Returns the number of TSEC devices that were initialized
  664. */
  665. int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
  666. int num)
  667. {
  668. int i;
  669. int count = 0;
  670. for (i = 0; i < num; i++) {
  671. int ret = tsec_initialize(bis, &tsecs[i]);
  672. if (ret > 0)
  673. count += ret;
  674. }
  675. return count;
  676. }
  677. int tsec_standard_init(struct bd_info *bis)
  678. {
  679. struct fsl_pq_mdio_info info;
  680. info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  681. info.name = DEFAULT_MII_NAME;
  682. fsl_pq_mdio_init(bis, &info);
  683. return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
  684. }
  685. #else /* CONFIG_DM_ETH */
  686. int tsec_probe(struct udevice *dev)
  687. {
  688. struct eth_pdata *pdata = dev_get_plat(dev);
  689. struct tsec_private *priv = dev_get_priv(dev);
  690. struct ofnode_phandle_args phandle_args;
  691. u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  692. struct tsec_data *data;
  693. const char *phy_mode;
  694. ofnode parent, child;
  695. fdt_addr_t reg;
  696. u32 max_speed;
  697. int ret;
  698. data = (struct tsec_data *)dev_get_driver_data(dev);
  699. pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  700. if (pdata->iobase == FDT_ADDR_T_NONE) {
  701. ofnode_for_each_subnode(child, dev_ofnode(dev)) {
  702. if (strncmp(ofnode_get_name(child), "queue-group",
  703. strlen("queue-group")))
  704. continue;
  705. reg = ofnode_get_addr(child);
  706. if (reg == FDT_ADDR_T_NONE) {
  707. printf("No 'reg' property of <queue-group>\n");
  708. return -ENOENT;
  709. }
  710. pdata->iobase = reg;
  711. /*
  712. * if there are multiple queue groups,
  713. * only the first one is used.
  714. */
  715. break;
  716. }
  717. if (!ofnode_valid(child)) {
  718. printf("No child node for <queue-group>?\n");
  719. return -ENOENT;
  720. }
  721. }
  722. priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
  723. ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
  724. &phandle_args);
  725. if (ret == 0) {
  726. ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
  727. parent = ofnode_get_parent(phandle_args.node);
  728. if (!ofnode_valid(parent)) {
  729. printf("No parent node for TBI PHY?\n");
  730. return -ENOENT;
  731. }
  732. reg = ofnode_get_addr_index(parent, 0);
  733. if (reg == FDT_ADDR_T_NONE) {
  734. printf("No 'reg' property of MII for TBI PHY\n");
  735. return -ENOENT;
  736. }
  737. priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
  738. 0, MAP_NOCACHE);
  739. }
  740. priv->tbiaddr = tbiaddr;
  741. phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
  742. if (phy_mode)
  743. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  744. if (pdata->phy_interface == -1) {
  745. printf("Invalid PHY interface '%s'\n", phy_mode);
  746. return -EINVAL;
  747. }
  748. priv->interface = pdata->phy_interface;
  749. /* Check for speed limit, default is 1000Mbps */
  750. max_speed = dev_read_u32_default(dev, "max-speed", 1000);
  751. /* Initialize flags */
  752. if (max_speed == 1000)
  753. priv->flags = TSEC_GIGABIT;
  754. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  755. priv->flags |= TSEC_SGMII;
  756. /* Reset the MAC */
  757. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  758. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  759. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  760. priv->dev = dev;
  761. priv->bus = miiphy_get_dev_by_name(dev->name);
  762. /* Try to initialize PHY here, and return */
  763. return !init_phy(priv);
  764. }
  765. int tsec_remove(struct udevice *dev)
  766. {
  767. struct tsec_private *priv = dev_get_priv(dev);
  768. free(priv->phydev);
  769. mdio_unregister(priv->bus);
  770. mdio_free(priv->bus);
  771. return 0;
  772. }
  773. static const struct eth_ops tsec_ops = {
  774. .start = tsec_init,
  775. .send = tsec_send,
  776. .recv = tsec_recv,
  777. .free_pkt = tsec_free_pkt,
  778. .stop = tsec_halt,
  779. .mcast = tsec_mcast_addr,
  780. };
  781. static struct tsec_data etsec2_data = {
  782. .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
  783. };
  784. static struct tsec_data gianfar_data = {
  785. .mdio_regs_off = 0x0,
  786. };
  787. static const struct udevice_id tsec_ids[] = {
  788. { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
  789. { .compatible = "gianfar", .data = (ulong)&gianfar_data },
  790. { }
  791. };
  792. U_BOOT_DRIVER(eth_tsec) = {
  793. .name = "tsec",
  794. .id = UCLASS_ETH,
  795. .of_match = tsec_ids,
  796. .probe = tsec_probe,
  797. .remove = tsec_remove,
  798. .ops = &tsec_ops,
  799. .priv_auto = sizeof(struct tsec_private),
  800. .plat_auto = sizeof(struct eth_pdata),
  801. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  802. };
  803. #endif /* CONFIG_DM_ETH */