pic32_eth.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <errno.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <net.h>
  13. #include <miiphy.h>
  14. #include <console.h>
  15. #include <time.h>
  16. #include <wait_bit.h>
  17. #include <asm/global_data.h>
  18. #include <asm/gpio.h>
  19. #include <linux/delay.h>
  20. #include <linux/mii.h>
  21. #include "pic32_eth.h"
  22. #define MAX_RX_BUF_SIZE 1536
  23. #define MAX_RX_DESCR PKTBUFSRX
  24. #define MAX_TX_DESCR 2
  25. DECLARE_GLOBAL_DATA_PTR;
  26. struct pic32eth_dev {
  27. struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
  28. struct eth_dma_desc txd_ring[MAX_TX_DESCR];
  29. u32 rxd_idx; /* index of RX desc to read */
  30. /* regs */
  31. struct pic32_ectl_regs *ectl_regs;
  32. struct pic32_emac_regs *emac_regs;
  33. /* Phy */
  34. struct phy_device *phydev;
  35. phy_interface_t phyif;
  36. u32 phy_addr;
  37. struct gpio_desc rst_gpio;
  38. };
  39. void __weak board_netphy_reset(void *dev)
  40. {
  41. struct pic32eth_dev *priv = dev;
  42. if (!dm_gpio_is_valid(&priv->rst_gpio))
  43. return;
  44. /* phy reset */
  45. dm_gpio_set_value(&priv->rst_gpio, 0);
  46. udelay(300);
  47. dm_gpio_set_value(&priv->rst_gpio, 1);
  48. udelay(300);
  49. }
  50. /* Initialize mii(MDIO) interface, discover which PHY is
  51. * attached to the device, and configure it properly.
  52. */
  53. static int pic32_mii_init(struct pic32eth_dev *priv)
  54. {
  55. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  56. struct pic32_emac_regs *emac_p = priv->emac_regs;
  57. /* board phy reset */
  58. board_netphy_reset(priv);
  59. /* disable RX, TX & all transactions */
  60. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  61. /* wait till busy */
  62. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  63. CONFIG_SYS_HZ, false);
  64. /* turn controller ON to access PHY over MII */
  65. writel(ETHCON_ON, &ectl_p->con1.set);
  66. mdelay(10);
  67. /* reset MAC */
  68. writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
  69. mdelay(10);
  70. writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
  71. /* initialize MDIO/MII */
  72. if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
  73. writel(EMAC_RMII_RESET, &emac_p->supp.set);
  74. mdelay(10);
  75. writel(EMAC_RMII_RESET, &emac_p->supp.clr);
  76. }
  77. return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
  78. }
  79. static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
  80. {
  81. struct mii_dev *mii;
  82. mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  83. /* find & connect PHY */
  84. priv->phydev = phy_connect(mii, priv->phy_addr,
  85. dev, priv->phyif);
  86. if (!priv->phydev) {
  87. printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
  88. return 0;
  89. }
  90. /* Wait for phy to complete reset */
  91. mdelay(10);
  92. /* configure supported modes */
  93. priv->phydev->supported = SUPPORTED_10baseT_Half |
  94. SUPPORTED_10baseT_Full |
  95. SUPPORTED_100baseT_Half |
  96. SUPPORTED_100baseT_Full |
  97. SUPPORTED_Autoneg;
  98. priv->phydev->advertising = ADVERTISED_10baseT_Half |
  99. ADVERTISED_10baseT_Full |
  100. ADVERTISED_100baseT_Half |
  101. ADVERTISED_100baseT_Full |
  102. ADVERTISED_Autoneg;
  103. priv->phydev->autoneg = AUTONEG_ENABLE;
  104. return 0;
  105. }
  106. /* Configure MAC based on negotiated speed and duplex
  107. * reported by PHY.
  108. */
  109. static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
  110. {
  111. struct phy_device *phydev = priv->phydev;
  112. struct pic32_emac_regs *emac_p = priv->emac_regs;
  113. if (!phydev->link) {
  114. printf("%s: No link.\n", phydev->dev->name);
  115. return -EINVAL;
  116. }
  117. if (phydev->duplex) {
  118. writel(EMAC_FULLDUP, &emac_p->cfg2.set);
  119. writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
  120. } else {
  121. writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
  122. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  123. }
  124. switch (phydev->speed) {
  125. case SPEED_100:
  126. writel(EMAC_RMII_SPD100, &emac_p->supp.set);
  127. break;
  128. case SPEED_10:
  129. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  130. break;
  131. default:
  132. printf("%s: Speed was bad\n", phydev->dev->name);
  133. return -EINVAL;
  134. }
  135. printf("pic32eth: PHY is %s with %dbase%s, %s\n",
  136. phydev->drv->name, phydev->speed,
  137. (phydev->port == PORT_TP) ? "T" : "X",
  138. (phydev->duplex) ? "full" : "half");
  139. return 0;
  140. }
  141. static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
  142. {
  143. struct pic32_emac_regs *emac_p = priv->emac_regs;
  144. u32 stat = 0, v;
  145. u64 expire;
  146. v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
  147. writel(v, &emac_p->cfg1.raw);
  148. v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
  149. EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
  150. writel(v, &emac_p->cfg2.raw);
  151. /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
  152. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  153. /* recommended non-back-to-back interpacket gap is 0xc12 */
  154. writel(0xc12, &emac_p->ipgr.raw);
  155. /* recommended collision window retry limit is 0x370F */
  156. writel(0x370f, &emac_p->clrt.raw);
  157. /* set maximum frame length: allow VLAN tagged frame */
  158. writel(0x600, &emac_p->maxf.raw);
  159. /* set the mac address */
  160. writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
  161. writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
  162. writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
  163. /* default, enable 10 Mbps operation */
  164. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  165. /* wait until link status UP or deadline elapsed */
  166. expire = get_ticks() + get_tbclk() * 2;
  167. for (; get_ticks() < expire;) {
  168. stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
  169. if (stat & BMSR_LSTATUS)
  170. break;
  171. }
  172. if (!(stat & BMSR_LSTATUS))
  173. printf("MAC: Link is DOWN!\n");
  174. /* delay to stabilize before any tx/rx */
  175. mdelay(10);
  176. }
  177. static void pic32_mac_reset(struct pic32eth_dev *priv)
  178. {
  179. struct pic32_emac_regs *emac_p = priv->emac_regs;
  180. struct mii_dev *mii;
  181. /* Reset MAC */
  182. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  183. mdelay(10);
  184. /* clear reset */
  185. writel(0, &emac_p->cfg1.raw);
  186. /* Reset MII */
  187. mii = priv->phydev->bus;
  188. if (mii && mii->reset)
  189. mii->reset(mii);
  190. }
  191. /* initializes the MAC and PHY, then establishes a link */
  192. static void pic32_ctrl_reset(struct pic32eth_dev *priv)
  193. {
  194. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  195. u32 v;
  196. /* disable RX, TX & any other transactions */
  197. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  198. /* wait till busy */
  199. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  200. CONFIG_SYS_HZ, false);
  201. /* decrement received buffcnt to zero. */
  202. while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
  203. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  204. /* clear any existing interrupt event */
  205. writel(0xffffffff, &ectl_p->irq.clr);
  206. /* clear RX/TX start address */
  207. writel(0xffffffff, &ectl_p->txst.clr);
  208. writel(0xffffffff, &ectl_p->rxst.clr);
  209. /* clear the receive filters */
  210. writel(0x00ff, &ectl_p->rxfc.clr);
  211. /* set the receive filters
  212. * ETH_FILT_CRC_ERR_REJECT
  213. * ETH_FILT_RUNT_REJECT
  214. * ETH_FILT_UCAST_ACCEPT
  215. * ETH_FILT_MCAST_ACCEPT
  216. * ETH_FILT_BCAST_ACCEPT
  217. */
  218. v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
  219. ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
  220. writel(v, &ectl_p->rxfc.set);
  221. /* turn controller ON to access PHY over MII */
  222. writel(ETHCON_ON, &ectl_p->con1.set);
  223. }
  224. static void pic32_rx_desc_init(struct pic32eth_dev *priv)
  225. {
  226. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  227. struct eth_dma_desc *rxd;
  228. u32 idx, bufsz;
  229. priv->rxd_idx = 0;
  230. for (idx = 0; idx < MAX_RX_DESCR; idx++) {
  231. rxd = &priv->rxd_ring[idx];
  232. /* hw owned */
  233. rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
  234. /* packet buffer address */
  235. rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
  236. /* link to next desc */
  237. rxd->next_ed = virt_to_phys(rxd + 1);
  238. /* reset status */
  239. rxd->stat1 = 0;
  240. rxd->stat2 = 0;
  241. /* decrement bufcnt */
  242. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  243. }
  244. /* link last descr to beginning of list */
  245. rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
  246. /* flush rx ring */
  247. flush_dcache_range((ulong)priv->rxd_ring,
  248. (ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
  249. /* set rx desc-ring start address */
  250. writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
  251. /* RX Buffer size */
  252. bufsz = readl(&ectl_p->con2.raw);
  253. bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
  254. bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
  255. writel(bufsz, &ectl_p->con2.raw);
  256. /* enable the receiver in hardware which allows hardware
  257. * to DMA received pkts to the descriptor pointer address.
  258. */
  259. writel(ETHCON_RXEN, &ectl_p->con1.set);
  260. }
  261. static int pic32_eth_start(struct udevice *dev)
  262. {
  263. struct eth_pdata *pdata = dev_get_plat(dev);
  264. struct pic32eth_dev *priv = dev_get_priv(dev);
  265. /* controller */
  266. pic32_ctrl_reset(priv);
  267. /* reset MAC */
  268. pic32_mac_reset(priv);
  269. /* configure PHY */
  270. phy_config(priv->phydev);
  271. /* initialize MAC */
  272. pic32_mac_init(priv, &pdata->enetaddr[0]);
  273. /* init RX descriptor; TX descriptors are handled in xmit */
  274. pic32_rx_desc_init(priv);
  275. /* Start up & update link status of PHY */
  276. phy_startup(priv->phydev);
  277. /* adjust mac with phy link status */
  278. return pic32_mac_adjust_link(priv);
  279. }
  280. static void pic32_eth_stop(struct udevice *dev)
  281. {
  282. struct pic32eth_dev *priv = dev_get_priv(dev);
  283. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  284. struct pic32_emac_regs *emac_p = priv->emac_regs;
  285. /* Reset the phy if the controller is enabled */
  286. if (readl(&ectl_p->con1.raw) & ETHCON_ON)
  287. phy_reset(priv->phydev);
  288. /* Shut down the PHY */
  289. phy_shutdown(priv->phydev);
  290. /* Stop rx/tx */
  291. writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  292. mdelay(10);
  293. /* reset MAC */
  294. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  295. /* clear reset */
  296. writel(0, &emac_p->cfg1.raw);
  297. mdelay(10);
  298. /* disable controller */
  299. writel(ETHCON_ON, &ectl_p->con1.clr);
  300. mdelay(10);
  301. /* wait until everything is down */
  302. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  303. 2 * CONFIG_SYS_HZ, false);
  304. /* clear any existing interrupt event */
  305. writel(0xffffffff, &ectl_p->irq.clr);
  306. }
  307. static int pic32_eth_send(struct udevice *dev, void *packet, int length)
  308. {
  309. struct pic32eth_dev *priv = dev_get_priv(dev);
  310. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  311. struct eth_dma_desc *txd;
  312. u64 deadline;
  313. txd = &priv->txd_ring[0];
  314. /* set proper flags & length in descriptor header */
  315. txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
  316. /* pass buffer address to hardware */
  317. txd->data_buff = virt_to_phys(packet);
  318. debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
  319. __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
  320. txd->next_ed);
  321. /* cache flush (packet) */
  322. flush_dcache_range((ulong)packet, (ulong)packet + length);
  323. /* cache flush (txd) */
  324. flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  325. /* pass descriptor table base to h/w */
  326. writel(virt_to_phys(txd), &ectl_p->txst.raw);
  327. /* ready to send enabled, hardware can now send the packet(s) */
  328. writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
  329. /* wait until tx has completed and h/w has released ownership
  330. * of the tx descriptor or timeout elapsed.
  331. */
  332. deadline = get_ticks() + get_tbclk();
  333. for (;;) {
  334. /* check timeout */
  335. if (get_ticks() > deadline)
  336. return -ETIMEDOUT;
  337. if (ctrlc())
  338. return -EINTR;
  339. /* tx completed ? */
  340. if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
  341. udelay(1);
  342. continue;
  343. }
  344. /* h/w not released ownership yet? */
  345. invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  346. if (!(txd->hdr & EDH_EOWN))
  347. break;
  348. }
  349. return 0;
  350. }
  351. static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  352. {
  353. struct pic32eth_dev *priv = dev_get_priv(dev);
  354. struct eth_dma_desc *rxd;
  355. u32 idx = priv->rxd_idx;
  356. u32 rx_count;
  357. /* find the next ready to receive */
  358. rxd = &priv->rxd_ring[idx];
  359. invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  360. /* check if owned by MAC */
  361. if (rxd->hdr & EDH_EOWN)
  362. return -EAGAIN;
  363. /* Sanity check on header: SOP and EOP */
  364. if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
  365. printf("%s: %s, rx pkt across multiple descr\n",
  366. __FILE__, __func__);
  367. return 0;
  368. }
  369. debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
  370. __func__, __LINE__, idx, rxd->hdr,
  371. rxd->data_buff, rxd->stat2, rxd->next_ed);
  372. /* Sanity check on rx_stat: OK, CRC */
  373. if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
  374. debug("%s: %s: Error, rx problem detected\n",
  375. __FILE__, __func__);
  376. return 0;
  377. }
  378. /* invalidate dcache */
  379. rx_count = RSV_RX_COUNT(rxd->stat2);
  380. invalidate_dcache_range((ulong)net_rx_packets[idx],
  381. (ulong)net_rx_packets[idx] + rx_count);
  382. /* Pass the packet to protocol layer */
  383. *packetp = net_rx_packets[idx];
  384. /* increment number of bytes rcvd (ignore CRC) */
  385. return rx_count - 4;
  386. }
  387. static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  388. {
  389. struct pic32eth_dev *priv = dev_get_priv(dev);
  390. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  391. struct eth_dma_desc *rxd;
  392. int idx = priv->rxd_idx;
  393. /* sanity check */
  394. if (packet != net_rx_packets[idx]) {
  395. printf("rxd_id %d: packet is not matched,\n", idx);
  396. return -EAGAIN;
  397. }
  398. /* prepare for receive */
  399. rxd = &priv->rxd_ring[idx];
  400. rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
  401. flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  402. /* decrement rx pkt count */
  403. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  404. debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
  405. __func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
  406. rxd->stat2, rxd->next_ed);
  407. priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
  408. return 0;
  409. }
  410. static const struct eth_ops pic32_eth_ops = {
  411. .start = pic32_eth_start,
  412. .send = pic32_eth_send,
  413. .recv = pic32_eth_recv,
  414. .free_pkt = pic32_eth_free_pkt,
  415. .stop = pic32_eth_stop,
  416. };
  417. static int pic32_eth_probe(struct udevice *dev)
  418. {
  419. struct eth_pdata *pdata = dev_get_plat(dev);
  420. struct pic32eth_dev *priv = dev_get_priv(dev);
  421. const char *phy_mode;
  422. void __iomem *iobase;
  423. fdt_addr_t addr;
  424. fdt_size_t size;
  425. int offset = 0;
  426. int phy_addr = -1;
  427. addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
  428. &size);
  429. if (addr == FDT_ADDR_T_NONE)
  430. return -EINVAL;
  431. iobase = ioremap(addr, size);
  432. pdata->iobase = (phys_addr_t)addr;
  433. /* get phy mode */
  434. pdata->phy_interface = -1;
  435. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  436. NULL);
  437. if (phy_mode)
  438. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  439. if (pdata->phy_interface == -1) {
  440. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  441. return -EINVAL;
  442. }
  443. /* get phy addr */
  444. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  445. "phy-handle");
  446. if (offset > 0)
  447. phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  448. /* phy reset gpio */
  449. gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
  450. &priv->rst_gpio, GPIOD_IS_OUT);
  451. priv->phyif = pdata->phy_interface;
  452. priv->phy_addr = phy_addr;
  453. priv->ectl_regs = iobase;
  454. priv->emac_regs = iobase + PIC32_EMAC1CFG1;
  455. pic32_mii_init(priv);
  456. return pic32_phy_init(priv, dev);
  457. }
  458. static int pic32_eth_remove(struct udevice *dev)
  459. {
  460. struct pic32eth_dev *priv = dev_get_priv(dev);
  461. struct mii_dev *bus;
  462. dm_gpio_free(dev, &priv->rst_gpio);
  463. phy_shutdown(priv->phydev);
  464. free(priv->phydev);
  465. bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  466. mdio_unregister(bus);
  467. mdio_free(bus);
  468. iounmap(priv->ectl_regs);
  469. return 0;
  470. }
  471. static const struct udevice_id pic32_eth_ids[] = {
  472. { .compatible = "microchip,pic32mzda-eth" },
  473. { }
  474. };
  475. U_BOOT_DRIVER(pic32_ethernet) = {
  476. .name = "pic32_ethernet",
  477. .id = UCLASS_ETH,
  478. .of_match = pic32_eth_ids,
  479. .probe = pic32_eth_probe,
  480. .remove = pic32_eth_remove,
  481. .ops = &pic32_eth_ops,
  482. .priv_auto = sizeof(struct pic32eth_dev),
  483. .plat_auto = sizeof(struct eth_pdata),
  484. };