rvu.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. */
  5. #ifndef __RVU_H__
  6. #define __RVU_H__
  7. #include <asm/arch/csrs/csrs-rvu.h>
  8. #define ALIGNED __aligned(CONFIG_SYS_CACHELINE_SIZE)
  9. #define Q_SIZE_16 0ULL /* 16 entries */
  10. #define Q_SIZE_64 1ULL /* 64 entries */
  11. #define Q_SIZE_256 2ULL
  12. #define Q_SIZE_1K 3ULL
  13. #define Q_SIZE_4K 4ULL
  14. #define Q_SIZE_16K 5ULL
  15. #define Q_SIZE_64K 6ULL
  16. #define Q_SIZE_256K 7ULL
  17. #define Q_SIZE_1M 8ULL /* Million entries */
  18. #define Q_SIZE_MIN Q_SIZE_16
  19. #define Q_SIZE_MAX Q_SIZE_1M
  20. #define Q_COUNT(x) (16ULL << (2 * (x)))
  21. #define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2)
  22. /* Admin queue info */
  23. /* Since we intend to add only one instruction at a time,
  24. * keep queue size to it's minimum.
  25. */
  26. #define AQ_SIZE Q_SIZE_16
  27. /* HW head & tail pointer mask */
  28. #define AQ_PTR_MASK 0xFFFFF
  29. struct qmem {
  30. void *base;
  31. dma_addr_t iova;
  32. size_t alloc_sz;
  33. u32 qsize;
  34. u8 entry_sz;
  35. };
  36. struct admin_queue {
  37. struct qmem inst;
  38. struct qmem res;
  39. };
  40. struct rvu_af {
  41. struct udevice *dev;
  42. void __iomem *af_base;
  43. struct nix_af *nix_af;
  44. };
  45. struct rvu_pf {
  46. struct udevice *dev;
  47. struct udevice *afdev;
  48. void __iomem *pf_base;
  49. struct nix *nix;
  50. u8 pfid;
  51. int nix_lfid;
  52. int npa_lfid;
  53. };
  54. /**
  55. * Store 128 bit value
  56. *
  57. * @param[out] dest pointer to destination address
  58. * @param val0 first 64 bits to write
  59. * @param val1 second 64 bits to write
  60. */
  61. static inline void st128(void *dest, u64 val0, u64 val1)
  62. {
  63. __asm__ __volatile__("stp %x[x0], %x[x1], [%[pm]]" :
  64. : [x0]"r"(val0), [x1]"r"(val1), [pm]"r"(dest)
  65. : "memory");
  66. }
  67. /**
  68. * Load 128 bit value
  69. *
  70. * @param[in] source pointer to 128 bits of data to load
  71. * @param[out] val0 first 64 bits of data
  72. * @param[out] val1 second 64 bits of data
  73. */
  74. static inline void ld128(const u64 *src, u64 *val0, u64 *val1)
  75. {
  76. __asm__ __volatile__ ("ldp %x[x0], %x[x1], [%[pm]]" :
  77. : [x0]"r"(*val0), [x1]"r"(*val1), [pm]"r"(src));
  78. }
  79. void qmem_free(struct qmem *q);
  80. int qmem_alloc(struct qmem *q, u32 qsize, size_t entry_sz);
  81. /**
  82. * Allocates an admin queue for instructions and results
  83. *
  84. * @param aq admin queue to allocate for
  85. * @param qsize Number of entries in the queue
  86. * @param inst_size Size of each instruction
  87. * @param res_size Size of each result
  88. *
  89. * @return -ENOMEM on error, 0 on success
  90. */
  91. int rvu_aq_alloc(struct admin_queue *aq, unsigned int qsize,
  92. size_t inst_size, size_t res_size);
  93. /**
  94. * Frees an admin queue
  95. *
  96. * @param aq Admin queue to free
  97. */
  98. void rvu_aq_free(struct admin_queue *aq);
  99. void rvu_get_lfid_for_pf(int pf, int *nixid, int *npaid);
  100. #endif /* __RVU_H__ */