cgx_intf.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. */
  5. #include <dm.h>
  6. #include <errno.h>
  7. #include <malloc.h>
  8. #include <misc.h>
  9. #include <net.h>
  10. #include <linux/bitops.h>
  11. #include <linux/delay.h>
  12. #include <linux/list.h>
  13. #include <asm/arch/board.h>
  14. #include <asm/io.h>
  15. #include "cgx_intf.h"
  16. #include "cgx.h"
  17. #include "nix.h"
  18. static u64 cgx_rd_scrx(u8 cgx, u8 lmac, u8 index)
  19. {
  20. u64 addr;
  21. addr = (index == 1) ? CGX_CMR_SCRATCH1 : CGX_CMR_SCRATCH0;
  22. addr += CGX_SHIFT(cgx) + CMR_SHIFT(lmac);
  23. return readq(addr);
  24. }
  25. static void cgx_wr_scrx(u8 cgx, u8 lmac, u8 index, u64 val)
  26. {
  27. u64 addr;
  28. addr = (index == 1) ? CGX_CMR_SCRATCH1 : CGX_CMR_SCRATCH0;
  29. addr += CGX_SHIFT(cgx) + CMR_SHIFT(lmac);
  30. writeq(val, addr);
  31. }
  32. static u64 cgx_rd_scr0(u8 cgx, u8 lmac)
  33. {
  34. return cgx_rd_scrx(cgx, lmac, 0);
  35. }
  36. static u64 cgx_rd_scr1(u8 cgx, u8 lmac)
  37. {
  38. return cgx_rd_scrx(cgx, lmac, 1);
  39. }
  40. static void cgx_wr_scr0(u8 cgx, u8 lmac, u64 val)
  41. {
  42. return cgx_wr_scrx(cgx, lmac, 0, val);
  43. }
  44. static void cgx_wr_scr1(u8 cgx, u8 lmac, u64 val)
  45. {
  46. return cgx_wr_scrx(cgx, lmac, 1, val);
  47. }
  48. static inline void set_ownership(u8 cgx, u8 lmac, u8 val)
  49. {
  50. union cgx_scratchx1 scr1;
  51. scr1.u = cgx_rd_scr1(cgx, lmac);
  52. scr1.s.own_status = val;
  53. cgx_wr_scr1(cgx, lmac, scr1.u);
  54. }
  55. static int wait_for_ownership(u8 cgx, u8 lmac)
  56. {
  57. union cgx_scratchx1 scr1;
  58. union cgx_scratchx0 scr0;
  59. u64 cmrx_int;
  60. int timeout = 5000;
  61. do {
  62. scr1.u = cgx_rd_scr1(cgx, lmac);
  63. scr0.u = cgx_rd_scr0(cgx, lmac);
  64. /* clear async events if any */
  65. if (scr0.s.evt_sts.evt_type == CGX_EVT_ASYNC &&
  66. scr0.s.evt_sts.ack) {
  67. /* clear interrupt */
  68. cmrx_int = readq(CGX_CMR_INT +
  69. CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
  70. cmrx_int |= 0x2; // Overflw bit
  71. writeq(cmrx_int, CGX_CMR_INT +
  72. CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
  73. /* clear ack */
  74. scr0.s.evt_sts.ack = 0;
  75. cgx_wr_scr0(cgx, lmac, scr0.u);
  76. }
  77. if (timeout-- < 0) {
  78. debug("timeout waiting for ownership\n");
  79. return -ETIMEDOUT;
  80. }
  81. mdelay(1);
  82. } while ((scr1.s.own_status == CGX_OWN_FIRMWARE) &&
  83. scr0.s.evt_sts.ack);
  84. return 0;
  85. }
  86. int cgx_intf_req(u8 cgx, u8 lmac, union cgx_cmd_s cmd_args, u64 *rsp,
  87. int use_cmd_id_only)
  88. {
  89. union cgx_scratchx1 scr1;
  90. union cgx_scratchx0 scr0;
  91. u64 cmrx_int;
  92. int timeout = 500;
  93. int err = 0;
  94. u8 cmd = cmd_args.cmd.id;
  95. if (wait_for_ownership(cgx, lmac)) {
  96. err = -ETIMEDOUT;
  97. goto error;
  98. }
  99. /* send command */
  100. scr1.u = cgx_rd_scr1(cgx, lmac);
  101. if (use_cmd_id_only) {
  102. scr1.s.cmd.id = cmd;
  103. } else {
  104. cmd_args.own_status = scr1.s.own_status;
  105. scr1.s = cmd_args;
  106. }
  107. cgx_wr_scr1(cgx, lmac, scr1.u);
  108. set_ownership(cgx, lmac, CGX_OWN_FIRMWARE);
  109. /* wait for response and ownership */
  110. do {
  111. scr0.u = cgx_rd_scr0(cgx, lmac);
  112. scr1.u = cgx_rd_scr1(cgx, lmac);
  113. mdelay(10);
  114. } while (timeout-- && (!scr0.s.evt_sts.ack) &&
  115. (scr1.s.own_status == CGX_OWN_FIRMWARE));
  116. if (timeout < 0) {
  117. debug("%s timeout waiting for ack\n", __func__);
  118. err = -ETIMEDOUT;
  119. goto error;
  120. }
  121. if (cmd == CGX_CMD_INTF_SHUTDOWN)
  122. goto error;
  123. if (scr0.s.evt_sts.evt_type != CGX_EVT_CMD_RESP) {
  124. debug("%s received async event instead of cmd resp event\n",
  125. __func__);
  126. err = -1;
  127. goto error;
  128. }
  129. if (scr0.s.evt_sts.id != cmd) {
  130. debug("%s received resp for cmd %d expected cmd %d\n",
  131. __func__, scr0.s.evt_sts.id, cmd);
  132. err = -1;
  133. goto error;
  134. }
  135. if (scr0.s.evt_sts.stat != CGX_STAT_SUCCESS) {
  136. debug("%s cmd%d failed on cgx%u lmac%u with errcode %d\n",
  137. __func__, cmd, cgx, lmac, scr0.s.link_sts.err_type);
  138. err = -1;
  139. }
  140. error:
  141. /* clear interrupt */
  142. cmrx_int = readq(CGX_CMR_INT + CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
  143. cmrx_int |= 0x2; // Overflw bit
  144. writeq(cmrx_int, CGX_CMR_INT + CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
  145. /* clear ownership and ack */
  146. scr0.s.evt_sts.ack = 0;
  147. cgx_wr_scr0(cgx, lmac, scr0.u);
  148. *rsp = err ? 0 : scr0.u;
  149. return err;
  150. }
  151. int cgx_intf_get_mac_addr(u8 cgx, u8 lmac, u8 *mac)
  152. {
  153. union cgx_scratchx0 scr0;
  154. int ret;
  155. union cgx_cmd_s cmd;
  156. cmd.cmd.id = CGX_CMD_GET_MAC_ADDR;
  157. ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
  158. if (ret)
  159. return -1;
  160. scr0.u >>= 9;
  161. memcpy(mac, &scr0.u, 6);
  162. return 0;
  163. }
  164. int cgx_intf_get_ver(u8 cgx, u8 lmac, u8 *ver)
  165. {
  166. union cgx_scratchx0 scr0;
  167. int ret;
  168. union cgx_cmd_s cmd;
  169. cmd.cmd.id = CGX_CMD_GET_FW_VER;
  170. ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
  171. if (ret)
  172. return -1;
  173. scr0.u >>= 9;
  174. *ver = scr0.u & 0xFFFF;
  175. return 0;
  176. }
  177. int cgx_intf_get_link_sts(u8 cgx, u8 lmac, u64 *lnk_sts)
  178. {
  179. union cgx_scratchx0 scr0;
  180. int ret;
  181. union cgx_cmd_s cmd;
  182. cmd.cmd.id = CGX_CMD_GET_LINK_STS;
  183. ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
  184. if (ret)
  185. return -1;
  186. scr0.u >>= 9;
  187. /* pass the same format as cgx_lnk_sts_s
  188. * err_type:10, speed:4, full_duplex:1, link_up:1
  189. */
  190. *lnk_sts = scr0.u & 0xFFFF;
  191. return 0;
  192. }
  193. int cgx_intf_link_up_dwn(u8 cgx, u8 lmac, u8 up_dwn, u64 *lnk_sts)
  194. {
  195. union cgx_scratchx0 scr0;
  196. int ret;
  197. union cgx_cmd_s cmd;
  198. cmd.cmd.id = up_dwn ? CGX_CMD_LINK_BRING_UP : CGX_CMD_LINK_BRING_DOWN;
  199. ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
  200. if (ret)
  201. return -1;
  202. scr0.u >>= 9;
  203. /* pass the same format as cgx_lnk_sts_s
  204. * err_type:10, speed:4, full_duplex:1, link_up:1
  205. */
  206. *lnk_sts = scr0.u & 0xFFFF;
  207. return 0;
  208. }
  209. void cgx_intf_shutdown(void)
  210. {
  211. union cgx_scratchx0 scr0;
  212. union cgx_cmd_s cmd;
  213. cmd.cmd.id = CGX_CMD_INTF_SHUTDOWN;
  214. cgx_intf_req(0, 0, cmd, &scr0.u, 1);
  215. }
  216. int cgx_intf_prbs(u8 qlm, u8 mode, u32 time, u8 lane)
  217. {
  218. union cgx_scratchx0 scr0;
  219. int ret;
  220. union cgx_cmd_s cmd;
  221. cmd.cmd.id = CGX_CMD_PRBS;
  222. cmd.prbs_args.qlm = qlm;
  223. cmd.prbs_args.mode = mode;
  224. cmd.prbs_args.time = time;
  225. cmd.prbs_args.lane = lane;
  226. ret = cgx_intf_req(0, 0, cmd, &scr0.u, 0);
  227. if (ret)
  228. return -1;
  229. return 0;
  230. }
  231. enum cgx_mode {
  232. MODE_10G_C2C,
  233. MODE_10G_C2M,
  234. MODE_10G_KR,
  235. MODE_25G_C2C,
  236. MODE_25G_2_C2C,
  237. MODE_50G_C2C,
  238. MODE_50G_4_C2C
  239. };
  240. static char intf_speed_to_str[][8] = {
  241. "10M",
  242. "100M",
  243. "1G",
  244. "2.5G",
  245. "5G",
  246. "10G",
  247. "20G",
  248. "25G",
  249. "40G",
  250. "50G",
  251. "80G",
  252. "100G",
  253. };
  254. static void mode_to_args(int mode, struct cgx_mode_change_args *args)
  255. {
  256. args->an = 0;
  257. args->duplex = 0;
  258. args->port = 0;
  259. switch (mode) {
  260. case MODE_10G_C2C:
  261. args->speed = CGX_LINK_10G;
  262. args->mode = BIT_ULL(CGX_MODE_10G_C2C_BIT);
  263. break;
  264. case MODE_10G_C2M:
  265. args->speed = CGX_LINK_10G;
  266. args->mode = BIT_ULL(CGX_MODE_10G_C2M_BIT);
  267. break;
  268. case MODE_10G_KR:
  269. args->speed = CGX_LINK_10G;
  270. args->mode = BIT_ULL(CGX_MODE_10G_KR_BIT);
  271. args->an = 1;
  272. break;
  273. case MODE_25G_C2C:
  274. args->speed = CGX_LINK_25G;
  275. args->mode = BIT_ULL(CGX_MODE_25G_C2C_BIT);
  276. break;
  277. case MODE_25G_2_C2C:
  278. args->speed = CGX_LINK_25G;
  279. args->mode = BIT_ULL(CGX_MODE_25G_2_C2C_BIT);
  280. break;
  281. case MODE_50G_C2C:
  282. args->speed = CGX_LINK_50G;
  283. args->mode = BIT_ULL(CGX_MODE_50G_C2C_BIT);
  284. break;
  285. case MODE_50G_4_C2C:
  286. args->speed = CGX_LINK_50G;
  287. args->mode = BIT_ULL(CGX_MODE_50G_4_C2C_BIT);
  288. }
  289. }
  290. int cgx_intf_set_mode(struct udevice *ethdev, int mode)
  291. {
  292. struct rvu_pf *rvu = dev_get_priv(ethdev);
  293. struct nix *nix = rvu->nix;
  294. union cgx_scratchx0 scr0;
  295. int ret;
  296. union cgx_cmd_s cmd;
  297. cmd.cmd.id = CGX_CMD_MODE_CHANGE;
  298. mode_to_args(mode, &cmd.mode_change_args);
  299. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  300. cmd, &scr0.u, 0);
  301. if (ret) {
  302. printf("Mode change command failed for %s\n", ethdev->name);
  303. return -1;
  304. }
  305. cmd.cmd.id = CGX_CMD_GET_LINK_STS;
  306. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  307. cmd, &scr0.u, 1);
  308. if (ret) {
  309. printf("Get Link Status failed for %s\n", ethdev->name);
  310. return -1;
  311. }
  312. printf("Current Link Status: ");
  313. if (scr0.s.link_sts.speed) {
  314. printf("%s\n", intf_speed_to_str[scr0.s.link_sts.speed]);
  315. switch (scr0.s.link_sts.fec) {
  316. case 0:
  317. printf("FEC_NONE\n");
  318. break;
  319. case 1:
  320. printf("FEC_BASE_R\n");
  321. break;
  322. case 2:
  323. printf("FEC_RS\n");
  324. break;
  325. }
  326. printf("Auto Negotiation %sabled\n",
  327. scr0.s.link_sts.an ? "En" : "Dis");
  328. printf("%s Duplex\n",
  329. scr0.s.link_sts.full_duplex ? "Full" : "Half");
  330. } else {
  331. printf("Down\n");
  332. }
  333. return 0;
  334. }
  335. int cgx_intf_get_mode(struct udevice *ethdev)
  336. {
  337. struct rvu_pf *rvu = dev_get_priv(ethdev);
  338. struct nix *nix = rvu->nix;
  339. union cgx_scratchx0 scr0;
  340. int ret;
  341. union cgx_cmd_s cmd;
  342. cmd.cmd.id = CGX_CMD_GET_LINK_STS;
  343. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  344. cmd, &scr0.u, 1);
  345. if (ret) {
  346. printf("Get link status failed for %s\n", ethdev->name);
  347. return -1;
  348. }
  349. printf("Current Interface Mode: ");
  350. switch (scr0.s.link_sts.mode) {
  351. case CGX_MODE_10G_C2C_BIT:
  352. printf("10G_C2C\n");
  353. break;
  354. case CGX_MODE_10G_C2M_BIT:
  355. printf("10G_C2M\n");
  356. break;
  357. case CGX_MODE_10G_KR_BIT:
  358. printf("10G_KR\n");
  359. break;
  360. case CGX_MODE_25G_C2C_BIT:
  361. printf("25G_C2C\n");
  362. break;
  363. case CGX_MODE_25G_2_C2C_BIT:
  364. printf("25G_2_C2C\n");
  365. break;
  366. case CGX_MODE_50G_C2C_BIT:
  367. printf("50G_C2C\n");
  368. break;
  369. case CGX_MODE_50G_4_C2C_BIT:
  370. printf("50G_4_C2C\n");
  371. break;
  372. default:
  373. printf("Unknown\n");
  374. break;
  375. }
  376. return 0;
  377. }
  378. int cgx_intf_get_fec(struct udevice *ethdev)
  379. {
  380. struct rvu_pf *rvu = dev_get_priv(ethdev);
  381. struct nix *nix = rvu->nix;
  382. union cgx_scratchx0 scr0;
  383. int ret;
  384. union cgx_cmd_s cmd;
  385. cmd.cmd.id = CGX_CMD_GET_SUPPORTED_FEC;
  386. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  387. cmd, &scr0.u, 1);
  388. if (ret) {
  389. printf("Get supported FEC failed for %s\n", ethdev->name);
  390. return -1;
  391. }
  392. printf("Supported FEC type: ");
  393. switch (scr0.s.supported_fec.fec) {
  394. case 0:
  395. printf("FEC_NONE\n");
  396. break;
  397. case 1:
  398. printf("FEC_BASE_R\n");
  399. break;
  400. case 2:
  401. printf("FEC_RS\n");
  402. break;
  403. case 3:
  404. printf("FEC_BASE_R FEC_RS\n");
  405. break;
  406. }
  407. cmd.cmd.id = CGX_CMD_GET_LINK_STS;
  408. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  409. cmd, &scr0.u, 1);
  410. if (ret) {
  411. printf("Get active fec failed for %s\n", ethdev->name);
  412. return -1;
  413. }
  414. printf("Active FEC type: ");
  415. switch (scr0.s.link_sts.fec) {
  416. case 0:
  417. printf("FEC_NONE\n");
  418. break;
  419. case 1:
  420. printf("FEC_BASE_R\n");
  421. break;
  422. case 2:
  423. printf("FEC_RS\n");
  424. break;
  425. }
  426. return 0;
  427. }
  428. int cgx_intf_set_fec(struct udevice *ethdev, int type)
  429. {
  430. struct rvu_pf *rvu = dev_get_priv(ethdev);
  431. struct nix *nix = rvu->nix;
  432. union cgx_scratchx0 scr0;
  433. int ret;
  434. union cgx_cmd_s cmd;
  435. cmd.cmd.id = CGX_CMD_SET_FEC;
  436. cmd.fec_args.fec = type;
  437. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  438. cmd, &scr0.u, 0);
  439. if (ret) {
  440. printf("Set FEC type %d failed for %s\n", type, ethdev->name);
  441. return -1;
  442. }
  443. return 0;
  444. }
  445. int cgx_intf_get_phy_mod_type(struct udevice *ethdev)
  446. {
  447. struct rvu_pf *rvu = dev_get_priv(ethdev);
  448. struct nix *nix = rvu->nix;
  449. union cgx_scratchx0 scr0;
  450. int ret;
  451. union cgx_cmd_s cmd;
  452. cmd.cmd.id = CGX_CMD_GET_PHY_MOD_TYPE;
  453. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  454. cmd, &scr0.u, 1);
  455. if (ret) {
  456. printf("Get PHYMOD type failed for %s\n", ethdev->name);
  457. return -1;
  458. }
  459. printf("Current phy mod type %s\n",
  460. scr0.s.phy_mod_type.mod ? "PAM4" : "NRZ");
  461. return 0;
  462. }
  463. int cgx_intf_set_phy_mod_type(struct udevice *ethdev, int type)
  464. {
  465. struct rvu_pf *rvu = dev_get_priv(ethdev);
  466. struct nix *nix = rvu->nix;
  467. union cgx_scratchx0 scr0;
  468. int ret;
  469. union cgx_cmd_s cmd;
  470. cmd.cmd.id = CGX_CMD_SET_PHY_MOD_TYPE;
  471. cmd.phy_mod_args.mod = type;
  472. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  473. cmd, &scr0.u, 0);
  474. if (ret) {
  475. printf("Set PHYMOD type %d failed for %s\n", type,
  476. ethdev->name);
  477. return -1;
  478. }
  479. return 0;
  480. }
  481. int cgx_intf_set_an_lbk(struct udevice *ethdev, int enable)
  482. {
  483. struct rvu_pf *rvu = dev_get_priv(ethdev);
  484. struct nix *nix = rvu->nix;
  485. union cgx_scratchx0 scr0;
  486. int ret;
  487. union cgx_cmd_s cmd;
  488. cmd.cmd.id = CGX_CMD_AN_LOOPBACK;
  489. cmd.cmd_args.enable = enable;
  490. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  491. cmd, &scr0.u, 0);
  492. if (ret) {
  493. printf("Set AN loopback command failed on %s\n", ethdev->name);
  494. return -1;
  495. }
  496. printf("AN loopback %s for %s\n", enable ? "set" : "clear",
  497. ethdev->name);
  498. return 0;
  499. }
  500. int cgx_intf_get_ignore(struct udevice *ethdev, int cgx, int lmac)
  501. {
  502. struct rvu_pf *rvu;
  503. struct nix *nix;
  504. union cgx_scratchx0 scr0;
  505. int ret, cgx_id = cgx, lmac_id = lmac;
  506. union cgx_cmd_s cmd;
  507. if (ethdev) {
  508. rvu = dev_get_priv(ethdev);
  509. nix = rvu->nix;
  510. cgx_id = nix->lmac->cgx->cgx_id;
  511. lmac_id = nix->lmac->lmac_id;
  512. }
  513. cmd.cmd.id = CGX_CMD_GET_PERSIST_IGNORE;
  514. ret = cgx_intf_req(cgx_id, lmac_id, cmd, &scr0.u, 1);
  515. if (ret) {
  516. if (ethdev)
  517. printf("Get ignore command failed for %s\n",
  518. ethdev->name);
  519. else
  520. printf("Get ignore command failed for CGX%d LMAC%d\n",
  521. cgx_id, lmac_id);
  522. return -1;
  523. }
  524. if (ethdev)
  525. printf("Persist settings %signored for %s\n",
  526. scr0.s.persist.ignore ? "" : "not ", ethdev->name);
  527. else
  528. printf("Persist settings %signored for CGX%d LMAC%d\n",
  529. scr0.s.persist.ignore ? "" : "not ", cgx_id, lmac_id);
  530. return 0;
  531. }
  532. int cgx_intf_set_ignore(struct udevice *ethdev, int cgx, int lmac, int ignore)
  533. {
  534. struct rvu_pf *rvu;
  535. struct nix *nix;
  536. union cgx_scratchx0 scr0;
  537. int ret, cgx_id = cgx, lmac_id = lmac;
  538. union cgx_cmd_s cmd;
  539. if (ethdev) {
  540. rvu = dev_get_priv(ethdev);
  541. nix = rvu->nix;
  542. cgx_id = nix->lmac->cgx->cgx_id;
  543. lmac_id = nix->lmac->lmac_id;
  544. }
  545. cmd.cmd.id = CGX_CMD_SET_PERSIST_IGNORE;
  546. cmd.persist_args.ignore = ignore;
  547. ret = cgx_intf_req(cgx_id, lmac_id, cmd, &scr0.u, 0);
  548. if (ret) {
  549. if (ethdev)
  550. printf("Set ignore command failed for %s\n",
  551. ethdev->name);
  552. else
  553. printf("Set ignore command failed for CGX%d LMAC%d\n",
  554. cgx_id, lmac_id);
  555. return -1;
  556. }
  557. return 0;
  558. }
  559. int cgx_intf_set_macaddr(struct udevice *ethdev)
  560. {
  561. struct rvu_pf *rvu = dev_get_priv(ethdev);
  562. struct nix *nix = rvu->nix;
  563. union cgx_scratchx0 scr0;
  564. int ret;
  565. union cgx_cmd_s cmd;
  566. u64 mac, tmp;
  567. memcpy((void *)&tmp, nix->lmac->mac_addr, 6);
  568. mac = swab64(tmp) >> 16;
  569. cmd.cmd.id = CGX_CMD_SET_MAC_ADDR;
  570. cmd.mac_args.addr = mac;
  571. cmd.mac_args.pf_id = rvu->pfid;
  572. ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
  573. cmd, &scr0.u, 0);
  574. if (ret) {
  575. printf("Set user mac addr failed for %s\n", ethdev->name);
  576. return -1;
  577. }
  578. return 0;
  579. }
  580. int cgx_intf_display_eye(u8 qlm, u8 lane)
  581. {
  582. union cgx_scratchx0 scr0;
  583. int ret;
  584. union cgx_cmd_s cmd;
  585. cmd.cmd.id = CGX_CMD_DISPLAY_EYE;
  586. cmd.dsp_eye_args.qlm = qlm;
  587. cmd.dsp_eye_args.lane = lane;
  588. ret = cgx_intf_req(0, 0, cmd, &scr0.u, 0);
  589. if (ret)
  590. return -1;
  591. return 0;
  592. }
  593. int cgx_intf_display_serdes(u8 qlm, u8 lane)
  594. {
  595. union cgx_scratchx0 scr0;
  596. int ret;
  597. union cgx_cmd_s cmd;
  598. cmd.cmd.id = CGX_CMD_DISPLAY_SERDES;
  599. cmd.dsp_eye_args.qlm = qlm;
  600. cmd.dsp_eye_args.lane = lane;
  601. ret = cgx_intf_req(0, 0, cmd, &scr0.u, 0);
  602. if (ret)
  603. return -1;
  604. return 0;
  605. }