mvpp2.c 153 KB

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  1. /*
  2. * Driver for Marvell PPv2 network controller for Armada 375 SoC.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Marcin Wojtas <mw@semihalf.com>
  7. *
  8. * U-Boot version:
  9. * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <dm.h>
  18. #include <asm/cache.h>
  19. #include <asm/global_data.h>
  20. #include <dm/device-internal.h>
  21. #include <dm/device_compat.h>
  22. #include <dm/devres.h>
  23. #include <dm/lists.h>
  24. #include <net.h>
  25. #include <netdev.h>
  26. #include <config.h>
  27. #include <malloc.h>
  28. #include <asm/io.h>
  29. #include <linux/bitops.h>
  30. #include <linux/bug.h>
  31. #include <linux/delay.h>
  32. #include <linux/err.h>
  33. #include <linux/errno.h>
  34. #include <phy.h>
  35. #include <miiphy.h>
  36. #include <watchdog.h>
  37. #include <asm/arch/cpu.h>
  38. #include <asm/arch/soc.h>
  39. #include <linux/compat.h>
  40. #include <linux/libfdt.h>
  41. #include <linux/mbus.h>
  42. #include <asm-generic/gpio.h>
  43. #include <fdt_support.h>
  44. #include <linux/mdio.h>
  45. DECLARE_GLOBAL_DATA_PTR;
  46. #define __verify_pcpu_ptr(ptr) \
  47. do { \
  48. const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  49. (void)__vpp_verify; \
  50. } while (0)
  51. #define VERIFY_PERCPU_PTR(__p) \
  52. ({ \
  53. __verify_pcpu_ptr(__p); \
  54. (typeof(*(__p)) __kernel __force *)(__p); \
  55. })
  56. #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
  57. #define smp_processor_id() 0
  58. #define num_present_cpus() 1
  59. #define for_each_present_cpu(cpu) \
  60. for ((cpu) = 0; (cpu) < 1; (cpu)++)
  61. #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
  62. #define CONFIG_NR_CPUS 1
  63. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  64. #define WRAP (2 + ETH_HLEN + 4 + 32)
  65. #define MTU 1500
  66. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  67. /* RX Fifo Registers */
  68. #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
  69. #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
  70. #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
  71. #define MVPP2_RX_FIFO_INIT_REG 0x64
  72. /* RX DMA Top Registers */
  73. #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
  74. #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
  75. #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
  76. #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
  77. #define MVPP2_POOL_BUF_SIZE_OFFSET 5
  78. #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
  79. #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
  80. #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
  81. #define MVPP2_RXQ_POOL_SHORT_OFFS 20
  82. #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
  83. #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
  84. #define MVPP2_RXQ_POOL_LONG_OFFS 24
  85. #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
  86. #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
  87. #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
  88. #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
  89. #define MVPP2_RXQ_DISABLE_MASK BIT(31)
  90. /* Parser Registers */
  91. #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
  92. #define MVPP2_PRS_PORT_LU_MAX 0xf
  93. #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
  94. #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
  95. #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
  96. #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
  97. #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
  98. #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
  99. #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
  100. #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
  101. #define MVPP2_PRS_TCAM_IDX_REG 0x1100
  102. #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
  103. #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
  104. #define MVPP2_PRS_SRAM_IDX_REG 0x1200
  105. #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
  106. #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
  107. #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
  108. /* Classifier Registers */
  109. #define MVPP2_CLS_MODE_REG 0x1800
  110. #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
  111. #define MVPP2_CLS_PORT_WAY_REG 0x1810
  112. #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
  113. #define MVPP2_CLS_LKP_INDEX_REG 0x1814
  114. #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
  115. #define MVPP2_CLS_LKP_TBL_REG 0x1818
  116. #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
  117. #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
  118. #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
  119. #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
  120. #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
  121. #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
  122. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
  123. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
  124. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
  125. #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
  126. #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
  127. #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
  128. /* Descriptor Manager Top Registers */
  129. #define MVPP2_RXQ_NUM_REG 0x2040
  130. #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
  131. #define MVPP22_DESC_ADDR_OFFS 8
  132. #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
  133. #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
  134. #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
  135. #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
  136. #define MVPP2_RXQ_NUM_NEW_OFFSET 16
  137. #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
  138. #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
  139. #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
  140. #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
  141. #define MVPP2_RXQ_THRESH_REG 0x204c
  142. #define MVPP2_OCCUPIED_THRESH_OFFSET 0
  143. #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
  144. #define MVPP2_RXQ_INDEX_REG 0x2050
  145. #define MVPP2_TXQ_NUM_REG 0x2080
  146. #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
  147. #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
  148. #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
  149. #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
  150. #define MVPP2_TXQ_THRESH_REG 0x2094
  151. #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
  152. #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
  153. #define MVPP2_TXQ_INDEX_REG 0x2098
  154. #define MVPP2_TXQ_PREF_BUF_REG 0x209c
  155. #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
  156. #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
  157. #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
  158. #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
  159. #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
  160. #define MVPP2_TXQ_PENDING_REG 0x20a0
  161. #define MVPP2_TXQ_PENDING_MASK 0x3fff
  162. #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
  163. #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
  164. #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
  165. #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
  166. #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
  167. #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
  168. #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
  169. #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
  170. #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
  171. #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
  172. #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
  173. #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
  174. #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
  175. #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
  176. #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
  177. #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
  178. #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
  179. /* MBUS bridge registers */
  180. #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
  181. #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
  182. #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
  183. #define MVPP2_BASE_ADDR_ENABLE 0x4060
  184. /* AXI Bridge Registers */
  185. #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
  186. #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
  187. #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
  188. #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
  189. #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
  190. #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
  191. #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
  192. #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
  193. #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
  194. #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
  195. #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
  196. #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
  197. /* Values for AXI Bridge registers */
  198. #define MVPP22_AXI_ATTR_CACHE_OFFS 0
  199. #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
  200. #define MVPP22_AXI_CODE_CACHE_OFFS 0
  201. #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
  202. #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
  203. #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
  204. #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
  205. #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
  206. #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
  207. /* Interrupt Cause and Mask registers */
  208. #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
  209. #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
  210. #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
  211. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  212. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  213. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
  214. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  215. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  216. #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
  217. #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
  218. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
  219. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
  220. #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
  221. #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
  222. #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
  223. #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
  224. #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  225. #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
  226. #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
  227. #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
  228. #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
  229. #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
  230. #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
  231. #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
  232. #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
  233. #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
  234. #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  235. #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
  236. #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
  237. #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
  238. /* Buffer Manager registers */
  239. #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
  240. #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
  241. #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
  242. #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
  243. #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
  244. #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
  245. #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
  246. #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
  247. #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
  248. #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
  249. #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
  250. #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
  251. #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
  252. #define MVPP2_BM_START_MASK BIT(0)
  253. #define MVPP2_BM_STOP_MASK BIT(1)
  254. #define MVPP2_BM_STATE_MASK BIT(4)
  255. #define MVPP2_BM_LOW_THRESH_OFFS 8
  256. #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
  257. #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
  258. MVPP2_BM_LOW_THRESH_OFFS)
  259. #define MVPP2_BM_HIGH_THRESH_OFFS 16
  260. #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
  261. #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
  262. MVPP2_BM_HIGH_THRESH_OFFS)
  263. #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
  264. #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
  265. #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
  266. #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
  267. #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
  268. #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
  269. #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
  270. #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
  271. #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
  272. #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
  273. #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
  274. #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
  275. #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
  276. #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
  277. #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
  278. #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
  279. #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
  280. #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
  281. #define MVPP2_BM_VIRT_RLS_REG 0x64c0
  282. #define MVPP21_BM_MC_RLS_REG 0x64c4
  283. #define MVPP2_BM_MC_ID_MASK 0xfff
  284. #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
  285. #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
  286. #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
  287. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
  288. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
  289. #define MVPP22_BM_MC_RLS_REG 0x64d4
  290. #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
  291. #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
  292. /* TX Scheduler registers */
  293. #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
  294. #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
  295. #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
  296. #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
  297. #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
  298. #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
  299. #define MVPP2_TXP_SCHED_MTU_REG 0x801c
  300. #define MVPP2_TXP_MTU_MAX 0x7FFFF
  301. #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
  302. #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
  303. #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
  304. #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
  305. #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
  306. #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
  307. #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
  308. #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
  309. #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
  310. #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
  311. #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
  312. #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  313. #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
  314. #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
  315. /* TX general registers */
  316. #define MVPP2_TX_SNOOP_REG 0x8800
  317. #define MVPP2_TX_PORT_FLUSH_REG 0x8810
  318. #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
  319. /* LMS registers */
  320. #define MVPP2_SRC_ADDR_MIDDLE 0x24
  321. #define MVPP2_SRC_ADDR_HIGH 0x28
  322. #define MVPP2_PHY_AN_CFG0_REG 0x34
  323. #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
  324. #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
  325. #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
  326. /* Per-port registers */
  327. #define MVPP2_GMAC_CTRL_0_REG 0x0
  328. #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
  329. #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
  330. #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
  331. #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  332. #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
  333. #define MVPP2_GMAC_CTRL_1_REG 0x4
  334. #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
  335. #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
  336. #define MVPP2_GMAC_PCS_LB_EN_BIT 6
  337. #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
  338. #define MVPP2_GMAC_SA_LOW_OFFS 7
  339. #define MVPP2_GMAC_CTRL_2_REG 0x8
  340. #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
  341. #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
  342. #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
  343. #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
  344. #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
  345. #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
  346. #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
  347. #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
  348. #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
  349. #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
  350. #define MVPP2_GMAC_EN_PCS_AN BIT(2)
  351. #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
  352. #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
  353. #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
  354. #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
  355. #define MVPP2_GMAC_FC_ADV_EN BIT(9)
  356. #define MVPP2_GMAC_EN_FC_AN BIT(11)
  357. #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  358. #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
  359. #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
  360. #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
  361. #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
  362. #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
  363. #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
  364. MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
  365. #define MVPP2_GMAC_CTRL_4_REG 0x90
  366. #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
  367. #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
  368. #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
  369. #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
  370. /*
  371. * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
  372. * relative to port->base.
  373. */
  374. /* Port Mac Control0 */
  375. #define MVPP22_XLG_CTRL0_REG 0x100
  376. #define MVPP22_XLG_PORT_EN BIT(0)
  377. #define MVPP22_XLG_MAC_RESETN BIT(1)
  378. #define MVPP22_XLG_RX_FC_EN BIT(7)
  379. #define MVPP22_XLG_MIBCNT_DIS BIT(13)
  380. /* Port Mac Control1 */
  381. #define MVPP22_XLG_CTRL1_REG 0x104
  382. #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
  383. #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
  384. /* Port Interrupt Mask */
  385. #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
  386. #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
  387. /* Port Mac Control3 */
  388. #define MVPP22_XLG_CTRL3_REG 0x11c
  389. #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
  390. #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
  391. #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
  392. /* Port Mac Control4 */
  393. #define MVPP22_XLG_CTRL4_REG 0x184
  394. #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
  395. #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
  396. #define MVPP22_XLG_MODE_DMA_1G BIT(12)
  397. #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
  398. /* XPCS registers */
  399. /* Global Configuration 0 */
  400. #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
  401. #define MVPP22_XPCS_PCSRESET BIT(0)
  402. #define MVPP22_XPCS_PCSMODE_OFFS 3
  403. #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
  404. MVPP22_XPCS_PCSMODE_OFFS)
  405. #define MVPP22_XPCS_LANEACTIVE_OFFS 5
  406. #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
  407. MVPP22_XPCS_LANEACTIVE_OFFS)
  408. /* MPCS registers */
  409. #define PCS40G_COMMON_CONTROL 0x14
  410. #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
  411. #define PCS_CLOCK_RESET 0x14c
  412. #define TX_SD_CLK_RESET_MASK BIT(0)
  413. #define RX_SD_CLK_RESET_MASK BIT(1)
  414. #define MAC_CLK_RESET_MASK BIT(2)
  415. #define CLK_DIVISION_RATIO_OFFS 4
  416. #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
  417. #define CLK_DIV_PHASE_SET_MASK BIT(11)
  418. /* System Soft Reset 1 */
  419. #define GOP_SOFT_RESET_1_REG 0x108
  420. #define NETC_GOP_SOFT_RESET_OFFS 6
  421. #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
  422. NETC_GOP_SOFT_RESET_OFFS)
  423. /* Ports Control 0 */
  424. #define NETCOMP_PORTS_CONTROL_0_REG 0x110
  425. #define NETC_BUS_WIDTH_SELECT_OFFS 1
  426. #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
  427. NETC_BUS_WIDTH_SELECT_OFFS)
  428. #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
  429. #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
  430. NETC_GIG_RX_DATA_SAMPLE_OFFS)
  431. #define NETC_CLK_DIV_PHASE_OFFS 31
  432. #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
  433. /* Ports Control 1 */
  434. #define NETCOMP_PORTS_CONTROL_1_REG 0x114
  435. #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
  436. #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
  437. NETC_PORTS_ACTIVE_OFFSET(p))
  438. #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
  439. #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
  440. NETC_PORT_GIG_RF_RESET_OFFS(p))
  441. #define NETCOMP_CONTROL_0_REG 0x120
  442. #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
  443. #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
  444. NETC_GBE_PORT0_SGMII_MODE_OFFS)
  445. #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
  446. #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
  447. NETC_GBE_PORT1_SGMII_MODE_OFFS)
  448. #define NETC_GBE_PORT1_MII_MODE_OFFS 2
  449. #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
  450. NETC_GBE_PORT1_MII_MODE_OFFS)
  451. #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
  452. #define MVPP22_SMI_POLLING_EN BIT(10)
  453. #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
  454. /* Descriptor ring Macros */
  455. #define MVPP2_QUEUE_NEXT_DESC(q, index) \
  456. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  457. /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
  458. #define MVPP22_SMI 0x1200
  459. /* Additional PPv2.2 offsets */
  460. #define MVPP22_MPCS 0x007000
  461. #define MVPP22_XPCS 0x007400
  462. #define MVPP22_PORT_BASE 0x007e00
  463. #define MVPP22_PORT_OFFSET 0x001000
  464. #define MVPP22_RFU1 0x318000
  465. /* Maximum number of ports */
  466. #define MVPP22_GOP_MAC_NUM 4
  467. /* Sets the field located at the specified in data */
  468. #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
  469. #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
  470. #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
  471. /* Net Complex */
  472. enum mv_netc_topology {
  473. MV_NETC_GE_MAC2_SGMII = BIT(0),
  474. MV_NETC_GE_MAC2_RGMII = BIT(1),
  475. MV_NETC_GE_MAC3_SGMII = BIT(2),
  476. MV_NETC_GE_MAC3_RGMII = BIT(3),
  477. };
  478. enum mv_netc_phase {
  479. MV_NETC_FIRST_PHASE,
  480. MV_NETC_SECOND_PHASE,
  481. };
  482. enum mv_netc_sgmii_xmi_mode {
  483. MV_NETC_GBE_SGMII,
  484. MV_NETC_GBE_XMII,
  485. };
  486. enum mv_netc_mii_mode {
  487. MV_NETC_GBE_RGMII,
  488. MV_NETC_GBE_MII,
  489. };
  490. enum mv_netc_lanes {
  491. MV_NETC_LANE_23,
  492. MV_NETC_LANE_45,
  493. };
  494. /* Various constants */
  495. /* Coalescing */
  496. #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
  497. #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
  498. #define MVPP2_RX_COAL_PKTS 32
  499. #define MVPP2_RX_COAL_USEC 100
  500. /* The two bytes Marvell header. Either contains a special value used
  501. * by Marvell switches when a specific hardware mode is enabled (not
  502. * supported by this driver) or is filled automatically by zeroes on
  503. * the RX side. Those two bytes being at the front of the Ethernet
  504. * header, they allow to have the IP header aligned on a 4 bytes
  505. * boundary automatically: the hardware skips those two bytes on its
  506. * own.
  507. */
  508. #define MVPP2_MH_SIZE 2
  509. #define MVPP2_ETH_TYPE_LEN 2
  510. #define MVPP2_PPPOE_HDR_SIZE 8
  511. #define MVPP2_VLAN_TAG_LEN 4
  512. /* Lbtd 802.3 type */
  513. #define MVPP2_IP_LBDT_TYPE 0xfffa
  514. #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
  515. #define MVPP2_TX_CSUM_MAX_SIZE 9800
  516. /* Timeout constants */
  517. #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
  518. #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
  519. #define MVPP2_TX_MTU_MAX 0x7ffff
  520. /* Maximum number of T-CONTs of PON port */
  521. #define MVPP2_MAX_TCONT 16
  522. /* Maximum number of supported ports */
  523. #define MVPP2_MAX_PORTS 4
  524. /* Maximum number of TXQs used by single port */
  525. #define MVPP2_MAX_TXQ 8
  526. /* Default number of TXQs in use */
  527. #define MVPP2_DEFAULT_TXQ 1
  528. /* Default number of RXQs in use */
  529. #define MVPP2_DEFAULT_RXQ 1
  530. #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
  531. /* Max number of Rx descriptors */
  532. #define MVPP2_MAX_RXD 16
  533. /* Max number of Tx descriptors */
  534. #define MVPP2_MAX_TXD 16
  535. /* Amount of Tx descriptors that can be reserved at once by CPU */
  536. #define MVPP2_CPU_DESC_CHUNK 16
  537. /* Max number of Tx descriptors in each aggregated queue */
  538. #define MVPP2_AGGR_TXQ_SIZE 16
  539. /* Descriptor aligned size */
  540. #define MVPP2_DESC_ALIGNED_SIZE 32
  541. /* Descriptor alignment mask */
  542. #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
  543. /* RX FIFO constants */
  544. #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
  545. #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
  546. #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
  547. #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
  548. #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
  549. #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
  550. #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
  551. #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
  552. #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
  553. /* TX general registers */
  554. #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
  555. #define MVPP22_TX_FIFO_SIZE_MASK 0xf
  556. /* TX FIFO constants */
  557. #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
  558. #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
  559. /* RX buffer constants */
  560. #define MVPP2_SKB_SHINFO_SIZE \
  561. 0
  562. #define MVPP2_RX_PKT_SIZE(mtu) \
  563. ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
  564. ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
  565. #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
  566. #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
  567. #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
  568. ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
  569. #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
  570. /* IPv6 max L3 address size */
  571. #define MVPP2_MAX_L3_ADDR_SIZE 16
  572. /* Port flags */
  573. #define MVPP2_F_LOOPBACK BIT(0)
  574. /* Marvell tag types */
  575. enum mvpp2_tag_type {
  576. MVPP2_TAG_TYPE_NONE = 0,
  577. MVPP2_TAG_TYPE_MH = 1,
  578. MVPP2_TAG_TYPE_DSA = 2,
  579. MVPP2_TAG_TYPE_EDSA = 3,
  580. MVPP2_TAG_TYPE_VLAN = 4,
  581. MVPP2_TAG_TYPE_LAST = 5
  582. };
  583. /* Parser constants */
  584. #define MVPP2_PRS_TCAM_SRAM_SIZE 256
  585. #define MVPP2_PRS_TCAM_WORDS 6
  586. #define MVPP2_PRS_SRAM_WORDS 4
  587. #define MVPP2_PRS_FLOW_ID_SIZE 64
  588. #define MVPP2_PRS_FLOW_ID_MASK 0x3f
  589. #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
  590. #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
  591. #define MVPP2_PRS_IPV4_HEAD 0x40
  592. #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
  593. #define MVPP2_PRS_IPV4_MC 0xe0
  594. #define MVPP2_PRS_IPV4_MC_MASK 0xf0
  595. #define MVPP2_PRS_IPV4_BC_MASK 0xff
  596. #define MVPP2_PRS_IPV4_IHL 0x5
  597. #define MVPP2_PRS_IPV4_IHL_MASK 0xf
  598. #define MVPP2_PRS_IPV6_MC 0xff
  599. #define MVPP2_PRS_IPV6_MC_MASK 0xff
  600. #define MVPP2_PRS_IPV6_HOP_MASK 0xff
  601. #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
  602. #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
  603. #define MVPP2_PRS_DBL_VLANS_MAX 100
  604. /* Tcam structure:
  605. * - lookup ID - 4 bits
  606. * - port ID - 1 byte
  607. * - additional information - 1 byte
  608. * - header data - 8 bytes
  609. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
  610. */
  611. #define MVPP2_PRS_AI_BITS 8
  612. #define MVPP2_PRS_PORT_MASK 0xff
  613. #define MVPP2_PRS_LU_MASK 0xf
  614. #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
  615. (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
  616. #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
  617. (((offs) * 2) - ((offs) % 2) + 2)
  618. #define MVPP2_PRS_TCAM_AI_BYTE 16
  619. #define MVPP2_PRS_TCAM_PORT_BYTE 17
  620. #define MVPP2_PRS_TCAM_LU_BYTE 20
  621. #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
  622. #define MVPP2_PRS_TCAM_INV_WORD 5
  623. /* Tcam entries ID */
  624. #define MVPP2_PE_DROP_ALL 0
  625. #define MVPP2_PE_FIRST_FREE_TID 1
  626. #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
  627. #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
  628. #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
  629. #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
  630. #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
  631. #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
  632. #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
  633. #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
  634. #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
  635. #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
  636. #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
  637. #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
  638. #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
  639. #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
  640. #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
  641. #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
  642. #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
  643. #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
  644. #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
  645. #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
  646. #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
  647. #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
  648. #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
  649. #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
  650. #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  651. /* Sram structure
  652. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
  653. */
  654. #define MVPP2_PRS_SRAM_RI_OFFS 0
  655. #define MVPP2_PRS_SRAM_RI_WORD 0
  656. #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
  657. #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
  658. #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
  659. #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
  660. #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
  661. #define MVPP2_PRS_SRAM_UDF_OFFS 73
  662. #define MVPP2_PRS_SRAM_UDF_BITS 8
  663. #define MVPP2_PRS_SRAM_UDF_MASK 0xff
  664. #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
  665. #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
  666. #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
  667. #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
  668. #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
  669. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
  670. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
  671. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
  672. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
  673. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
  674. #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
  675. #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
  676. #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
  677. #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
  678. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
  679. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
  680. #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
  681. #define MVPP2_PRS_SRAM_AI_OFFS 90
  682. #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
  683. #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
  684. #define MVPP2_PRS_SRAM_AI_MASK 0xff
  685. #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
  686. #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
  687. #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
  688. #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
  689. /* Sram result info bits assignment */
  690. #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
  691. #define MVPP2_PRS_RI_DSA_MASK 0x2
  692. #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
  693. #define MVPP2_PRS_RI_VLAN_NONE 0x0
  694. #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
  695. #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
  696. #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
  697. #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
  698. #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
  699. #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
  700. #define MVPP2_PRS_RI_L2_UCAST 0x0
  701. #define MVPP2_PRS_RI_L2_MCAST BIT(9)
  702. #define MVPP2_PRS_RI_L2_BCAST BIT(10)
  703. #define MVPP2_PRS_RI_PPPOE_MASK 0x800
  704. #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
  705. #define MVPP2_PRS_RI_L3_UN 0x0
  706. #define MVPP2_PRS_RI_L3_IP4 BIT(12)
  707. #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
  708. #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
  709. #define MVPP2_PRS_RI_L3_IP6 BIT(14)
  710. #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
  711. #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
  712. #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
  713. #define MVPP2_PRS_RI_L3_UCAST 0x0
  714. #define MVPP2_PRS_RI_L3_MCAST BIT(15)
  715. #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
  716. #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
  717. #define MVPP2_PRS_RI_UDF3_MASK 0x300000
  718. #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
  719. #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
  720. #define MVPP2_PRS_RI_L4_TCP BIT(22)
  721. #define MVPP2_PRS_RI_L4_UDP BIT(23)
  722. #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
  723. #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
  724. #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
  725. #define MVPP2_PRS_RI_DROP_MASK 0x80000000
  726. /* Sram additional info bits assignment */
  727. #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
  728. #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
  729. #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
  730. #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
  731. #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
  732. #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
  733. #define MVPP2_PRS_SINGLE_VLAN_AI 0
  734. #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
  735. /* DSA/EDSA type */
  736. #define MVPP2_PRS_TAGGED true
  737. #define MVPP2_PRS_UNTAGGED false
  738. #define MVPP2_PRS_EDSA true
  739. #define MVPP2_PRS_DSA false
  740. /* MAC entries, shadow udf */
  741. enum mvpp2_prs_udf {
  742. MVPP2_PRS_UDF_MAC_DEF,
  743. MVPP2_PRS_UDF_MAC_RANGE,
  744. MVPP2_PRS_UDF_L2_DEF,
  745. MVPP2_PRS_UDF_L2_DEF_COPY,
  746. MVPP2_PRS_UDF_L2_USER,
  747. };
  748. /* Lookup ID */
  749. enum mvpp2_prs_lookup {
  750. MVPP2_PRS_LU_MH,
  751. MVPP2_PRS_LU_MAC,
  752. MVPP2_PRS_LU_DSA,
  753. MVPP2_PRS_LU_VLAN,
  754. MVPP2_PRS_LU_L2,
  755. MVPP2_PRS_LU_PPPOE,
  756. MVPP2_PRS_LU_IP4,
  757. MVPP2_PRS_LU_IP6,
  758. MVPP2_PRS_LU_FLOWS,
  759. MVPP2_PRS_LU_LAST,
  760. };
  761. /* L3 cast enum */
  762. enum mvpp2_prs_l3_cast {
  763. MVPP2_PRS_L3_UNI_CAST,
  764. MVPP2_PRS_L3_MULTI_CAST,
  765. MVPP2_PRS_L3_BROAD_CAST
  766. };
  767. /* Classifier constants */
  768. #define MVPP2_CLS_FLOWS_TBL_SIZE 512
  769. #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
  770. #define MVPP2_CLS_LKP_TBL_SIZE 64
  771. /* BM constants */
  772. #define MVPP2_BM_POOLS_NUM 1
  773. #define MVPP2_BM_LONG_BUF_NUM 16
  774. #define MVPP2_BM_SHORT_BUF_NUM 16
  775. #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
  776. #define MVPP2_BM_POOL_PTR_ALIGN 128
  777. #define MVPP2_BM_SWF_LONG_POOL(port) 0
  778. /* BM cookie (32 bits) definition */
  779. #define MVPP2_BM_COOKIE_POOL_OFFS 8
  780. #define MVPP2_BM_COOKIE_CPU_OFFS 24
  781. /* BM short pool packet size
  782. * These value assure that for SWF the total number
  783. * of bytes allocated for each buffer will be 512
  784. */
  785. #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
  786. enum mvpp2_bm_type {
  787. MVPP2_BM_FREE,
  788. MVPP2_BM_SWF_LONG,
  789. MVPP2_BM_SWF_SHORT
  790. };
  791. /* Definitions */
  792. /* Shared Packet Processor resources */
  793. struct mvpp2 {
  794. /* Shared registers' base addresses */
  795. void __iomem *base;
  796. void __iomem *lms_base;
  797. void __iomem *iface_base;
  798. void __iomem *mpcs_base;
  799. void __iomem *xpcs_base;
  800. void __iomem *rfu1_base;
  801. u32 netc_config;
  802. /* List of pointers to port structures */
  803. struct mvpp2_port **port_list;
  804. /* Aggregated TXQs */
  805. struct mvpp2_tx_queue *aggr_txqs;
  806. /* BM pools */
  807. struct mvpp2_bm_pool *bm_pools;
  808. /* PRS shadow table */
  809. struct mvpp2_prs_shadow *prs_shadow;
  810. /* PRS auxiliary table for double vlan entries control */
  811. bool *prs_double_vlans;
  812. /* Tclk value */
  813. u32 tclk;
  814. /* HW version */
  815. enum { MVPP21, MVPP22 } hw_version;
  816. /* Maximum number of RXQs per port */
  817. unsigned int max_port_rxqs;
  818. int probe_done;
  819. u8 num_ports;
  820. };
  821. struct mvpp2_pcpu_stats {
  822. u64 rx_packets;
  823. u64 rx_bytes;
  824. u64 tx_packets;
  825. u64 tx_bytes;
  826. };
  827. struct mvpp2_port {
  828. u8 id;
  829. /* Index of the port from the "group of ports" complex point
  830. * of view
  831. */
  832. int gop_id;
  833. int irq;
  834. struct mvpp2 *priv;
  835. /* Per-port registers' base address */
  836. void __iomem *base;
  837. struct mvpp2_rx_queue **rxqs;
  838. struct mvpp2_tx_queue **txqs;
  839. int pkt_size;
  840. u32 pending_cause_rx;
  841. /* Per-CPU port control */
  842. struct mvpp2_port_pcpu __percpu *pcpu;
  843. /* Flags */
  844. unsigned long flags;
  845. u16 tx_ring_size;
  846. u16 rx_ring_size;
  847. struct mvpp2_pcpu_stats __percpu *stats;
  848. struct phy_device *phy_dev;
  849. phy_interface_t phy_interface;
  850. int phyaddr;
  851. struct udevice *mdio_dev;
  852. struct mii_dev *bus;
  853. #if CONFIG_IS_ENABLED(DM_GPIO)
  854. struct gpio_desc phy_reset_gpio;
  855. struct gpio_desc phy_tx_disable_gpio;
  856. #endif
  857. int init;
  858. unsigned int link;
  859. unsigned int duplex;
  860. unsigned int speed;
  861. struct mvpp2_bm_pool *pool_long;
  862. struct mvpp2_bm_pool *pool_short;
  863. /* Index of first port's physical RXQ */
  864. u8 first_rxq;
  865. u8 dev_addr[ETH_ALEN];
  866. };
  867. /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
  868. * layout of the transmit and reception DMA descriptors, and their
  869. * layout is therefore defined by the hardware design
  870. */
  871. #define MVPP2_TXD_L3_OFF_SHIFT 0
  872. #define MVPP2_TXD_IP_HLEN_SHIFT 8
  873. #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
  874. #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
  875. #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
  876. #define MVPP2_TXD_PADDING_DISABLE BIT(23)
  877. #define MVPP2_TXD_L4_UDP BIT(24)
  878. #define MVPP2_TXD_L3_IP6 BIT(26)
  879. #define MVPP2_TXD_L_DESC BIT(28)
  880. #define MVPP2_TXD_F_DESC BIT(29)
  881. #define MVPP2_RXD_ERR_SUMMARY BIT(15)
  882. #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
  883. #define MVPP2_RXD_ERR_CRC 0x0
  884. #define MVPP2_RXD_ERR_OVERRUN BIT(13)
  885. #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
  886. #define MVPP2_RXD_BM_POOL_ID_OFFS 16
  887. #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
  888. #define MVPP2_RXD_HWF_SYNC BIT(21)
  889. #define MVPP2_RXD_L4_CSUM_OK BIT(22)
  890. #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
  891. #define MVPP2_RXD_L4_TCP BIT(25)
  892. #define MVPP2_RXD_L4_UDP BIT(26)
  893. #define MVPP2_RXD_L3_IP4 BIT(28)
  894. #define MVPP2_RXD_L3_IP6 BIT(30)
  895. #define MVPP2_RXD_BUF_HDR BIT(31)
  896. /* HW TX descriptor for PPv2.1 */
  897. struct mvpp21_tx_desc {
  898. u32 command; /* Options used by HW for packet transmitting.*/
  899. u8 packet_offset; /* the offset from the buffer beginning */
  900. u8 phys_txq; /* destination queue ID */
  901. u16 data_size; /* data size of transmitted packet in bytes */
  902. u32 buf_dma_addr; /* physical addr of transmitted buffer */
  903. u32 buf_cookie; /* cookie for access to TX buffer in tx path */
  904. u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
  905. u32 reserved2; /* reserved (for future use) */
  906. };
  907. /* HW RX descriptor for PPv2.1 */
  908. struct mvpp21_rx_desc {
  909. u32 status; /* info about received packet */
  910. u16 reserved1; /* parser_info (for future use, PnC) */
  911. u16 data_size; /* size of received packet in bytes */
  912. u32 buf_dma_addr; /* physical address of the buffer */
  913. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  914. u16 reserved2; /* gem_port_id (for future use, PON) */
  915. u16 reserved3; /* csum_l4 (for future use, PnC) */
  916. u8 reserved4; /* bm_qset (for future use, BM) */
  917. u8 reserved5;
  918. u16 reserved6; /* classify_info (for future use, PnC) */
  919. u32 reserved7; /* flow_id (for future use, PnC) */
  920. u32 reserved8;
  921. };
  922. /* HW TX descriptor for PPv2.2 */
  923. struct mvpp22_tx_desc {
  924. u32 command;
  925. u8 packet_offset;
  926. u8 phys_txq;
  927. u16 data_size;
  928. u64 reserved1;
  929. u64 buf_dma_addr_ptp;
  930. u64 buf_cookie_misc;
  931. };
  932. /* HW RX descriptor for PPv2.2 */
  933. struct mvpp22_rx_desc {
  934. u32 status;
  935. u16 reserved1;
  936. u16 data_size;
  937. u32 reserved2;
  938. u32 reserved3;
  939. u64 buf_dma_addr_key_hash;
  940. u64 buf_cookie_misc;
  941. };
  942. /* Opaque type used by the driver to manipulate the HW TX and RX
  943. * descriptors
  944. */
  945. struct mvpp2_tx_desc {
  946. union {
  947. struct mvpp21_tx_desc pp21;
  948. struct mvpp22_tx_desc pp22;
  949. };
  950. };
  951. struct mvpp2_rx_desc {
  952. union {
  953. struct mvpp21_rx_desc pp21;
  954. struct mvpp22_rx_desc pp22;
  955. };
  956. };
  957. /* Per-CPU Tx queue control */
  958. struct mvpp2_txq_pcpu {
  959. int cpu;
  960. /* Number of Tx DMA descriptors in the descriptor ring */
  961. int size;
  962. /* Number of currently used Tx DMA descriptor in the
  963. * descriptor ring
  964. */
  965. int count;
  966. /* Number of Tx DMA descriptors reserved for each CPU */
  967. int reserved_num;
  968. /* Index of last TX DMA descriptor that was inserted */
  969. int txq_put_index;
  970. /* Index of the TX DMA descriptor to be cleaned up */
  971. int txq_get_index;
  972. };
  973. struct mvpp2_tx_queue {
  974. /* Physical number of this Tx queue */
  975. u8 id;
  976. /* Logical number of this Tx queue */
  977. u8 log_id;
  978. /* Number of Tx DMA descriptors in the descriptor ring */
  979. int size;
  980. /* Number of currently used Tx DMA descriptor in the descriptor ring */
  981. int count;
  982. /* Per-CPU control of physical Tx queues */
  983. struct mvpp2_txq_pcpu __percpu *pcpu;
  984. u32 done_pkts_coal;
  985. /* Virtual address of thex Tx DMA descriptors array */
  986. struct mvpp2_tx_desc *descs;
  987. /* DMA address of the Tx DMA descriptors array */
  988. dma_addr_t descs_dma;
  989. /* Index of the last Tx DMA descriptor */
  990. int last_desc;
  991. /* Index of the next Tx DMA descriptor to process */
  992. int next_desc_to_proc;
  993. };
  994. struct mvpp2_rx_queue {
  995. /* RX queue number, in the range 0-31 for physical RXQs */
  996. u8 id;
  997. /* Num of rx descriptors in the rx descriptor ring */
  998. int size;
  999. u32 pkts_coal;
  1000. u32 time_coal;
  1001. /* Virtual address of the RX DMA descriptors array */
  1002. struct mvpp2_rx_desc *descs;
  1003. /* DMA address of the RX DMA descriptors array */
  1004. dma_addr_t descs_dma;
  1005. /* Index of the last RX DMA descriptor */
  1006. int last_desc;
  1007. /* Index of the next RX DMA descriptor to process */
  1008. int next_desc_to_proc;
  1009. /* ID of port to which physical RXQ is mapped */
  1010. int port;
  1011. /* Port's logic RXQ number to which physical RXQ is mapped */
  1012. int logic_rxq;
  1013. };
  1014. union mvpp2_prs_tcam_entry {
  1015. u32 word[MVPP2_PRS_TCAM_WORDS];
  1016. u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
  1017. };
  1018. union mvpp2_prs_sram_entry {
  1019. u32 word[MVPP2_PRS_SRAM_WORDS];
  1020. u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
  1021. };
  1022. struct mvpp2_prs_entry {
  1023. u32 index;
  1024. union mvpp2_prs_tcam_entry tcam;
  1025. union mvpp2_prs_sram_entry sram;
  1026. };
  1027. struct mvpp2_prs_shadow {
  1028. bool valid;
  1029. bool finish;
  1030. /* Lookup ID */
  1031. int lu;
  1032. /* User defined offset */
  1033. int udf;
  1034. /* Result info */
  1035. u32 ri;
  1036. u32 ri_mask;
  1037. };
  1038. struct mvpp2_cls_flow_entry {
  1039. u32 index;
  1040. u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
  1041. };
  1042. struct mvpp2_cls_lookup_entry {
  1043. u32 lkpid;
  1044. u32 way;
  1045. u32 data;
  1046. };
  1047. struct mvpp2_bm_pool {
  1048. /* Pool number in the range 0-7 */
  1049. int id;
  1050. enum mvpp2_bm_type type;
  1051. /* Buffer Pointers Pool External (BPPE) size */
  1052. int size;
  1053. /* Number of buffers for this pool */
  1054. int buf_num;
  1055. /* Pool buffer size */
  1056. int buf_size;
  1057. /* Packet size */
  1058. int pkt_size;
  1059. /* BPPE virtual base address */
  1060. unsigned long *virt_addr;
  1061. /* BPPE DMA base address */
  1062. dma_addr_t dma_addr;
  1063. /* Ports using BM pool */
  1064. u32 port_map;
  1065. };
  1066. /* Static declaractions */
  1067. /* Number of RXQs used by single port */
  1068. static int rxq_number = MVPP2_DEFAULT_RXQ;
  1069. /* Number of TXQs used by single port */
  1070. static int txq_number = MVPP2_DEFAULT_TXQ;
  1071. static int base_id;
  1072. #define MVPP2_DRIVER_NAME "mvpp2"
  1073. #define MVPP2_DRIVER_VERSION "1.0"
  1074. /*
  1075. * U-Boot internal data, mostly uncached buffers for descriptors and data
  1076. */
  1077. struct buffer_location {
  1078. struct mvpp2_tx_desc *aggr_tx_descs;
  1079. struct mvpp2_tx_desc *tx_descs;
  1080. struct mvpp2_rx_desc *rx_descs;
  1081. unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
  1082. unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
  1083. int first_rxq;
  1084. };
  1085. /*
  1086. * All 4 interfaces use the same global buffer, since only one interface
  1087. * can be enabled at once
  1088. */
  1089. static struct buffer_location buffer_loc;
  1090. static int buffer_loc_init;
  1091. /*
  1092. * Page table entries are set to 1MB, or multiples of 1MB
  1093. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  1094. */
  1095. #define BD_SPACE (1 << 20)
  1096. /* Utility/helper methods */
  1097. static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  1098. {
  1099. writel(data, priv->base + offset);
  1100. }
  1101. static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  1102. {
  1103. return readl(priv->base + offset);
  1104. }
  1105. static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
  1106. struct mvpp2_tx_desc *tx_desc,
  1107. dma_addr_t dma_addr)
  1108. {
  1109. if (port->priv->hw_version == MVPP21) {
  1110. tx_desc->pp21.buf_dma_addr = dma_addr;
  1111. } else {
  1112. u64 val = (u64)dma_addr;
  1113. tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
  1114. tx_desc->pp22.buf_dma_addr_ptp |= val;
  1115. }
  1116. }
  1117. static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
  1118. struct mvpp2_tx_desc *tx_desc,
  1119. size_t size)
  1120. {
  1121. if (port->priv->hw_version == MVPP21)
  1122. tx_desc->pp21.data_size = size;
  1123. else
  1124. tx_desc->pp22.data_size = size;
  1125. }
  1126. static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
  1127. struct mvpp2_tx_desc *tx_desc,
  1128. unsigned int txq)
  1129. {
  1130. if (port->priv->hw_version == MVPP21)
  1131. tx_desc->pp21.phys_txq = txq;
  1132. else
  1133. tx_desc->pp22.phys_txq = txq;
  1134. }
  1135. static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
  1136. struct mvpp2_tx_desc *tx_desc,
  1137. unsigned int command)
  1138. {
  1139. if (port->priv->hw_version == MVPP21)
  1140. tx_desc->pp21.command = command;
  1141. else
  1142. tx_desc->pp22.command = command;
  1143. }
  1144. static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
  1145. struct mvpp2_tx_desc *tx_desc,
  1146. unsigned int offset)
  1147. {
  1148. if (port->priv->hw_version == MVPP21)
  1149. tx_desc->pp21.packet_offset = offset;
  1150. else
  1151. tx_desc->pp22.packet_offset = offset;
  1152. }
  1153. static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
  1154. struct mvpp2_rx_desc *rx_desc)
  1155. {
  1156. if (port->priv->hw_version == MVPP21)
  1157. return rx_desc->pp21.buf_dma_addr;
  1158. else
  1159. return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
  1160. }
  1161. static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
  1162. struct mvpp2_rx_desc *rx_desc)
  1163. {
  1164. if (port->priv->hw_version == MVPP21)
  1165. return rx_desc->pp21.buf_cookie;
  1166. else
  1167. return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
  1168. }
  1169. static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
  1170. struct mvpp2_rx_desc *rx_desc)
  1171. {
  1172. if (port->priv->hw_version == MVPP21)
  1173. return rx_desc->pp21.data_size;
  1174. else
  1175. return rx_desc->pp22.data_size;
  1176. }
  1177. static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
  1178. struct mvpp2_rx_desc *rx_desc)
  1179. {
  1180. if (port->priv->hw_version == MVPP21)
  1181. return rx_desc->pp21.status;
  1182. else
  1183. return rx_desc->pp22.status;
  1184. }
  1185. static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
  1186. {
  1187. txq_pcpu->txq_get_index++;
  1188. if (txq_pcpu->txq_get_index == txq_pcpu->size)
  1189. txq_pcpu->txq_get_index = 0;
  1190. }
  1191. /* Get number of physical egress port */
  1192. static inline int mvpp2_egress_port(struct mvpp2_port *port)
  1193. {
  1194. return MVPP2_MAX_TCONT + port->id;
  1195. }
  1196. /* Get number of physical TXQ */
  1197. static inline int mvpp2_txq_phys(int port, int txq)
  1198. {
  1199. return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
  1200. }
  1201. /* Parser configuration routines */
  1202. /* Update parser tcam and sram hw entries */
  1203. static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1204. {
  1205. int i;
  1206. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1207. return -EINVAL;
  1208. /* Clear entry invalidation bit */
  1209. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
  1210. /* Write tcam index - indirect access */
  1211. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1212. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1213. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
  1214. /* Write sram index - indirect access */
  1215. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1216. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1217. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
  1218. return 0;
  1219. }
  1220. /* Read tcam entry from hw */
  1221. static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1222. {
  1223. int i;
  1224. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1225. return -EINVAL;
  1226. /* Write tcam index - indirect access */
  1227. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1228. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
  1229. MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
  1230. if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
  1231. return MVPP2_PRS_TCAM_ENTRY_INVALID;
  1232. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1233. pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
  1234. /* Write sram index - indirect access */
  1235. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1236. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1237. pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
  1238. return 0;
  1239. }
  1240. /* Invalidate tcam hw entry */
  1241. static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
  1242. {
  1243. /* Write index - indirect access */
  1244. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1245. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
  1246. MVPP2_PRS_TCAM_INV_MASK);
  1247. }
  1248. /* Enable shadow table entry and set its lookup ID */
  1249. static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
  1250. {
  1251. priv->prs_shadow[index].valid = true;
  1252. priv->prs_shadow[index].lu = lu;
  1253. }
  1254. /* Update ri fields in shadow table entry */
  1255. static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
  1256. unsigned int ri, unsigned int ri_mask)
  1257. {
  1258. priv->prs_shadow[index].ri_mask = ri_mask;
  1259. priv->prs_shadow[index].ri = ri;
  1260. }
  1261. /* Update lookup field in tcam sw entry */
  1262. static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
  1263. {
  1264. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
  1265. pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
  1266. pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
  1267. }
  1268. /* Update mask for single port in tcam sw entry */
  1269. static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
  1270. unsigned int port, bool add)
  1271. {
  1272. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1273. if (add)
  1274. pe->tcam.byte[enable_off] &= ~(1 << port);
  1275. else
  1276. pe->tcam.byte[enable_off] |= 1 << port;
  1277. }
  1278. /* Update port map in tcam sw entry */
  1279. static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
  1280. unsigned int ports)
  1281. {
  1282. unsigned char port_mask = MVPP2_PRS_PORT_MASK;
  1283. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1284. pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
  1285. pe->tcam.byte[enable_off] &= ~port_mask;
  1286. pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
  1287. }
  1288. /* Obtain port map from tcam sw entry */
  1289. static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
  1290. {
  1291. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1292. return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
  1293. }
  1294. /* Set byte of data and its enable bits in tcam sw entry */
  1295. static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
  1296. unsigned int offs, unsigned char byte,
  1297. unsigned char enable)
  1298. {
  1299. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
  1300. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
  1301. }
  1302. /* Get byte of data and its enable bits from tcam sw entry */
  1303. static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
  1304. unsigned int offs, unsigned char *byte,
  1305. unsigned char *enable)
  1306. {
  1307. *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
  1308. *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
  1309. }
  1310. /* Set ethertype in tcam sw entry */
  1311. static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
  1312. unsigned short ethertype)
  1313. {
  1314. mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
  1315. mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
  1316. }
  1317. /* Set bits in sram sw entry */
  1318. static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
  1319. int val)
  1320. {
  1321. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
  1322. }
  1323. /* Clear bits in sram sw entry */
  1324. static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
  1325. int val)
  1326. {
  1327. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
  1328. }
  1329. /* Update ri bits in sram sw entry */
  1330. static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
  1331. unsigned int bits, unsigned int mask)
  1332. {
  1333. unsigned int i;
  1334. for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
  1335. int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
  1336. if (!(mask & BIT(i)))
  1337. continue;
  1338. if (bits & BIT(i))
  1339. mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
  1340. else
  1341. mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
  1342. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
  1343. }
  1344. }
  1345. /* Update ai bits in sram sw entry */
  1346. static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
  1347. unsigned int bits, unsigned int mask)
  1348. {
  1349. unsigned int i;
  1350. int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
  1351. for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
  1352. if (!(mask & BIT(i)))
  1353. continue;
  1354. if (bits & BIT(i))
  1355. mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
  1356. else
  1357. mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
  1358. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
  1359. }
  1360. }
  1361. /* Read ai bits from sram sw entry */
  1362. static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
  1363. {
  1364. u8 bits;
  1365. int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
  1366. int ai_en_off = ai_off + 1;
  1367. int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
  1368. bits = (pe->sram.byte[ai_off] >> ai_shift) |
  1369. (pe->sram.byte[ai_en_off] << (8 - ai_shift));
  1370. return bits;
  1371. }
  1372. /* In sram sw entry set lookup ID field of the tcam key to be used in the next
  1373. * lookup interation
  1374. */
  1375. static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
  1376. unsigned int lu)
  1377. {
  1378. int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
  1379. mvpp2_prs_sram_bits_clear(pe, sram_next_off,
  1380. MVPP2_PRS_SRAM_NEXT_LU_MASK);
  1381. mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
  1382. }
  1383. /* In the sram sw entry set sign and value of the next lookup offset
  1384. * and the offset value generated to the classifier
  1385. */
  1386. static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
  1387. unsigned int op)
  1388. {
  1389. /* Set sign */
  1390. if (shift < 0) {
  1391. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1392. shift = 0 - shift;
  1393. } else {
  1394. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1395. }
  1396. /* Set value */
  1397. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
  1398. (unsigned char)shift;
  1399. /* Reset and set operation */
  1400. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
  1401. MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
  1402. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
  1403. /* Set base offset as current */
  1404. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1405. }
  1406. /* In the sram sw entry set sign and value of the user defined offset
  1407. * generated to the classifier
  1408. */
  1409. static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
  1410. unsigned int type, int offset,
  1411. unsigned int op)
  1412. {
  1413. /* Set sign */
  1414. if (offset < 0) {
  1415. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1416. offset = 0 - offset;
  1417. } else {
  1418. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1419. }
  1420. /* Set value */
  1421. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
  1422. MVPP2_PRS_SRAM_UDF_MASK);
  1423. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
  1424. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1425. MVPP2_PRS_SRAM_UDF_BITS)] &=
  1426. ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1427. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1428. MVPP2_PRS_SRAM_UDF_BITS)] |=
  1429. (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1430. /* Set offset type */
  1431. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
  1432. MVPP2_PRS_SRAM_UDF_TYPE_MASK);
  1433. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
  1434. /* Set offset operation */
  1435. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
  1436. MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
  1437. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
  1438. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1439. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
  1440. ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
  1441. (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1442. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1443. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
  1444. (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1445. /* Set base offset as current */
  1446. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1447. }
  1448. /* Find parser flow entry */
  1449. static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
  1450. {
  1451. struct mvpp2_prs_entry *pe;
  1452. int tid;
  1453. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1454. if (!pe)
  1455. return NULL;
  1456. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  1457. /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
  1458. for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
  1459. u8 bits;
  1460. if (!priv->prs_shadow[tid].valid ||
  1461. priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
  1462. continue;
  1463. pe->index = tid;
  1464. mvpp2_prs_hw_read(priv, pe);
  1465. bits = mvpp2_prs_sram_ai_get(pe);
  1466. /* Sram store classification lookup ID in AI bits [5:0] */
  1467. if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
  1468. return pe;
  1469. }
  1470. kfree(pe);
  1471. return NULL;
  1472. }
  1473. /* Return first free tcam index, seeking from start to end */
  1474. static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
  1475. unsigned char end)
  1476. {
  1477. int tid;
  1478. if (start > end)
  1479. swap(start, end);
  1480. if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
  1481. end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
  1482. for (tid = start; tid <= end; tid++) {
  1483. if (!priv->prs_shadow[tid].valid)
  1484. return tid;
  1485. }
  1486. return -EINVAL;
  1487. }
  1488. /* Enable/disable dropping all mac da's */
  1489. static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
  1490. {
  1491. struct mvpp2_prs_entry pe;
  1492. if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
  1493. /* Entry exist - update port only */
  1494. pe.index = MVPP2_PE_DROP_ALL;
  1495. mvpp2_prs_hw_read(priv, &pe);
  1496. } else {
  1497. /* Entry doesn't exist - create new */
  1498. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1499. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1500. pe.index = MVPP2_PE_DROP_ALL;
  1501. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1502. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1503. MVPP2_PRS_RI_DROP_MASK);
  1504. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1505. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1506. /* Update shadow table */
  1507. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1508. /* Mask all ports */
  1509. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1510. }
  1511. /* Update port mask */
  1512. mvpp2_prs_tcam_port_set(&pe, port, add);
  1513. mvpp2_prs_hw_write(priv, &pe);
  1514. }
  1515. /* Set port to promiscuous mode */
  1516. static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
  1517. {
  1518. struct mvpp2_prs_entry pe;
  1519. /* Promiscuous mode - Accept unknown packets */
  1520. if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
  1521. /* Entry exist - update port only */
  1522. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1523. mvpp2_prs_hw_read(priv, &pe);
  1524. } else {
  1525. /* Entry doesn't exist - create new */
  1526. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1527. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1528. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1529. /* Continue - set next lookup */
  1530. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1531. /* Set result info bits */
  1532. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
  1533. MVPP2_PRS_RI_L2_CAST_MASK);
  1534. /* Shift to ethertype */
  1535. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1536. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1537. /* Mask all ports */
  1538. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1539. /* Update shadow table */
  1540. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1541. }
  1542. /* Update port mask */
  1543. mvpp2_prs_tcam_port_set(&pe, port, add);
  1544. mvpp2_prs_hw_write(priv, &pe);
  1545. }
  1546. /* Accept multicast */
  1547. static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
  1548. bool add)
  1549. {
  1550. struct mvpp2_prs_entry pe;
  1551. unsigned char da_mc;
  1552. /* Ethernet multicast address first byte is
  1553. * 0x01 for IPv4 and 0x33 for IPv6
  1554. */
  1555. da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
  1556. if (priv->prs_shadow[index].valid) {
  1557. /* Entry exist - update port only */
  1558. pe.index = index;
  1559. mvpp2_prs_hw_read(priv, &pe);
  1560. } else {
  1561. /* Entry doesn't exist - create new */
  1562. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1563. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1564. pe.index = index;
  1565. /* Continue - set next lookup */
  1566. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1567. /* Set result info bits */
  1568. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
  1569. MVPP2_PRS_RI_L2_CAST_MASK);
  1570. /* Update tcam entry data first byte */
  1571. mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
  1572. /* Shift to ethertype */
  1573. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1574. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1575. /* Mask all ports */
  1576. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1577. /* Update shadow table */
  1578. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1579. }
  1580. /* Update port mask */
  1581. mvpp2_prs_tcam_port_set(&pe, port, add);
  1582. mvpp2_prs_hw_write(priv, &pe);
  1583. }
  1584. /* Parser per-port initialization */
  1585. static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
  1586. int lu_max, int offset)
  1587. {
  1588. u32 val;
  1589. /* Set lookup ID */
  1590. val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
  1591. val &= ~MVPP2_PRS_PORT_LU_MASK(port);
  1592. val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
  1593. mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
  1594. /* Set maximum number of loops for packet received from port */
  1595. val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
  1596. val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
  1597. val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
  1598. mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
  1599. /* Set initial offset for packet header extraction for the first
  1600. * searching loop
  1601. */
  1602. val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
  1603. val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
  1604. val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
  1605. mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
  1606. }
  1607. /* Default flow entries initialization for all ports */
  1608. static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
  1609. {
  1610. struct mvpp2_prs_entry pe;
  1611. int port;
  1612. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  1613. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1614. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1615. pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
  1616. /* Mask all ports */
  1617. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1618. /* Set flow ID*/
  1619. mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
  1620. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  1621. /* Update shadow table and hw entry */
  1622. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
  1623. mvpp2_prs_hw_write(priv, &pe);
  1624. }
  1625. }
  1626. /* Set default entry for Marvell Header field */
  1627. static void mvpp2_prs_mh_init(struct mvpp2 *priv)
  1628. {
  1629. struct mvpp2_prs_entry pe;
  1630. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1631. pe.index = MVPP2_PE_MH_DEFAULT;
  1632. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
  1633. mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
  1634. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1635. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1636. /* Unmask all ports */
  1637. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1638. /* Update shadow table and hw entry */
  1639. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
  1640. mvpp2_prs_hw_write(priv, &pe);
  1641. }
  1642. /* Set default entires (place holder) for promiscuous, non-promiscuous and
  1643. * multicast MAC addresses
  1644. */
  1645. static void mvpp2_prs_mac_init(struct mvpp2 *priv)
  1646. {
  1647. struct mvpp2_prs_entry pe;
  1648. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1649. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1650. pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
  1651. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1652. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1653. MVPP2_PRS_RI_DROP_MASK);
  1654. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1655. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1656. /* Unmask all ports */
  1657. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1658. /* Update shadow table and hw entry */
  1659. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1660. mvpp2_prs_hw_write(priv, &pe);
  1661. /* place holders only - no ports */
  1662. mvpp2_prs_mac_drop_all_set(priv, 0, false);
  1663. mvpp2_prs_mac_promisc_set(priv, 0, false);
  1664. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
  1665. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
  1666. }
  1667. /* Match basic ethertypes */
  1668. static int mvpp2_prs_etype_init(struct mvpp2 *priv)
  1669. {
  1670. struct mvpp2_prs_entry pe;
  1671. int tid;
  1672. /* Ethertype: PPPoE */
  1673. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1674. MVPP2_PE_LAST_FREE_TID);
  1675. if (tid < 0)
  1676. return tid;
  1677. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1678. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1679. pe.index = tid;
  1680. mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
  1681. mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
  1682. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1683. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
  1684. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
  1685. MVPP2_PRS_RI_PPPOE_MASK);
  1686. /* Update shadow table and hw entry */
  1687. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1688. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1689. priv->prs_shadow[pe.index].finish = false;
  1690. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
  1691. MVPP2_PRS_RI_PPPOE_MASK);
  1692. mvpp2_prs_hw_write(priv, &pe);
  1693. /* Ethertype: ARP */
  1694. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1695. MVPP2_PE_LAST_FREE_TID);
  1696. if (tid < 0)
  1697. return tid;
  1698. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1699. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1700. pe.index = tid;
  1701. mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
  1702. /* Generate flow in the next iteration*/
  1703. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1704. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1705. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
  1706. MVPP2_PRS_RI_L3_PROTO_MASK);
  1707. /* Set L3 offset */
  1708. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1709. MVPP2_ETH_TYPE_LEN,
  1710. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1711. /* Update shadow table and hw entry */
  1712. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1713. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1714. priv->prs_shadow[pe.index].finish = true;
  1715. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
  1716. MVPP2_PRS_RI_L3_PROTO_MASK);
  1717. mvpp2_prs_hw_write(priv, &pe);
  1718. /* Ethertype: LBTD */
  1719. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1720. MVPP2_PE_LAST_FREE_TID);
  1721. if (tid < 0)
  1722. return tid;
  1723. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1724. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1725. pe.index = tid;
  1726. mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
  1727. /* Generate flow in the next iteration*/
  1728. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1729. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1730. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1731. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1732. MVPP2_PRS_RI_CPU_CODE_MASK |
  1733. MVPP2_PRS_RI_UDF3_MASK);
  1734. /* Set L3 offset */
  1735. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1736. MVPP2_ETH_TYPE_LEN,
  1737. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1738. /* Update shadow table and hw entry */
  1739. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1740. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1741. priv->prs_shadow[pe.index].finish = true;
  1742. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1743. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1744. MVPP2_PRS_RI_CPU_CODE_MASK |
  1745. MVPP2_PRS_RI_UDF3_MASK);
  1746. mvpp2_prs_hw_write(priv, &pe);
  1747. /* Ethertype: IPv4 without options */
  1748. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1749. MVPP2_PE_LAST_FREE_TID);
  1750. if (tid < 0)
  1751. return tid;
  1752. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1753. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1754. pe.index = tid;
  1755. mvpp2_prs_match_etype(&pe, 0, PROT_IP);
  1756. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1757. MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
  1758. MVPP2_PRS_IPV4_HEAD_MASK |
  1759. MVPP2_PRS_IPV4_IHL_MASK);
  1760. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
  1761. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
  1762. MVPP2_PRS_RI_L3_PROTO_MASK);
  1763. /* Skip eth_type + 4 bytes of IP header */
  1764. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
  1765. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1766. /* Set L3 offset */
  1767. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1768. MVPP2_ETH_TYPE_LEN,
  1769. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1770. /* Update shadow table and hw entry */
  1771. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1772. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1773. priv->prs_shadow[pe.index].finish = false;
  1774. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
  1775. MVPP2_PRS_RI_L3_PROTO_MASK);
  1776. mvpp2_prs_hw_write(priv, &pe);
  1777. /* Ethertype: IPv4 with options */
  1778. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1779. MVPP2_PE_LAST_FREE_TID);
  1780. if (tid < 0)
  1781. return tid;
  1782. pe.index = tid;
  1783. /* Clear tcam data before updating */
  1784. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1785. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1786. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1787. MVPP2_PRS_IPV4_HEAD,
  1788. MVPP2_PRS_IPV4_HEAD_MASK);
  1789. /* Clear ri before updating */
  1790. pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
  1791. pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
  1792. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
  1793. MVPP2_PRS_RI_L3_PROTO_MASK);
  1794. /* Update shadow table and hw entry */
  1795. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1796. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1797. priv->prs_shadow[pe.index].finish = false;
  1798. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
  1799. MVPP2_PRS_RI_L3_PROTO_MASK);
  1800. mvpp2_prs_hw_write(priv, &pe);
  1801. /* Ethertype: IPv6 without options */
  1802. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1803. MVPP2_PE_LAST_FREE_TID);
  1804. if (tid < 0)
  1805. return tid;
  1806. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1807. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1808. pe.index = tid;
  1809. mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
  1810. /* Skip DIP of IPV6 header */
  1811. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
  1812. MVPP2_MAX_L3_ADDR_SIZE,
  1813. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1814. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
  1815. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
  1816. MVPP2_PRS_RI_L3_PROTO_MASK);
  1817. /* Set L3 offset */
  1818. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1819. MVPP2_ETH_TYPE_LEN,
  1820. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1821. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1822. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1823. priv->prs_shadow[pe.index].finish = false;
  1824. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
  1825. MVPP2_PRS_RI_L3_PROTO_MASK);
  1826. mvpp2_prs_hw_write(priv, &pe);
  1827. /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
  1828. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1829. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1830. pe.index = MVPP2_PE_ETH_TYPE_UN;
  1831. /* Unmask all ports */
  1832. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1833. /* Generate flow in the next iteration*/
  1834. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1835. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1836. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
  1837. MVPP2_PRS_RI_L3_PROTO_MASK);
  1838. /* Set L3 offset even it's unknown L3 */
  1839. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1840. MVPP2_ETH_TYPE_LEN,
  1841. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1842. /* Update shadow table and hw entry */
  1843. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1844. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1845. priv->prs_shadow[pe.index].finish = true;
  1846. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
  1847. MVPP2_PRS_RI_L3_PROTO_MASK);
  1848. mvpp2_prs_hw_write(priv, &pe);
  1849. return 0;
  1850. }
  1851. /* Parser default initialization */
  1852. static int mvpp2_prs_default_init(struct udevice *dev,
  1853. struct mvpp2 *priv)
  1854. {
  1855. int err, index, i;
  1856. /* Enable tcam table */
  1857. mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
  1858. /* Clear all tcam and sram entries */
  1859. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
  1860. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1861. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1862. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
  1863. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
  1864. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1865. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
  1866. }
  1867. /* Invalidate all tcam entries */
  1868. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
  1869. mvpp2_prs_hw_inv(priv, index);
  1870. priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
  1871. sizeof(struct mvpp2_prs_shadow),
  1872. GFP_KERNEL);
  1873. if (!priv->prs_shadow)
  1874. return -ENOMEM;
  1875. /* Always start from lookup = 0 */
  1876. for (index = 0; index < MVPP2_MAX_PORTS; index++)
  1877. mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
  1878. MVPP2_PRS_PORT_LU_MAX, 0);
  1879. mvpp2_prs_def_flow_init(priv);
  1880. mvpp2_prs_mh_init(priv);
  1881. mvpp2_prs_mac_init(priv);
  1882. err = mvpp2_prs_etype_init(priv);
  1883. if (err)
  1884. return err;
  1885. return 0;
  1886. }
  1887. /* Compare MAC DA with tcam entry data */
  1888. static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
  1889. const u8 *da, unsigned char *mask)
  1890. {
  1891. unsigned char tcam_byte, tcam_mask;
  1892. int index;
  1893. for (index = 0; index < ETH_ALEN; index++) {
  1894. mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
  1895. if (tcam_mask != mask[index])
  1896. return false;
  1897. if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
  1898. return false;
  1899. }
  1900. return true;
  1901. }
  1902. /* Find tcam entry with matched pair <MAC DA, port> */
  1903. static struct mvpp2_prs_entry *
  1904. mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
  1905. unsigned char *mask, int udf_type)
  1906. {
  1907. struct mvpp2_prs_entry *pe;
  1908. int tid;
  1909. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1910. if (!pe)
  1911. return NULL;
  1912. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1913. /* Go through the all entires with MVPP2_PRS_LU_MAC */
  1914. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1915. tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
  1916. unsigned int entry_pmap;
  1917. if (!priv->prs_shadow[tid].valid ||
  1918. (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
  1919. (priv->prs_shadow[tid].udf != udf_type))
  1920. continue;
  1921. pe->index = tid;
  1922. mvpp2_prs_hw_read(priv, pe);
  1923. entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
  1924. if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
  1925. entry_pmap == pmap)
  1926. return pe;
  1927. }
  1928. kfree(pe);
  1929. return NULL;
  1930. }
  1931. /* Update parser's mac da entry */
  1932. static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
  1933. const u8 *da, bool add)
  1934. {
  1935. struct mvpp2_prs_entry *pe;
  1936. unsigned int pmap, len, ri;
  1937. unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  1938. int tid;
  1939. /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
  1940. pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
  1941. MVPP2_PRS_UDF_MAC_DEF);
  1942. /* No such entry */
  1943. if (!pe) {
  1944. if (!add)
  1945. return 0;
  1946. /* Create new TCAM entry */
  1947. /* Find first range mac entry*/
  1948. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1949. tid <= MVPP2_PE_LAST_FREE_TID; tid++)
  1950. if (priv->prs_shadow[tid].valid &&
  1951. (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
  1952. (priv->prs_shadow[tid].udf ==
  1953. MVPP2_PRS_UDF_MAC_RANGE))
  1954. break;
  1955. /* Go through the all entries from first to last */
  1956. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1957. tid - 1);
  1958. if (tid < 0)
  1959. return tid;
  1960. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1961. if (!pe)
  1962. return -1;
  1963. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1964. pe->index = tid;
  1965. /* Mask all ports */
  1966. mvpp2_prs_tcam_port_map_set(pe, 0);
  1967. }
  1968. /* Update port mask */
  1969. mvpp2_prs_tcam_port_set(pe, port, add);
  1970. /* Invalidate the entry if no ports are left enabled */
  1971. pmap = mvpp2_prs_tcam_port_map_get(pe);
  1972. if (pmap == 0) {
  1973. if (add) {
  1974. kfree(pe);
  1975. return -1;
  1976. }
  1977. mvpp2_prs_hw_inv(priv, pe->index);
  1978. priv->prs_shadow[pe->index].valid = false;
  1979. kfree(pe);
  1980. return 0;
  1981. }
  1982. /* Continue - set next lookup */
  1983. mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
  1984. /* Set match on DA */
  1985. len = ETH_ALEN;
  1986. while (len--)
  1987. mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
  1988. /* Set result info bits */
  1989. ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
  1990. mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1991. MVPP2_PRS_RI_MAC_ME_MASK);
  1992. mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1993. MVPP2_PRS_RI_MAC_ME_MASK);
  1994. /* Shift to ethertype */
  1995. mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
  1996. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1997. /* Update shadow table and hw entry */
  1998. priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
  1999. mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
  2000. mvpp2_prs_hw_write(priv, pe);
  2001. kfree(pe);
  2002. return 0;
  2003. }
  2004. static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
  2005. {
  2006. int err;
  2007. /* Remove old parser entry */
  2008. err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
  2009. false);
  2010. if (err)
  2011. return err;
  2012. /* Add new parser entry */
  2013. err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
  2014. if (err)
  2015. return err;
  2016. /* Set addr in the device */
  2017. memcpy(port->dev_addr, da, ETH_ALEN);
  2018. return 0;
  2019. }
  2020. /* Set prs flow for the port */
  2021. static int mvpp2_prs_def_flow(struct mvpp2_port *port)
  2022. {
  2023. struct mvpp2_prs_entry *pe;
  2024. int tid;
  2025. pe = mvpp2_prs_flow_find(port->priv, port->id);
  2026. /* Such entry not exist */
  2027. if (!pe) {
  2028. /* Go through the all entires from last to first */
  2029. tid = mvpp2_prs_tcam_first_free(port->priv,
  2030. MVPP2_PE_LAST_FREE_TID,
  2031. MVPP2_PE_FIRST_FREE_TID);
  2032. if (tid < 0)
  2033. return tid;
  2034. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  2035. if (!pe)
  2036. return -ENOMEM;
  2037. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  2038. pe->index = tid;
  2039. /* Set flow ID*/
  2040. mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
  2041. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  2042. /* Update shadow table */
  2043. mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
  2044. }
  2045. mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
  2046. mvpp2_prs_hw_write(port->priv, pe);
  2047. kfree(pe);
  2048. return 0;
  2049. }
  2050. /* Classifier configuration routines */
  2051. /* Update classification flow table registers */
  2052. static void mvpp2_cls_flow_write(struct mvpp2 *priv,
  2053. struct mvpp2_cls_flow_entry *fe)
  2054. {
  2055. mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
  2056. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
  2057. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
  2058. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
  2059. }
  2060. /* Update classification lookup table register */
  2061. static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
  2062. struct mvpp2_cls_lookup_entry *le)
  2063. {
  2064. u32 val;
  2065. val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
  2066. mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
  2067. mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
  2068. }
  2069. /* Classifier default initialization */
  2070. static void mvpp2_cls_init(struct mvpp2 *priv)
  2071. {
  2072. struct mvpp2_cls_lookup_entry le;
  2073. struct mvpp2_cls_flow_entry fe;
  2074. int index;
  2075. /* Enable classifier */
  2076. mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
  2077. /* Clear classifier flow table */
  2078. memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
  2079. for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
  2080. fe.index = index;
  2081. mvpp2_cls_flow_write(priv, &fe);
  2082. }
  2083. /* Clear classifier lookup table */
  2084. le.data = 0;
  2085. for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
  2086. le.lkpid = index;
  2087. le.way = 0;
  2088. mvpp2_cls_lookup_write(priv, &le);
  2089. le.way = 1;
  2090. mvpp2_cls_lookup_write(priv, &le);
  2091. }
  2092. }
  2093. static void mvpp2_cls_port_config(struct mvpp2_port *port)
  2094. {
  2095. struct mvpp2_cls_lookup_entry le;
  2096. u32 val;
  2097. /* Set way for the port */
  2098. val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
  2099. val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
  2100. mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
  2101. /* Pick the entry to be accessed in lookup ID decoding table
  2102. * according to the way and lkpid.
  2103. */
  2104. le.lkpid = port->id;
  2105. le.way = 0;
  2106. le.data = 0;
  2107. /* Set initial CPU queue for receiving packets */
  2108. le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
  2109. le.data |= port->first_rxq;
  2110. /* Disable classification engines */
  2111. le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
  2112. /* Update lookup ID table entry */
  2113. mvpp2_cls_lookup_write(port->priv, &le);
  2114. }
  2115. /* Set CPU queue number for oversize packets */
  2116. static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
  2117. {
  2118. u32 val;
  2119. mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
  2120. port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
  2121. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
  2122. (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
  2123. val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
  2124. val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
  2125. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
  2126. }
  2127. /* Buffer Manager configuration routines */
  2128. /* Create pool */
  2129. static int mvpp2_bm_pool_create(struct udevice *dev,
  2130. struct mvpp2 *priv,
  2131. struct mvpp2_bm_pool *bm_pool, int size)
  2132. {
  2133. u32 val;
  2134. /* Number of buffer pointers must be a multiple of 16, as per
  2135. * hardware constraints
  2136. */
  2137. if (!IS_ALIGNED(size, 16))
  2138. return -EINVAL;
  2139. bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
  2140. bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
  2141. if (!bm_pool->virt_addr)
  2142. return -ENOMEM;
  2143. if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
  2144. MVPP2_BM_POOL_PTR_ALIGN)) {
  2145. dev_err(dev, "BM pool %d is not %d bytes aligned\n",
  2146. bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
  2147. return -ENOMEM;
  2148. }
  2149. mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
  2150. lower_32_bits(bm_pool->dma_addr));
  2151. if (priv->hw_version == MVPP22)
  2152. mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
  2153. (upper_32_bits(bm_pool->dma_addr) &
  2154. MVPP22_BM_POOL_BASE_HIGH_MASK));
  2155. mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
  2156. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2157. val |= MVPP2_BM_START_MASK;
  2158. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2159. bm_pool->type = MVPP2_BM_FREE;
  2160. bm_pool->size = size;
  2161. bm_pool->pkt_size = 0;
  2162. bm_pool->buf_num = 0;
  2163. return 0;
  2164. }
  2165. /* Set pool buffer size */
  2166. static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
  2167. struct mvpp2_bm_pool *bm_pool,
  2168. int buf_size)
  2169. {
  2170. u32 val;
  2171. bm_pool->buf_size = buf_size;
  2172. val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
  2173. mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
  2174. }
  2175. /* Free all buffers from the pool */
  2176. static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
  2177. struct mvpp2_bm_pool *bm_pool)
  2178. {
  2179. int i;
  2180. for (i = 0; i < bm_pool->buf_num; i++) {
  2181. /* Allocate buffer back from the buffer manager */
  2182. mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
  2183. }
  2184. bm_pool->buf_num = 0;
  2185. }
  2186. /* Cleanup pool */
  2187. static int mvpp2_bm_pool_destroy(struct udevice *dev,
  2188. struct mvpp2 *priv,
  2189. struct mvpp2_bm_pool *bm_pool)
  2190. {
  2191. u32 val;
  2192. mvpp2_bm_bufs_free(dev, priv, bm_pool);
  2193. if (bm_pool->buf_num) {
  2194. dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
  2195. return 0;
  2196. }
  2197. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2198. val |= MVPP2_BM_STOP_MASK;
  2199. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2200. return 0;
  2201. }
  2202. static int mvpp2_bm_pools_init(struct udevice *dev,
  2203. struct mvpp2 *priv)
  2204. {
  2205. int i, err, size;
  2206. struct mvpp2_bm_pool *bm_pool;
  2207. /* Create all pools with maximum size */
  2208. size = MVPP2_BM_POOL_SIZE_MAX;
  2209. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2210. bm_pool = &priv->bm_pools[i];
  2211. bm_pool->id = i;
  2212. err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
  2213. if (err)
  2214. goto err_unroll_pools;
  2215. mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
  2216. }
  2217. return 0;
  2218. err_unroll_pools:
  2219. dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
  2220. for (i = i - 1; i >= 0; i--)
  2221. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  2222. return err;
  2223. }
  2224. static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
  2225. {
  2226. int i, err;
  2227. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2228. /* Mask BM all interrupts */
  2229. mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
  2230. /* Clear BM cause register */
  2231. mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
  2232. }
  2233. /* Allocate and initialize BM pools */
  2234. priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
  2235. sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
  2236. if (!priv->bm_pools)
  2237. return -ENOMEM;
  2238. err = mvpp2_bm_pools_init(dev, priv);
  2239. if (err < 0)
  2240. return err;
  2241. return 0;
  2242. }
  2243. /* Attach long pool to rxq */
  2244. static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
  2245. int lrxq, int long_pool)
  2246. {
  2247. u32 val, mask;
  2248. int prxq;
  2249. /* Get queue physical ID */
  2250. prxq = port->rxqs[lrxq]->id;
  2251. if (port->priv->hw_version == MVPP21)
  2252. mask = MVPP21_RXQ_POOL_LONG_MASK;
  2253. else
  2254. mask = MVPP22_RXQ_POOL_LONG_MASK;
  2255. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  2256. val &= ~mask;
  2257. val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
  2258. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  2259. }
  2260. /* Set pool number in a BM cookie */
  2261. static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
  2262. {
  2263. u32 bm;
  2264. bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
  2265. bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
  2266. return bm;
  2267. }
  2268. /* Get pool number from a BM cookie */
  2269. static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
  2270. {
  2271. return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
  2272. }
  2273. /* Release buffer to BM */
  2274. static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
  2275. dma_addr_t buf_dma_addr,
  2276. unsigned long buf_phys_addr)
  2277. {
  2278. if (port->priv->hw_version == MVPP22) {
  2279. u32 val = 0;
  2280. if (sizeof(dma_addr_t) == 8)
  2281. val |= upper_32_bits(buf_dma_addr) &
  2282. MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
  2283. if (sizeof(phys_addr_t) == 8)
  2284. val |= (upper_32_bits(buf_phys_addr)
  2285. << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
  2286. MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
  2287. mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
  2288. }
  2289. /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
  2290. * returned in the "cookie" field of the RX
  2291. * descriptor. Instead of storing the virtual address, we
  2292. * store the physical address
  2293. */
  2294. mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
  2295. mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
  2296. }
  2297. /* Refill BM pool */
  2298. static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
  2299. dma_addr_t dma_addr,
  2300. phys_addr_t phys_addr)
  2301. {
  2302. int pool = mvpp2_bm_cookie_pool_get(bm);
  2303. mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
  2304. }
  2305. /* Allocate buffers for the pool */
  2306. static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
  2307. struct mvpp2_bm_pool *bm_pool, int buf_num)
  2308. {
  2309. int i;
  2310. if (buf_num < 0 ||
  2311. (buf_num + bm_pool->buf_num > bm_pool->size)) {
  2312. dev_err(port->phy_dev->dev,
  2313. "cannot allocate %d buffers for pool %d\n", buf_num,
  2314. bm_pool->id);
  2315. return 0;
  2316. }
  2317. for (i = 0; i < buf_num; i++) {
  2318. mvpp2_bm_pool_put(port, bm_pool->id,
  2319. (dma_addr_t)buffer_loc.rx_buffer[i],
  2320. (unsigned long)buffer_loc.rx_buffer[i]);
  2321. }
  2322. /* Update BM driver with number of buffers added to pool */
  2323. bm_pool->buf_num += i;
  2324. return i;
  2325. }
  2326. /* Notify the driver that BM pool is being used as specific type and return the
  2327. * pool pointer on success
  2328. */
  2329. static struct mvpp2_bm_pool *
  2330. mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
  2331. int pkt_size)
  2332. {
  2333. struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
  2334. int num;
  2335. if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
  2336. dev_err(port->phy_dev->dev, "mixing pool types is forbidden\n");
  2337. return NULL;
  2338. }
  2339. if (new_pool->type == MVPP2_BM_FREE)
  2340. new_pool->type = type;
  2341. /* Allocate buffers in case BM pool is used as long pool, but packet
  2342. * size doesn't match MTU or BM pool hasn't being used yet
  2343. */
  2344. if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
  2345. (new_pool->pkt_size == 0)) {
  2346. int pkts_num;
  2347. /* Set default buffer number or free all the buffers in case
  2348. * the pool is not empty
  2349. */
  2350. pkts_num = new_pool->buf_num;
  2351. if (pkts_num == 0)
  2352. pkts_num = type == MVPP2_BM_SWF_LONG ?
  2353. MVPP2_BM_LONG_BUF_NUM :
  2354. MVPP2_BM_SHORT_BUF_NUM;
  2355. else
  2356. mvpp2_bm_bufs_free(NULL,
  2357. port->priv, new_pool);
  2358. new_pool->pkt_size = pkt_size;
  2359. /* Allocate buffers for this pool */
  2360. num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
  2361. if (num != pkts_num) {
  2362. dev_err(port->phy_dev->dev,
  2363. "pool %d: %d of %d allocated\n", new_pool->id,
  2364. num, pkts_num);
  2365. return NULL;
  2366. }
  2367. }
  2368. return new_pool;
  2369. }
  2370. /* Initialize pools for swf */
  2371. static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
  2372. {
  2373. int rxq;
  2374. if (!port->pool_long) {
  2375. port->pool_long =
  2376. mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
  2377. MVPP2_BM_SWF_LONG,
  2378. port->pkt_size);
  2379. if (!port->pool_long)
  2380. return -ENOMEM;
  2381. port->pool_long->port_map |= (1 << port->id);
  2382. for (rxq = 0; rxq < rxq_number; rxq++)
  2383. mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
  2384. }
  2385. return 0;
  2386. }
  2387. /* Port configuration routines */
  2388. static void mvpp2_port_mii_set(struct mvpp2_port *port)
  2389. {
  2390. u32 val;
  2391. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2392. switch (port->phy_interface) {
  2393. case PHY_INTERFACE_MODE_SGMII:
  2394. case PHY_INTERFACE_MODE_SGMII_2500:
  2395. val |= MVPP2_GMAC_INBAND_AN_MASK;
  2396. break;
  2397. case PHY_INTERFACE_MODE_1000BASEX:
  2398. case PHY_INTERFACE_MODE_2500BASEX:
  2399. val &= ~MVPP2_GMAC_INBAND_AN_MASK;
  2400. break;
  2401. case PHY_INTERFACE_MODE_RGMII:
  2402. case PHY_INTERFACE_MODE_RGMII_ID:
  2403. val |= MVPP2_GMAC_PORT_RGMII_MASK;
  2404. default:
  2405. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2406. }
  2407. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2408. }
  2409. static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
  2410. {
  2411. u32 val;
  2412. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2413. val |= MVPP2_GMAC_FC_ADV_EN;
  2414. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2415. }
  2416. static void mvpp2_port_enable(struct mvpp2_port *port)
  2417. {
  2418. u32 val;
  2419. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2420. val |= MVPP2_GMAC_PORT_EN_MASK;
  2421. val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
  2422. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2423. }
  2424. static void mvpp2_port_disable(struct mvpp2_port *port)
  2425. {
  2426. u32 val;
  2427. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2428. val &= ~(MVPP2_GMAC_PORT_EN_MASK);
  2429. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2430. }
  2431. /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
  2432. static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
  2433. {
  2434. u32 val;
  2435. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
  2436. ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2437. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2438. }
  2439. /* Configure loopback port */
  2440. static void mvpp2_port_loopback_set(struct mvpp2_port *port)
  2441. {
  2442. u32 val;
  2443. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2444. if (port->speed == 1000)
  2445. val |= MVPP2_GMAC_GMII_LB_EN_MASK;
  2446. else
  2447. val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
  2448. if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
  2449. port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
  2450. port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
  2451. port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
  2452. val |= MVPP2_GMAC_PCS_LB_EN_MASK;
  2453. else
  2454. val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
  2455. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2456. }
  2457. static void mvpp2_port_reset(struct mvpp2_port *port)
  2458. {
  2459. u32 val;
  2460. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2461. ~MVPP2_GMAC_PORT_RESET_MASK;
  2462. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2463. while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2464. MVPP2_GMAC_PORT_RESET_MASK)
  2465. continue;
  2466. }
  2467. /* Change maximum receive size of the port */
  2468. static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
  2469. {
  2470. u32 val;
  2471. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2472. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2473. val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
  2474. MVPP2_GMAC_MAX_RX_SIZE_OFFS);
  2475. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2476. }
  2477. /* PPv2.2 GoP/GMAC config */
  2478. /* Set the MAC to reset or exit from reset */
  2479. static int gop_gmac_reset(struct mvpp2_port *port, int reset)
  2480. {
  2481. u32 val;
  2482. /* read - modify - write */
  2483. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2484. if (reset)
  2485. val |= MVPP2_GMAC_PORT_RESET_MASK;
  2486. else
  2487. val &= ~MVPP2_GMAC_PORT_RESET_MASK;
  2488. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2489. return 0;
  2490. }
  2491. /*
  2492. * gop_gpcs_mode_cfg
  2493. *
  2494. * Configure port to working with Gig PCS or don't.
  2495. */
  2496. static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
  2497. {
  2498. u32 val;
  2499. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2500. if (en)
  2501. val |= MVPP2_GMAC_PCS_ENABLE_MASK;
  2502. else
  2503. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2504. /* enable / disable PCS on this port */
  2505. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2506. return 0;
  2507. }
  2508. static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
  2509. {
  2510. u32 val;
  2511. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2512. if (en)
  2513. val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2514. else
  2515. val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2516. /* enable / disable PCS on this port */
  2517. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2518. return 0;
  2519. }
  2520. static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
  2521. {
  2522. u32 val, thresh;
  2523. /*
  2524. * Configure minimal level of the Tx FIFO before the lower part
  2525. * starts to read a packet
  2526. */
  2527. thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
  2528. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2529. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2530. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2531. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2532. /* Disable bypass of sync module */
  2533. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2534. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2535. /* configure DP clock select according to mode */
  2536. val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2537. /* configure QSGMII bypass according to mode */
  2538. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2539. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2540. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2541. /*
  2542. * Configure GIG MAC to SGMII mode connected to a fiber
  2543. * transceiver
  2544. */
  2545. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2546. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2547. /* configure AN 0x9268 */
  2548. val = MVPP2_GMAC_EN_PCS_AN |
  2549. MVPP2_GMAC_AN_BYPASS_EN |
  2550. MVPP2_GMAC_CONFIG_MII_SPEED |
  2551. MVPP2_GMAC_CONFIG_GMII_SPEED |
  2552. MVPP2_GMAC_FC_ADV_EN |
  2553. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  2554. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2555. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2556. }
  2557. static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
  2558. {
  2559. u32 val, thresh;
  2560. /*
  2561. * Configure minimal level of the Tx FIFO before the lower part
  2562. * starts to read a packet
  2563. */
  2564. thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
  2565. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2566. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2567. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2568. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2569. /* Disable bypass of sync module */
  2570. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2571. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2572. /* configure DP clock select according to mode */
  2573. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2574. /* configure QSGMII bypass according to mode */
  2575. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2576. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2577. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2578. /* configure GIG MAC to SGMII mode */
  2579. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2580. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2581. /* configure AN */
  2582. val = MVPP2_GMAC_EN_PCS_AN |
  2583. MVPP2_GMAC_AN_BYPASS_EN |
  2584. MVPP2_GMAC_AN_SPEED_EN |
  2585. MVPP2_GMAC_EN_FC_AN |
  2586. MVPP2_GMAC_AN_DUPLEX_EN |
  2587. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2588. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2589. }
  2590. static void gop_gmac_2500basex_cfg(struct mvpp2_port *port)
  2591. {
  2592. u32 val, thresh;
  2593. /*
  2594. * Configure minimal level of the Tx FIFO before the lower part
  2595. * starts to read a packet
  2596. */
  2597. thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
  2598. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2599. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2600. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2601. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2602. /* Disable bypass of sync module */
  2603. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2604. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2605. /* configure DP clock select according to mode */
  2606. val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2607. /* configure QSGMII bypass according to mode */
  2608. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2609. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2610. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2611. /*
  2612. * Configure GIG MAC to 2500Base-X mode connected to a fiber
  2613. * transceiver
  2614. */
  2615. val |= MVPP2_GMAC_PORT_TYPE_MASK;
  2616. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2617. /* In 2500BaseX mode, we can't negotiate speed
  2618. * and we do not want InBand autoneg
  2619. * bypass enabled (link interrupt storm risk
  2620. * otherwise).
  2621. */
  2622. val = MVPP2_GMAC_AN_BYPASS_EN |
  2623. MVPP2_GMAC_EN_PCS_AN |
  2624. MVPP2_GMAC_CONFIG_GMII_SPEED |
  2625. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  2626. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2627. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2628. }
  2629. static void gop_gmac_1000basex_cfg(struct mvpp2_port *port)
  2630. {
  2631. u32 val, thresh;
  2632. /*
  2633. * Configure minimal level of the Tx FIFO before the lower part
  2634. * starts to read a packet
  2635. */
  2636. thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
  2637. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2638. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2639. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2640. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2641. /* Disable bypass of sync module */
  2642. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2643. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2644. /* configure DP clock select according to mode */
  2645. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2646. /* configure QSGMII bypass according to mode */
  2647. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2648. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2649. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2650. /* configure GIG MAC to 1000BASEX mode */
  2651. val |= MVPP2_GMAC_PORT_TYPE_MASK;
  2652. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2653. /* In 1000BaseX mode, we can't negotiate speed (it's
  2654. * only 1000), and we do not want InBand autoneg
  2655. * bypass enabled (link interrupt storm risk
  2656. * otherwise).
  2657. */
  2658. val = MVPP2_GMAC_AN_BYPASS_EN |
  2659. MVPP2_GMAC_EN_PCS_AN |
  2660. MVPP2_GMAC_CONFIG_GMII_SPEED |
  2661. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  2662. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2663. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2664. }
  2665. static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
  2666. {
  2667. u32 val, thresh;
  2668. /*
  2669. * Configure minimal level of the Tx FIFO before the lower part
  2670. * starts to read a packet
  2671. */
  2672. thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
  2673. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2674. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2675. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2676. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2677. /* Disable bypass of sync module */
  2678. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2679. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2680. /* configure DP clock select according to mode */
  2681. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2682. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2683. val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
  2684. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2685. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2686. /* configure GIG MAC to SGMII mode */
  2687. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2688. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2689. /* configure AN 0xb8e8 */
  2690. val = MVPP2_GMAC_AN_BYPASS_EN |
  2691. MVPP2_GMAC_AN_SPEED_EN |
  2692. MVPP2_GMAC_EN_FC_AN |
  2693. MVPP2_GMAC_AN_DUPLEX_EN |
  2694. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2695. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2696. }
  2697. /* Set the internal mux's to the required MAC in the GOP */
  2698. static int gop_gmac_mode_cfg(struct mvpp2_port *port)
  2699. {
  2700. u32 val;
  2701. /* Set TX FIFO thresholds */
  2702. switch (port->phy_interface) {
  2703. case PHY_INTERFACE_MODE_SGMII:
  2704. gop_gmac_sgmii_cfg(port);
  2705. break;
  2706. case PHY_INTERFACE_MODE_SGMII_2500:
  2707. gop_gmac_sgmii2_5_cfg(port);
  2708. break;
  2709. case PHY_INTERFACE_MODE_1000BASEX:
  2710. gop_gmac_1000basex_cfg(port);
  2711. break;
  2712. case PHY_INTERFACE_MODE_2500BASEX:
  2713. gop_gmac_2500basex_cfg(port);
  2714. break;
  2715. case PHY_INTERFACE_MODE_RGMII:
  2716. case PHY_INTERFACE_MODE_RGMII_ID:
  2717. gop_gmac_rgmii_cfg(port);
  2718. break;
  2719. default:
  2720. return -1;
  2721. }
  2722. /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
  2723. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2724. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2725. val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
  2726. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2727. /* PeriodicXonEn disable */
  2728. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2729. val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2730. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2731. return 0;
  2732. }
  2733. static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
  2734. {
  2735. u32 val;
  2736. /* relevant only for MAC0 (XLG0 and GMAC0) */
  2737. if (port->gop_id > 0)
  2738. return;
  2739. /* configure 1Gig MAC mode */
  2740. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2741. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2742. val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
  2743. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2744. }
  2745. static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
  2746. {
  2747. u32 val;
  2748. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2749. if (reset)
  2750. val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
  2751. else
  2752. val |= MVPP2_GMAC_SGMII_MODE_MASK;
  2753. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2754. return 0;
  2755. }
  2756. static int gop_mpcs_mode(struct mvpp2_port *port)
  2757. {
  2758. u32 val;
  2759. /* configure PCS40G COMMON CONTROL */
  2760. val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
  2761. PCS40G_COMMON_CONTROL);
  2762. val &= ~FORWARD_ERROR_CORRECTION_MASK;
  2763. writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
  2764. PCS40G_COMMON_CONTROL);
  2765. /* configure PCS CLOCK RESET */
  2766. val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
  2767. PCS_CLOCK_RESET);
  2768. val &= ~CLK_DIVISION_RATIO_MASK;
  2769. val |= 1 << CLK_DIVISION_RATIO_OFFS;
  2770. writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
  2771. PCS_CLOCK_RESET);
  2772. val &= ~CLK_DIV_PHASE_SET_MASK;
  2773. val |= MAC_CLK_RESET_MASK;
  2774. val |= RX_SD_CLK_RESET_MASK;
  2775. val |= TX_SD_CLK_RESET_MASK;
  2776. writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
  2777. PCS_CLOCK_RESET);
  2778. return 0;
  2779. }
  2780. /* Set the internal mux's to the required MAC in the GOP */
  2781. static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
  2782. {
  2783. u32 val;
  2784. /* configure 10G MAC mode */
  2785. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2786. val |= MVPP22_XLG_RX_FC_EN;
  2787. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2788. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2789. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2790. val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
  2791. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2792. /* read - modify - write */
  2793. val = readl(port->base + MVPP22_XLG_CTRL4_REG);
  2794. val &= ~MVPP22_XLG_MODE_DMA_1G;
  2795. val |= MVPP22_XLG_FORWARD_PFC_EN;
  2796. val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
  2797. val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
  2798. writel(val, port->base + MVPP22_XLG_CTRL4_REG);
  2799. /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
  2800. val = readl(port->base + MVPP22_XLG_CTRL1_REG);
  2801. val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
  2802. val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
  2803. writel(val, port->base + MVPP22_XLG_CTRL1_REG);
  2804. /* unmask link change interrupt */
  2805. val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2806. val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
  2807. val |= 1; /* unmask summary bit */
  2808. writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2809. return 0;
  2810. }
  2811. /* Set the MAC to reset or exit from reset */
  2812. static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
  2813. {
  2814. u32 val;
  2815. /* read - modify - write */
  2816. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2817. if (reset)
  2818. val &= ~MVPP22_XLG_MAC_RESETN;
  2819. else
  2820. val |= MVPP22_XLG_MAC_RESETN;
  2821. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2822. return 0;
  2823. }
  2824. /*
  2825. * gop_port_init
  2826. *
  2827. * Init physical port. Configures the port mode and all it's elements
  2828. * accordingly.
  2829. * Does not verify that the selected mode/port number is valid at the
  2830. * core level.
  2831. */
  2832. static int gop_port_init(struct mvpp2_port *port)
  2833. {
  2834. int mac_num = port->gop_id;
  2835. int num_of_act_lanes;
  2836. if (mac_num >= MVPP22_GOP_MAC_NUM) {
  2837. log_err("illegal port number %d", mac_num);
  2838. return -1;
  2839. }
  2840. switch (port->phy_interface) {
  2841. case PHY_INTERFACE_MODE_RGMII:
  2842. case PHY_INTERFACE_MODE_RGMII_ID:
  2843. gop_gmac_reset(port, 1);
  2844. /* configure PCS */
  2845. gop_gpcs_mode_cfg(port, 0);
  2846. gop_bypass_clk_cfg(port, 1);
  2847. /* configure MAC */
  2848. gop_gmac_mode_cfg(port);
  2849. /* pcs unreset */
  2850. gop_gpcs_reset(port, 0);
  2851. /* mac unreset */
  2852. gop_gmac_reset(port, 0);
  2853. break;
  2854. case PHY_INTERFACE_MODE_SGMII:
  2855. case PHY_INTERFACE_MODE_SGMII_2500:
  2856. case PHY_INTERFACE_MODE_1000BASEX:
  2857. case PHY_INTERFACE_MODE_2500BASEX:
  2858. /* configure PCS */
  2859. gop_gpcs_mode_cfg(port, 1);
  2860. /* configure MAC */
  2861. gop_gmac_mode_cfg(port);
  2862. /* select proper Mac mode */
  2863. gop_xlg_2_gig_mac_cfg(port);
  2864. /* pcs unreset */
  2865. gop_gpcs_reset(port, 0);
  2866. /* mac unreset */
  2867. gop_gmac_reset(port, 0);
  2868. break;
  2869. case PHY_INTERFACE_MODE_SFI:
  2870. num_of_act_lanes = 2;
  2871. mac_num = 0;
  2872. /* configure PCS */
  2873. gop_mpcs_mode(port);
  2874. /* configure MAC */
  2875. gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
  2876. /* mac unreset */
  2877. gop_xlg_mac_reset(port, 0);
  2878. break;
  2879. default:
  2880. log_err("Requested port mode (%d) not supported\n",
  2881. port->phy_interface);
  2882. return -1;
  2883. }
  2884. return 0;
  2885. }
  2886. static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
  2887. {
  2888. u32 val;
  2889. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2890. if (enable) {
  2891. /* Enable port and MIB counters update */
  2892. val |= MVPP22_XLG_PORT_EN;
  2893. val &= ~MVPP22_XLG_MIBCNT_DIS;
  2894. } else {
  2895. /* Disable port */
  2896. val &= ~MVPP22_XLG_PORT_EN;
  2897. }
  2898. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2899. }
  2900. static void gop_port_enable(struct mvpp2_port *port, int enable)
  2901. {
  2902. switch (port->phy_interface) {
  2903. case PHY_INTERFACE_MODE_RGMII:
  2904. case PHY_INTERFACE_MODE_RGMII_ID:
  2905. case PHY_INTERFACE_MODE_SGMII:
  2906. case PHY_INTERFACE_MODE_SGMII_2500:
  2907. case PHY_INTERFACE_MODE_1000BASEX:
  2908. case PHY_INTERFACE_MODE_2500BASEX:
  2909. if (enable)
  2910. mvpp2_port_enable(port);
  2911. else
  2912. mvpp2_port_disable(port);
  2913. break;
  2914. case PHY_INTERFACE_MODE_SFI:
  2915. gop_xlg_mac_port_enable(port, enable);
  2916. break;
  2917. default:
  2918. log_err("%s: Wrong port mode (%d)\n", __func__,
  2919. port->phy_interface);
  2920. return;
  2921. }
  2922. }
  2923. /* RFU1 functions */
  2924. static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
  2925. {
  2926. return readl(priv->rfu1_base + offset);
  2927. }
  2928. static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
  2929. {
  2930. writel(data, priv->rfu1_base + offset);
  2931. }
  2932. static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
  2933. {
  2934. u32 val = 0;
  2935. if (gop_id == 2) {
  2936. if (phy_type == PHY_INTERFACE_MODE_SGMII ||
  2937. phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
  2938. phy_type == PHY_INTERFACE_MODE_1000BASEX ||
  2939. phy_type == PHY_INTERFACE_MODE_2500BASEX)
  2940. val |= MV_NETC_GE_MAC2_SGMII;
  2941. else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
  2942. phy_type == PHY_INTERFACE_MODE_RGMII_ID)
  2943. val |= MV_NETC_GE_MAC2_RGMII;
  2944. }
  2945. if (gop_id == 3) {
  2946. if (phy_type == PHY_INTERFACE_MODE_SGMII ||
  2947. phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
  2948. phy_type == PHY_INTERFACE_MODE_1000BASEX ||
  2949. phy_type == PHY_INTERFACE_MODE_2500BASEX)
  2950. val |= MV_NETC_GE_MAC3_SGMII;
  2951. else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
  2952. phy_type == PHY_INTERFACE_MODE_RGMII_ID)
  2953. val |= MV_NETC_GE_MAC3_RGMII;
  2954. }
  2955. return val;
  2956. }
  2957. static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
  2958. {
  2959. u32 reg;
  2960. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  2961. reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
  2962. val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
  2963. val &= NETC_PORTS_ACTIVE_MASK(gop_id);
  2964. reg |= val;
  2965. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  2966. }
  2967. static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
  2968. {
  2969. u32 reg;
  2970. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  2971. reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
  2972. val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
  2973. val &= NETC_GBE_PORT1_MII_MODE_MASK;
  2974. reg |= val;
  2975. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  2976. }
  2977. static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
  2978. {
  2979. u32 reg;
  2980. reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
  2981. reg &= ~NETC_GOP_SOFT_RESET_MASK;
  2982. val <<= NETC_GOP_SOFT_RESET_OFFS;
  2983. val &= NETC_GOP_SOFT_RESET_MASK;
  2984. reg |= val;
  2985. gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
  2986. }
  2987. static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
  2988. {
  2989. u32 reg;
  2990. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2991. reg &= ~NETC_CLK_DIV_PHASE_MASK;
  2992. val <<= NETC_CLK_DIV_PHASE_OFFS;
  2993. val &= NETC_CLK_DIV_PHASE_MASK;
  2994. reg |= val;
  2995. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2996. }
  2997. static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
  2998. {
  2999. u32 reg;
  3000. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  3001. reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
  3002. val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
  3003. val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
  3004. reg |= val;
  3005. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  3006. }
  3007. static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
  3008. u32 val)
  3009. {
  3010. u32 reg, mask, offset;
  3011. if (gop_id == 2) {
  3012. mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
  3013. offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
  3014. } else {
  3015. mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
  3016. offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
  3017. }
  3018. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  3019. reg &= ~mask;
  3020. val <<= offset;
  3021. val &= mask;
  3022. reg |= val;
  3023. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  3024. }
  3025. static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
  3026. {
  3027. u32 reg;
  3028. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  3029. reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
  3030. val <<= NETC_BUS_WIDTH_SELECT_OFFS;
  3031. val &= NETC_BUS_WIDTH_SELECT_MASK;
  3032. reg |= val;
  3033. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  3034. }
  3035. static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
  3036. {
  3037. u32 reg;
  3038. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  3039. reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
  3040. val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
  3041. val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
  3042. reg |= val;
  3043. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  3044. }
  3045. static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
  3046. enum mv_netc_phase phase)
  3047. {
  3048. switch (phase) {
  3049. case MV_NETC_FIRST_PHASE:
  3050. /* Set Bus Width to HB mode = 1 */
  3051. gop_netc_bus_width_select(priv, 1);
  3052. /* Select RGMII mode */
  3053. gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
  3054. break;
  3055. case MV_NETC_SECOND_PHASE:
  3056. /* De-assert the relevant port HB reset */
  3057. gop_netc_port_rf_reset(priv, gop_id, 1);
  3058. break;
  3059. }
  3060. }
  3061. static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
  3062. enum mv_netc_phase phase)
  3063. {
  3064. switch (phase) {
  3065. case MV_NETC_FIRST_PHASE:
  3066. /* Set Bus Width to HB mode = 1 */
  3067. gop_netc_bus_width_select(priv, 1);
  3068. /* Select SGMII mode */
  3069. if (gop_id >= 1) {
  3070. gop_netc_gbe_sgmii_mode_select(priv, gop_id,
  3071. MV_NETC_GBE_SGMII);
  3072. }
  3073. /* Configure the sample stages */
  3074. gop_netc_sample_stages_timing(priv, 0);
  3075. /* Configure the ComPhy Selector */
  3076. /* gop_netc_com_phy_selector_config(netComplex); */
  3077. break;
  3078. case MV_NETC_SECOND_PHASE:
  3079. /* De-assert the relevant port HB reset */
  3080. gop_netc_port_rf_reset(priv, gop_id, 1);
  3081. break;
  3082. }
  3083. }
  3084. static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
  3085. {
  3086. u32 c = priv->netc_config;
  3087. if (c & MV_NETC_GE_MAC2_SGMII)
  3088. gop_netc_mac_to_sgmii(priv, 2, phase);
  3089. else if (c & MV_NETC_GE_MAC2_RGMII)
  3090. gop_netc_mac_to_xgmii(priv, 2, phase);
  3091. if (c & MV_NETC_GE_MAC3_SGMII) {
  3092. gop_netc_mac_to_sgmii(priv, 3, phase);
  3093. } else {
  3094. gop_netc_mac_to_xgmii(priv, 3, phase);
  3095. if (c & MV_NETC_GE_MAC3_RGMII)
  3096. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
  3097. else
  3098. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
  3099. }
  3100. /* Activate gop ports 0, 2, 3 */
  3101. gop_netc_active_port(priv, 0, 1);
  3102. gop_netc_active_port(priv, 2, 1);
  3103. gop_netc_active_port(priv, 3, 1);
  3104. if (phase == MV_NETC_SECOND_PHASE) {
  3105. /* Enable the GOP internal clock logic */
  3106. gop_netc_gop_clock_logic_set(priv, 1);
  3107. /* De-assert GOP unit reset */
  3108. gop_netc_gop_reset(priv, 1);
  3109. }
  3110. return 0;
  3111. }
  3112. /* Set defaults to the MVPP2 port */
  3113. static void mvpp2_defaults_set(struct mvpp2_port *port)
  3114. {
  3115. int tx_port_num, val, queue, ptxq, lrxq;
  3116. if (port->priv->hw_version == MVPP21) {
  3117. /* Configure port to loopback if needed */
  3118. if (port->flags & MVPP2_F_LOOPBACK)
  3119. mvpp2_port_loopback_set(port);
  3120. /* Update TX FIFO MIN Threshold */
  3121. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3122. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  3123. /* Min. TX threshold must be less than minimal packet length */
  3124. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
  3125. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3126. }
  3127. /* Disable Legacy WRR, Disable EJP, Release from reset */
  3128. tx_port_num = mvpp2_egress_port(port);
  3129. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
  3130. tx_port_num);
  3131. mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
  3132. /* Close bandwidth for all queues */
  3133. for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
  3134. ptxq = mvpp2_txq_phys(port->id, queue);
  3135. mvpp2_write(port->priv,
  3136. MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
  3137. }
  3138. /* Set refill period to 1 usec, refill tokens
  3139. * and bucket size to maximum
  3140. */
  3141. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
  3142. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
  3143. val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
  3144. val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
  3145. val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
  3146. mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
  3147. val = MVPP2_TXP_TOKEN_SIZE_MAX;
  3148. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3149. /* Set MaximumLowLatencyPacketSize value to 256 */
  3150. mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
  3151. MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
  3152. MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
  3153. /* Enable Rx cache snoop */
  3154. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3155. queue = port->rxqs[lrxq]->id;
  3156. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3157. val |= MVPP2_SNOOP_PKT_SIZE_MASK |
  3158. MVPP2_SNOOP_BUF_HDR_MASK;
  3159. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3160. }
  3161. }
  3162. /* Enable/disable receiving packets */
  3163. static void mvpp2_ingress_enable(struct mvpp2_port *port)
  3164. {
  3165. u32 val;
  3166. int lrxq, queue;
  3167. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3168. queue = port->rxqs[lrxq]->id;
  3169. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3170. val &= ~MVPP2_RXQ_DISABLE_MASK;
  3171. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3172. }
  3173. }
  3174. static void mvpp2_ingress_disable(struct mvpp2_port *port)
  3175. {
  3176. u32 val;
  3177. int lrxq, queue;
  3178. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3179. queue = port->rxqs[lrxq]->id;
  3180. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3181. val |= MVPP2_RXQ_DISABLE_MASK;
  3182. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3183. }
  3184. }
  3185. /* Enable transmit via physical egress queue
  3186. * - HW starts take descriptors from DRAM
  3187. */
  3188. static void mvpp2_egress_enable(struct mvpp2_port *port)
  3189. {
  3190. u32 qmap;
  3191. int queue;
  3192. int tx_port_num = mvpp2_egress_port(port);
  3193. /* Enable all initialized TXs. */
  3194. qmap = 0;
  3195. for (queue = 0; queue < txq_number; queue++) {
  3196. struct mvpp2_tx_queue *txq = port->txqs[queue];
  3197. if (txq->descs != NULL)
  3198. qmap |= (1 << queue);
  3199. }
  3200. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3201. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
  3202. }
  3203. /* Disable transmit via physical egress queue
  3204. * - HW doesn't take descriptors from DRAM
  3205. */
  3206. static void mvpp2_egress_disable(struct mvpp2_port *port)
  3207. {
  3208. u32 reg_data;
  3209. int delay;
  3210. int tx_port_num = mvpp2_egress_port(port);
  3211. /* Issue stop command for active channels only */
  3212. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3213. reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
  3214. MVPP2_TXP_SCHED_ENQ_MASK;
  3215. if (reg_data != 0)
  3216. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
  3217. (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
  3218. /* Wait for all Tx activity to terminate. */
  3219. delay = 0;
  3220. do {
  3221. if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
  3222. dev_warn(port->phy_dev->dev,
  3223. "Tx stop timed out, status=0x%08x\n",
  3224. reg_data);
  3225. break;
  3226. }
  3227. mdelay(1);
  3228. delay++;
  3229. /* Check port TX Command register that all
  3230. * Tx queues are stopped
  3231. */
  3232. reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
  3233. } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
  3234. }
  3235. /* Rx descriptors helper methods */
  3236. /* Get number of Rx descriptors occupied by received packets */
  3237. static inline int
  3238. mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
  3239. {
  3240. u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
  3241. return val & MVPP2_RXQ_OCCUPIED_MASK;
  3242. }
  3243. /* Update Rx queue status with the number of occupied and available
  3244. * Rx descriptor slots.
  3245. */
  3246. static inline void
  3247. mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
  3248. int used_count, int free_count)
  3249. {
  3250. /* Decrement the number of used descriptors and increment count
  3251. * increment the number of free descriptors.
  3252. */
  3253. u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
  3254. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
  3255. }
  3256. /* Get pointer to next RX descriptor to be processed by SW */
  3257. static inline struct mvpp2_rx_desc *
  3258. mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
  3259. {
  3260. int rx_desc = rxq->next_desc_to_proc;
  3261. rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
  3262. prefetch(rxq->descs + rxq->next_desc_to_proc);
  3263. return rxq->descs + rx_desc;
  3264. }
  3265. /* Set rx queue offset */
  3266. static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
  3267. int prxq, int offset)
  3268. {
  3269. u32 val;
  3270. /* Convert offset from bytes to units of 32 bytes */
  3271. offset = offset >> 5;
  3272. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  3273. val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
  3274. /* Offset is in */
  3275. val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
  3276. MVPP2_RXQ_PACKET_OFFSET_MASK);
  3277. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  3278. }
  3279. /* Obtain BM cookie information from descriptor */
  3280. static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
  3281. struct mvpp2_rx_desc *rx_desc)
  3282. {
  3283. int cpu = smp_processor_id();
  3284. int pool;
  3285. pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
  3286. MVPP2_RXD_BM_POOL_ID_MASK) >>
  3287. MVPP2_RXD_BM_POOL_ID_OFFS;
  3288. return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
  3289. ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
  3290. }
  3291. /* Tx descriptors helper methods */
  3292. /* Get number of Tx descriptors waiting to be transmitted by HW */
  3293. static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
  3294. struct mvpp2_tx_queue *txq)
  3295. {
  3296. u32 val;
  3297. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3298. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3299. return val & MVPP2_TXQ_PENDING_MASK;
  3300. }
  3301. /* Get pointer to next Tx descriptor to be processed (send) by HW */
  3302. static struct mvpp2_tx_desc *
  3303. mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
  3304. {
  3305. int tx_desc = txq->next_desc_to_proc;
  3306. txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
  3307. return txq->descs + tx_desc;
  3308. }
  3309. /* Update HW with number of aggregated Tx descriptors to be sent */
  3310. static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
  3311. {
  3312. /* aggregated access - relevant TXQ number is written in TX desc */
  3313. mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
  3314. }
  3315. /* Get number of sent descriptors and decrement counter.
  3316. * The number of sent descriptors is returned.
  3317. * Per-CPU access
  3318. */
  3319. static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
  3320. struct mvpp2_tx_queue *txq)
  3321. {
  3322. u32 val;
  3323. /* Reading status reg resets transmitted descriptor counter */
  3324. val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
  3325. return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
  3326. MVPP2_TRANSMITTED_COUNT_OFFSET;
  3327. }
  3328. static void mvpp2_txq_sent_counter_clear(void *arg)
  3329. {
  3330. struct mvpp2_port *port = arg;
  3331. int queue;
  3332. for (queue = 0; queue < txq_number; queue++) {
  3333. int id = port->txqs[queue]->id;
  3334. mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
  3335. }
  3336. }
  3337. /* Set max sizes for Tx queues */
  3338. static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
  3339. {
  3340. u32 val, size, mtu;
  3341. int txq, tx_port_num;
  3342. mtu = port->pkt_size * 8;
  3343. if (mtu > MVPP2_TXP_MTU_MAX)
  3344. mtu = MVPP2_TXP_MTU_MAX;
  3345. /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
  3346. mtu = 3 * mtu;
  3347. /* Indirect access to registers */
  3348. tx_port_num = mvpp2_egress_port(port);
  3349. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3350. /* Set MTU */
  3351. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
  3352. val &= ~MVPP2_TXP_MTU_MAX;
  3353. val |= mtu;
  3354. mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
  3355. /* TXP token size and all TXQs token size must be larger that MTU */
  3356. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
  3357. size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
  3358. if (size < mtu) {
  3359. size = mtu;
  3360. val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
  3361. val |= size;
  3362. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3363. }
  3364. for (txq = 0; txq < txq_number; txq++) {
  3365. val = mvpp2_read(port->priv,
  3366. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
  3367. size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
  3368. if (size < mtu) {
  3369. size = mtu;
  3370. val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
  3371. val |= size;
  3372. mvpp2_write(port->priv,
  3373. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
  3374. val);
  3375. }
  3376. }
  3377. }
  3378. /* Free Tx queue skbuffs */
  3379. static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
  3380. struct mvpp2_tx_queue *txq,
  3381. struct mvpp2_txq_pcpu *txq_pcpu, int num)
  3382. {
  3383. int i;
  3384. for (i = 0; i < num; i++)
  3385. mvpp2_txq_inc_get(txq_pcpu);
  3386. }
  3387. static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
  3388. u32 cause)
  3389. {
  3390. int queue = fls(cause) - 1;
  3391. return port->rxqs[queue];
  3392. }
  3393. static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
  3394. u32 cause)
  3395. {
  3396. int queue = fls(cause) - 1;
  3397. return port->txqs[queue];
  3398. }
  3399. /* Rx/Tx queue initialization/cleanup methods */
  3400. /* Allocate and initialize descriptors for aggr TXQ */
  3401. static int mvpp2_aggr_txq_init(struct udevice *dev,
  3402. struct mvpp2_tx_queue *aggr_txq,
  3403. int desc_num, int cpu,
  3404. struct mvpp2 *priv)
  3405. {
  3406. u32 txq_dma;
  3407. /* Allocate memory for TX descriptors */
  3408. aggr_txq->descs = buffer_loc.aggr_tx_descs;
  3409. aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
  3410. if (!aggr_txq->descs)
  3411. return -ENOMEM;
  3412. /* Make sure descriptor address is cache line size aligned */
  3413. BUG_ON(aggr_txq->descs !=
  3414. PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3415. aggr_txq->last_desc = aggr_txq->size - 1;
  3416. /* Aggr TXQ no reset WA */
  3417. aggr_txq->next_desc_to_proc = mvpp2_read(priv,
  3418. MVPP2_AGGR_TXQ_INDEX_REG(cpu));
  3419. /* Set Tx descriptors queue starting address indirect
  3420. * access
  3421. */
  3422. if (priv->hw_version == MVPP21)
  3423. txq_dma = aggr_txq->descs_dma;
  3424. else
  3425. txq_dma = aggr_txq->descs_dma >>
  3426. MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
  3427. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
  3428. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
  3429. return 0;
  3430. }
  3431. /* Create a specified Rx queue */
  3432. static int mvpp2_rxq_init(struct mvpp2_port *port,
  3433. struct mvpp2_rx_queue *rxq)
  3434. {
  3435. u32 rxq_dma;
  3436. rxq->size = port->rx_ring_size;
  3437. /* Allocate memory for RX descriptors */
  3438. rxq->descs = buffer_loc.rx_descs;
  3439. rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
  3440. if (!rxq->descs)
  3441. return -ENOMEM;
  3442. BUG_ON(rxq->descs !=
  3443. PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3444. rxq->last_desc = rxq->size - 1;
  3445. /* Zero occupied and non-occupied counters - direct access */
  3446. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3447. /* Set Rx descriptors queue starting address - indirect access */
  3448. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3449. if (port->priv->hw_version == MVPP21)
  3450. rxq_dma = rxq->descs_dma;
  3451. else
  3452. rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
  3453. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
  3454. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
  3455. mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
  3456. /* Set Offset */
  3457. mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
  3458. /* Add number of descriptors ready for receiving packets */
  3459. mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
  3460. return 0;
  3461. }
  3462. /* Push packets received by the RXQ to BM pool */
  3463. static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
  3464. struct mvpp2_rx_queue *rxq)
  3465. {
  3466. int rx_received, i;
  3467. rx_received = mvpp2_rxq_received(port, rxq->id);
  3468. if (!rx_received)
  3469. return;
  3470. for (i = 0; i < rx_received; i++) {
  3471. struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
  3472. u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
  3473. mvpp2_pool_refill(port, bm,
  3474. mvpp2_rxdesc_dma_addr_get(port, rx_desc),
  3475. mvpp2_rxdesc_cookie_get(port, rx_desc));
  3476. }
  3477. mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
  3478. }
  3479. /* Cleanup Rx queue */
  3480. static void mvpp2_rxq_deinit(struct mvpp2_port *port,
  3481. struct mvpp2_rx_queue *rxq)
  3482. {
  3483. mvpp2_rxq_drop_pkts(port, rxq);
  3484. rxq->descs = NULL;
  3485. rxq->last_desc = 0;
  3486. rxq->next_desc_to_proc = 0;
  3487. rxq->descs_dma = 0;
  3488. /* Clear Rx descriptors queue starting address and size;
  3489. * free descriptor number
  3490. */
  3491. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3492. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3493. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
  3494. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
  3495. }
  3496. /* Create and initialize a Tx queue */
  3497. static int mvpp2_txq_init(struct mvpp2_port *port,
  3498. struct mvpp2_tx_queue *txq)
  3499. {
  3500. u32 val;
  3501. int cpu, desc, desc_per_txq, tx_port_num;
  3502. struct mvpp2_txq_pcpu *txq_pcpu;
  3503. txq->size = port->tx_ring_size;
  3504. /* Allocate memory for Tx descriptors */
  3505. txq->descs = buffer_loc.tx_descs;
  3506. txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
  3507. if (!txq->descs)
  3508. return -ENOMEM;
  3509. /* Make sure descriptor address is cache line size aligned */
  3510. BUG_ON(txq->descs !=
  3511. PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3512. txq->last_desc = txq->size - 1;
  3513. /* Set Tx descriptors queue starting address - indirect access */
  3514. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3515. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
  3516. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
  3517. MVPP2_TXQ_DESC_SIZE_MASK);
  3518. mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
  3519. mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
  3520. txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
  3521. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3522. val &= ~MVPP2_TXQ_PENDING_MASK;
  3523. mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
  3524. /* Calculate base address in prefetch buffer. We reserve 16 descriptors
  3525. * for each existing TXQ.
  3526. * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
  3527. * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
  3528. */
  3529. desc_per_txq = 16;
  3530. desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
  3531. (txq->log_id * desc_per_txq);
  3532. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
  3533. MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
  3534. MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
  3535. /* WRR / EJP configuration - indirect access */
  3536. tx_port_num = mvpp2_egress_port(port);
  3537. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3538. val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
  3539. val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
  3540. val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
  3541. val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
  3542. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
  3543. val = MVPP2_TXQ_TOKEN_SIZE_MAX;
  3544. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
  3545. val);
  3546. for_each_present_cpu(cpu) {
  3547. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3548. txq_pcpu->size = txq->size;
  3549. }
  3550. return 0;
  3551. }
  3552. /* Free allocated TXQ resources */
  3553. static void mvpp2_txq_deinit(struct mvpp2_port *port,
  3554. struct mvpp2_tx_queue *txq)
  3555. {
  3556. txq->descs = NULL;
  3557. txq->last_desc = 0;
  3558. txq->next_desc_to_proc = 0;
  3559. txq->descs_dma = 0;
  3560. /* Set minimum bandwidth for disabled TXQs */
  3561. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
  3562. /* Set Tx descriptors queue starting address and size */
  3563. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3564. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
  3565. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
  3566. }
  3567. /* Cleanup Tx ports */
  3568. static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
  3569. {
  3570. struct mvpp2_txq_pcpu *txq_pcpu;
  3571. int delay, pending, cpu;
  3572. u32 val;
  3573. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3574. val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
  3575. val |= MVPP2_TXQ_DRAIN_EN_MASK;
  3576. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3577. /* The napi queue has been stopped so wait for all packets
  3578. * to be transmitted.
  3579. */
  3580. delay = 0;
  3581. do {
  3582. if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
  3583. dev_warn(port->phy_dev->dev,
  3584. "port %d: cleaning queue %d timed out\n",
  3585. port->id, txq->log_id);
  3586. break;
  3587. }
  3588. mdelay(1);
  3589. delay++;
  3590. pending = mvpp2_txq_pend_desc_num_get(port, txq);
  3591. } while (pending);
  3592. val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
  3593. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3594. for_each_present_cpu(cpu) {
  3595. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3596. /* Release all packets */
  3597. mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
  3598. /* Reset queue */
  3599. txq_pcpu->count = 0;
  3600. txq_pcpu->txq_put_index = 0;
  3601. txq_pcpu->txq_get_index = 0;
  3602. }
  3603. }
  3604. /* Cleanup all Tx queues */
  3605. static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
  3606. {
  3607. struct mvpp2_tx_queue *txq;
  3608. int queue;
  3609. u32 val;
  3610. val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
  3611. /* Reset Tx ports and delete Tx queues */
  3612. val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3613. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3614. for (queue = 0; queue < txq_number; queue++) {
  3615. txq = port->txqs[queue];
  3616. mvpp2_txq_clean(port, txq);
  3617. mvpp2_txq_deinit(port, txq);
  3618. }
  3619. mvpp2_txq_sent_counter_clear(port);
  3620. val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3621. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3622. }
  3623. /* Cleanup all Rx queues */
  3624. static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
  3625. {
  3626. int queue;
  3627. for (queue = 0; queue < rxq_number; queue++)
  3628. mvpp2_rxq_deinit(port, port->rxqs[queue]);
  3629. }
  3630. /* Init all Rx queues for port */
  3631. static int mvpp2_setup_rxqs(struct mvpp2_port *port)
  3632. {
  3633. int queue, err;
  3634. for (queue = 0; queue < rxq_number; queue++) {
  3635. err = mvpp2_rxq_init(port, port->rxqs[queue]);
  3636. if (err)
  3637. goto err_cleanup;
  3638. }
  3639. return 0;
  3640. err_cleanup:
  3641. mvpp2_cleanup_rxqs(port);
  3642. return err;
  3643. }
  3644. /* Init all tx queues for port */
  3645. static int mvpp2_setup_txqs(struct mvpp2_port *port)
  3646. {
  3647. struct mvpp2_tx_queue *txq;
  3648. int queue, err;
  3649. for (queue = 0; queue < txq_number; queue++) {
  3650. txq = port->txqs[queue];
  3651. err = mvpp2_txq_init(port, txq);
  3652. if (err)
  3653. goto err_cleanup;
  3654. }
  3655. mvpp2_txq_sent_counter_clear(port);
  3656. return 0;
  3657. err_cleanup:
  3658. mvpp2_cleanup_txqs(port);
  3659. return err;
  3660. }
  3661. /* Adjust link */
  3662. static void mvpp2_link_event(struct mvpp2_port *port)
  3663. {
  3664. struct phy_device *phydev = port->phy_dev;
  3665. int status_change = 0;
  3666. u32 val;
  3667. if (phydev->link) {
  3668. if ((port->speed != phydev->speed) ||
  3669. (port->duplex != phydev->duplex)) {
  3670. u32 val;
  3671. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3672. val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
  3673. MVPP2_GMAC_CONFIG_GMII_SPEED |
  3674. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  3675. MVPP2_GMAC_AN_SPEED_EN |
  3676. MVPP2_GMAC_AN_DUPLEX_EN);
  3677. if (phydev->duplex)
  3678. val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
  3679. if (phydev->speed == SPEED_1000 ||
  3680. phydev->speed == 2500)
  3681. val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
  3682. else if (phydev->speed == SPEED_100)
  3683. val |= MVPP2_GMAC_CONFIG_MII_SPEED;
  3684. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3685. port->duplex = phydev->duplex;
  3686. port->speed = phydev->speed;
  3687. }
  3688. }
  3689. if (phydev->link != port->link) {
  3690. if (!phydev->link) {
  3691. port->duplex = -1;
  3692. port->speed = 0;
  3693. }
  3694. port->link = phydev->link;
  3695. status_change = 1;
  3696. }
  3697. if (status_change) {
  3698. if (phydev->link) {
  3699. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3700. val |= (MVPP2_GMAC_FORCE_LINK_PASS |
  3701. MVPP2_GMAC_FORCE_LINK_DOWN);
  3702. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3703. mvpp2_egress_enable(port);
  3704. mvpp2_ingress_enable(port);
  3705. } else {
  3706. mvpp2_ingress_disable(port);
  3707. mvpp2_egress_disable(port);
  3708. }
  3709. }
  3710. }
  3711. /* Main RX/TX processing routines */
  3712. /* Display more error info */
  3713. static void mvpp2_rx_error(struct mvpp2_port *port,
  3714. struct mvpp2_rx_desc *rx_desc)
  3715. {
  3716. u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
  3717. size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
  3718. switch (status & MVPP2_RXD_ERR_CODE_MASK) {
  3719. case MVPP2_RXD_ERR_CRC:
  3720. dev_err(port->phy_dev->dev,
  3721. "bad rx status %08x (crc error), size=%zu\n", status,
  3722. sz);
  3723. break;
  3724. case MVPP2_RXD_ERR_OVERRUN:
  3725. dev_err(port->phy_dev->dev,
  3726. "bad rx status %08x (overrun error), size=%zu\n",
  3727. status, sz);
  3728. break;
  3729. case MVPP2_RXD_ERR_RESOURCE:
  3730. dev_err(port->phy_dev->dev,
  3731. "bad rx status %08x (resource error), size=%zu\n",
  3732. status, sz);
  3733. break;
  3734. }
  3735. }
  3736. /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
  3737. static int mvpp2_rx_refill(struct mvpp2_port *port,
  3738. struct mvpp2_bm_pool *bm_pool,
  3739. u32 bm, dma_addr_t dma_addr)
  3740. {
  3741. mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
  3742. return 0;
  3743. }
  3744. /* Set hw internals when starting port */
  3745. static void mvpp2_start_dev(struct mvpp2_port *port)
  3746. {
  3747. switch (port->phy_interface) {
  3748. case PHY_INTERFACE_MODE_RGMII:
  3749. case PHY_INTERFACE_MODE_RGMII_ID:
  3750. case PHY_INTERFACE_MODE_SGMII:
  3751. case PHY_INTERFACE_MODE_SGMII_2500:
  3752. case PHY_INTERFACE_MODE_1000BASEX:
  3753. case PHY_INTERFACE_MODE_2500BASEX:
  3754. mvpp2_gmac_max_rx_size_set(port);
  3755. default:
  3756. break;
  3757. }
  3758. mvpp2_txp_max_tx_size_set(port);
  3759. if (port->priv->hw_version == MVPP21)
  3760. mvpp2_port_enable(port);
  3761. else
  3762. gop_port_enable(port, 1);
  3763. }
  3764. /* Set hw internals when stopping port */
  3765. static void mvpp2_stop_dev(struct mvpp2_port *port)
  3766. {
  3767. /* Stop new packets from arriving to RXQs */
  3768. mvpp2_ingress_disable(port);
  3769. mvpp2_egress_disable(port);
  3770. if (port->priv->hw_version == MVPP21)
  3771. mvpp2_port_disable(port);
  3772. else
  3773. gop_port_enable(port, 0);
  3774. }
  3775. static void mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
  3776. {
  3777. struct phy_device *phy_dev;
  3778. if (!port->init || port->link == 0) {
  3779. phy_dev = dm_mdio_phy_connect(port->mdio_dev, port->phyaddr,
  3780. dev, port->phy_interface);
  3781. /*
  3782. * If the phy doesn't match with any existing u-boot drivers the
  3783. * phy framework will connect it to generic one which
  3784. * uid == 0xffffffff. In this case act as if the phy wouldn't be
  3785. * declared in dts. Otherwise in case of 3310 (for which the
  3786. * driver doesn't exist) the link will not be correctly
  3787. * detected. Removing phy entry from dts in case of 3310 is not
  3788. * an option because it is required for the phy_fw_down
  3789. * procedure.
  3790. */
  3791. if (phy_dev &&
  3792. phy_dev->drv->uid == 0xffffffff) {/* Generic phy */
  3793. dev_warn(port->phy_dev->dev,
  3794. "Marking phy as invalid, link will not be checked\n");
  3795. /* set phy_addr to invalid value */
  3796. port->phyaddr = PHY_MAX_ADDR;
  3797. mvpp2_egress_enable(port);
  3798. mvpp2_ingress_enable(port);
  3799. return;
  3800. }
  3801. port->phy_dev = phy_dev;
  3802. if (!phy_dev) {
  3803. dev_err(port->phy_dev->dev, "cannot connect to phy\n");
  3804. return;
  3805. }
  3806. phy_dev->supported &= PHY_GBIT_FEATURES;
  3807. phy_dev->advertising = phy_dev->supported;
  3808. port->phy_dev = phy_dev;
  3809. port->link = 0;
  3810. port->duplex = 0;
  3811. port->speed = 0;
  3812. phy_config(phy_dev);
  3813. phy_startup(phy_dev);
  3814. if (!phy_dev->link)
  3815. printf("%s: No link\n", phy_dev->dev->name);
  3816. else
  3817. port->init = 1;
  3818. } else {
  3819. mvpp2_egress_enable(port);
  3820. mvpp2_ingress_enable(port);
  3821. }
  3822. }
  3823. static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
  3824. {
  3825. unsigned char mac_bcast[ETH_ALEN] = {
  3826. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  3827. int err;
  3828. err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
  3829. if (err) {
  3830. dev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
  3831. return err;
  3832. }
  3833. err = mvpp2_prs_mac_da_accept(port->priv, port->id,
  3834. port->dev_addr, true);
  3835. if (err) {
  3836. dev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
  3837. return err;
  3838. }
  3839. err = mvpp2_prs_def_flow(port);
  3840. if (err) {
  3841. dev_err(dev, "mvpp2_prs_def_flow failed\n");
  3842. return err;
  3843. }
  3844. /* Allocate the Rx/Tx queues */
  3845. err = mvpp2_setup_rxqs(port);
  3846. if (err) {
  3847. dev_err(port->phy_dev->dev, "cannot allocate Rx queues\n");
  3848. return err;
  3849. }
  3850. err = mvpp2_setup_txqs(port);
  3851. if (err) {
  3852. dev_err(port->phy_dev->dev, "cannot allocate Tx queues\n");
  3853. return err;
  3854. }
  3855. if (port->phyaddr < PHY_MAX_ADDR) {
  3856. mvpp2_phy_connect(dev, port);
  3857. mvpp2_link_event(port);
  3858. } else {
  3859. mvpp2_egress_enable(port);
  3860. mvpp2_ingress_enable(port);
  3861. }
  3862. mvpp2_start_dev(port);
  3863. return 0;
  3864. }
  3865. /* No Device ops here in U-Boot */
  3866. /* Driver initialization */
  3867. static void mvpp2_port_power_up(struct mvpp2_port *port)
  3868. {
  3869. struct mvpp2 *priv = port->priv;
  3870. /* On PPv2.2 the GoP / interface configuration has already been done */
  3871. if (priv->hw_version == MVPP21)
  3872. mvpp2_port_mii_set(port);
  3873. mvpp2_port_periodic_xon_disable(port);
  3874. if (priv->hw_version == MVPP21)
  3875. mvpp2_port_fc_adv_enable(port);
  3876. mvpp2_port_reset(port);
  3877. }
  3878. /* Initialize port HW */
  3879. static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
  3880. {
  3881. struct mvpp2 *priv = port->priv;
  3882. struct mvpp2_txq_pcpu *txq_pcpu;
  3883. int queue, cpu, err;
  3884. if (port->first_rxq + rxq_number >
  3885. MVPP2_MAX_PORTS * priv->max_port_rxqs)
  3886. return -EINVAL;
  3887. /* Disable port */
  3888. mvpp2_egress_disable(port);
  3889. if (priv->hw_version == MVPP21)
  3890. mvpp2_port_disable(port);
  3891. else
  3892. gop_port_enable(port, 0);
  3893. port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
  3894. GFP_KERNEL);
  3895. if (!port->txqs)
  3896. return -ENOMEM;
  3897. /* Associate physical Tx queues to this port and initialize.
  3898. * The mapping is predefined.
  3899. */
  3900. for (queue = 0; queue < txq_number; queue++) {
  3901. int queue_phy_id = mvpp2_txq_phys(port->id, queue);
  3902. struct mvpp2_tx_queue *txq;
  3903. txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
  3904. if (!txq)
  3905. return -ENOMEM;
  3906. txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
  3907. GFP_KERNEL);
  3908. if (!txq->pcpu)
  3909. return -ENOMEM;
  3910. txq->id = queue_phy_id;
  3911. txq->log_id = queue;
  3912. txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
  3913. for_each_present_cpu(cpu) {
  3914. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3915. txq_pcpu->cpu = cpu;
  3916. }
  3917. port->txqs[queue] = txq;
  3918. }
  3919. port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
  3920. GFP_KERNEL);
  3921. if (!port->rxqs)
  3922. return -ENOMEM;
  3923. /* Allocate and initialize Rx queue for this port */
  3924. for (queue = 0; queue < rxq_number; queue++) {
  3925. struct mvpp2_rx_queue *rxq;
  3926. /* Map physical Rx queue to port's logical Rx queue */
  3927. rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
  3928. if (!rxq)
  3929. return -ENOMEM;
  3930. /* Map this Rx queue to a physical queue */
  3931. rxq->id = port->first_rxq + queue;
  3932. rxq->port = port->id;
  3933. rxq->logic_rxq = queue;
  3934. port->rxqs[queue] = rxq;
  3935. }
  3936. /* Create Rx descriptor rings */
  3937. for (queue = 0; queue < rxq_number; queue++) {
  3938. struct mvpp2_rx_queue *rxq = port->rxqs[queue];
  3939. rxq->size = port->rx_ring_size;
  3940. rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
  3941. rxq->time_coal = MVPP2_RX_COAL_USEC;
  3942. }
  3943. mvpp2_ingress_disable(port);
  3944. /* Port default configuration */
  3945. mvpp2_defaults_set(port);
  3946. /* Port's classifier configuration */
  3947. mvpp2_cls_oversize_rxq_set(port);
  3948. mvpp2_cls_port_config(port);
  3949. /* Provide an initial Rx packet size */
  3950. port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
  3951. /* Initialize pools for swf */
  3952. err = mvpp2_swf_bm_pool_init(port);
  3953. if (err)
  3954. return err;
  3955. return 0;
  3956. }
  3957. static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
  3958. {
  3959. int port_node = dev_of_offset(dev);
  3960. const char *phy_mode_str;
  3961. int phy_node;
  3962. u32 id;
  3963. u32 phyaddr = 0;
  3964. int phy_mode = -1;
  3965. int fixed_link = 0;
  3966. int ret;
  3967. phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
  3968. fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link");
  3969. if (phy_node > 0) {
  3970. int parent;
  3971. if (fixed_link != -FDT_ERR_NOTFOUND) {
  3972. /* phy_addr is set to invalid value for fixed links */
  3973. phyaddr = PHY_MAX_ADDR;
  3974. } else {
  3975. phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node,
  3976. "reg", 0);
  3977. if (phyaddr < 0) {
  3978. dev_err(dev, "could not find phy address\n");
  3979. return -1;
  3980. }
  3981. }
  3982. parent = fdt_parent_offset(gd->fdt_blob, phy_node);
  3983. ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
  3984. &port->mdio_dev);
  3985. if (ret)
  3986. return ret;
  3987. } else {
  3988. /* phy_addr is set to invalid value */
  3989. phyaddr = PHY_MAX_ADDR;
  3990. }
  3991. phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
  3992. if (phy_mode_str)
  3993. phy_mode = phy_get_interface_by_name(phy_mode_str);
  3994. if (phy_mode == -1) {
  3995. dev_err(dev, "incorrect phy mode\n");
  3996. return -EINVAL;
  3997. }
  3998. id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
  3999. if (id == -1) {
  4000. dev_err(dev, "missing port-id value\n");
  4001. return -EINVAL;
  4002. }
  4003. #if CONFIG_IS_ENABLED(DM_GPIO)
  4004. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  4005. &port->phy_reset_gpio, GPIOD_IS_OUT);
  4006. gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
  4007. &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
  4008. #endif
  4009. port->id = id;
  4010. if (port->priv->hw_version == MVPP21)
  4011. port->first_rxq = port->id * rxq_number;
  4012. else
  4013. port->first_rxq = port->id * port->priv->max_port_rxqs;
  4014. port->phy_interface = phy_mode;
  4015. port->phyaddr = phyaddr;
  4016. return 0;
  4017. }
  4018. #if CONFIG_IS_ENABLED(DM_GPIO)
  4019. /* Port GPIO initialization */
  4020. static void mvpp2_gpio_init(struct mvpp2_port *port)
  4021. {
  4022. if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
  4023. dm_gpio_set_value(&port->phy_reset_gpio, 1);
  4024. mdelay(10);
  4025. dm_gpio_set_value(&port->phy_reset_gpio, 0);
  4026. }
  4027. if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
  4028. dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
  4029. }
  4030. #endif
  4031. /* Ports initialization */
  4032. static int mvpp2_port_probe(struct udevice *dev,
  4033. struct mvpp2_port *port,
  4034. int port_node,
  4035. struct mvpp2 *priv)
  4036. {
  4037. int err;
  4038. port->tx_ring_size = MVPP2_MAX_TXD;
  4039. port->rx_ring_size = MVPP2_MAX_RXD;
  4040. err = mvpp2_port_init(dev, port);
  4041. if (err < 0) {
  4042. dev_err(dev, "failed to init port %d\n", port->id);
  4043. return err;
  4044. }
  4045. mvpp2_port_power_up(port);
  4046. #if CONFIG_IS_ENABLED(DM_GPIO)
  4047. mvpp2_gpio_init(port);
  4048. #endif
  4049. priv->port_list[port->id] = port;
  4050. priv->num_ports++;
  4051. return 0;
  4052. }
  4053. /* Initialize decoding windows */
  4054. static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
  4055. struct mvpp2 *priv)
  4056. {
  4057. u32 win_enable;
  4058. int i;
  4059. for (i = 0; i < 6; i++) {
  4060. mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
  4061. mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
  4062. if (i < 4)
  4063. mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
  4064. }
  4065. win_enable = 0;
  4066. for (i = 0; i < dram->num_cs; i++) {
  4067. const struct mbus_dram_window *cs = dram->cs + i;
  4068. mvpp2_write(priv, MVPP2_WIN_BASE(i),
  4069. (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
  4070. dram->mbus_dram_target_id);
  4071. mvpp2_write(priv, MVPP2_WIN_SIZE(i),
  4072. (cs->size - 1) & 0xffff0000);
  4073. win_enable |= (1 << i);
  4074. }
  4075. mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
  4076. }
  4077. /* Initialize Rx FIFO's */
  4078. static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
  4079. {
  4080. int port;
  4081. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4082. if (priv->hw_version == MVPP22) {
  4083. if (port == 0) {
  4084. mvpp2_write(priv,
  4085. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4086. MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
  4087. mvpp2_write(priv,
  4088. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4089. MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
  4090. } else if (port == 1) {
  4091. mvpp2_write(priv,
  4092. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4093. MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
  4094. mvpp2_write(priv,
  4095. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4096. MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
  4097. } else {
  4098. mvpp2_write(priv,
  4099. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4100. MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
  4101. mvpp2_write(priv,
  4102. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4103. MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
  4104. }
  4105. } else {
  4106. mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4107. MVPP21_RX_FIFO_PORT_DATA_SIZE);
  4108. mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4109. MVPP21_RX_FIFO_PORT_ATTR_SIZE);
  4110. }
  4111. }
  4112. mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
  4113. MVPP2_RX_FIFO_PORT_MIN_PKT);
  4114. mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
  4115. }
  4116. /* Initialize Tx FIFO's */
  4117. static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
  4118. {
  4119. int port, val;
  4120. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4121. /* Port 0 supports 10KB TX FIFO */
  4122. if (port == 0) {
  4123. val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
  4124. MVPP22_TX_FIFO_SIZE_MASK;
  4125. } else {
  4126. val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
  4127. MVPP22_TX_FIFO_SIZE_MASK;
  4128. }
  4129. mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
  4130. }
  4131. }
  4132. static void mvpp2_axi_init(struct mvpp2 *priv)
  4133. {
  4134. u32 val, rdval, wrval;
  4135. mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
  4136. /* AXI Bridge Configuration */
  4137. rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4138. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4139. rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4140. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4141. wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4142. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4143. wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4144. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4145. /* BM */
  4146. mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
  4147. mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
  4148. /* Descriptors */
  4149. mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
  4150. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
  4151. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
  4152. mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
  4153. /* Buffer Data */
  4154. mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
  4155. mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
  4156. val = MVPP22_AXI_CODE_CACHE_NON_CACHE
  4157. << MVPP22_AXI_CODE_CACHE_OFFS;
  4158. val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
  4159. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4160. mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
  4161. mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
  4162. val = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4163. << MVPP22_AXI_CODE_CACHE_OFFS;
  4164. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4165. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4166. mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
  4167. val = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4168. << MVPP22_AXI_CODE_CACHE_OFFS;
  4169. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4170. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4171. mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
  4172. }
  4173. /* Initialize network controller common part HW */
  4174. static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
  4175. {
  4176. const struct mbus_dram_target_info *dram_target_info;
  4177. int err, i;
  4178. u32 val;
  4179. /* Checks for hardware constraints (U-Boot uses only one rxq) */
  4180. if ((rxq_number > priv->max_port_rxqs) ||
  4181. (txq_number > MVPP2_MAX_TXQ)) {
  4182. dev_err(dev, "invalid queue size parameter\n");
  4183. return -EINVAL;
  4184. }
  4185. if (priv->hw_version == MVPP22)
  4186. mvpp2_axi_init(priv);
  4187. else {
  4188. /* MBUS windows configuration */
  4189. dram_target_info = mvebu_mbus_dram_info();
  4190. if (dram_target_info)
  4191. mvpp2_conf_mbus_windows(dram_target_info, priv);
  4192. }
  4193. if (priv->hw_version == MVPP21) {
  4194. /* Disable HW PHY polling */
  4195. val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4196. val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
  4197. writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4198. } else {
  4199. /* Enable HW PHY polling */
  4200. val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4201. val |= MVPP22_SMI_POLLING_EN;
  4202. writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4203. }
  4204. /* Allocate and initialize aggregated TXQs */
  4205. priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
  4206. sizeof(struct mvpp2_tx_queue),
  4207. GFP_KERNEL);
  4208. if (!priv->aggr_txqs)
  4209. return -ENOMEM;
  4210. for_each_present_cpu(i) {
  4211. priv->aggr_txqs[i].id = i;
  4212. priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
  4213. err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
  4214. MVPP2_AGGR_TXQ_SIZE, i, priv);
  4215. if (err < 0)
  4216. return err;
  4217. }
  4218. /* Rx Fifo Init */
  4219. mvpp2_rx_fifo_init(priv);
  4220. /* Tx Fifo Init */
  4221. if (priv->hw_version == MVPP22)
  4222. mvpp2_tx_fifo_init(priv);
  4223. if (priv->hw_version == MVPP21)
  4224. writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
  4225. priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
  4226. /* Allow cache snoop when transmiting packets */
  4227. mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
  4228. /* Buffer Manager initialization */
  4229. err = mvpp2_bm_init(dev, priv);
  4230. if (err < 0)
  4231. return err;
  4232. /* Parser default initialization */
  4233. err = mvpp2_prs_default_init(dev, priv);
  4234. if (err < 0)
  4235. return err;
  4236. /* Classifier default initialization */
  4237. mvpp2_cls_init(priv);
  4238. return 0;
  4239. }
  4240. static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
  4241. {
  4242. struct mvpp2_port *port = dev_get_priv(dev);
  4243. struct mvpp2_rx_desc *rx_desc;
  4244. struct mvpp2_bm_pool *bm_pool;
  4245. dma_addr_t dma_addr;
  4246. u32 bm, rx_status;
  4247. int pool, rx_bytes, err;
  4248. int rx_received;
  4249. struct mvpp2_rx_queue *rxq;
  4250. u8 *data;
  4251. if (port->phyaddr < PHY_MAX_ADDR)
  4252. if (!port->phy_dev->link)
  4253. return 0;
  4254. /* Process RX packets */
  4255. rxq = port->rxqs[0];
  4256. /* Get number of received packets and clamp the to-do */
  4257. rx_received = mvpp2_rxq_received(port, rxq->id);
  4258. /* Return if no packets are received */
  4259. if (!rx_received)
  4260. return 0;
  4261. rx_desc = mvpp2_rxq_next_desc_get(rxq);
  4262. rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
  4263. rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
  4264. rx_bytes -= MVPP2_MH_SIZE;
  4265. dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
  4266. bm = mvpp2_bm_cookie_build(port, rx_desc);
  4267. pool = mvpp2_bm_cookie_pool_get(bm);
  4268. bm_pool = &port->priv->bm_pools[pool];
  4269. /* In case of an error, release the requested buffer pointer
  4270. * to the Buffer Manager. This request process is controlled
  4271. * by the hardware, and the information about the buffer is
  4272. * comprised by the RX descriptor.
  4273. */
  4274. if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
  4275. mvpp2_rx_error(port, rx_desc);
  4276. /* Return the buffer to the pool */
  4277. mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
  4278. return 0;
  4279. }
  4280. err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
  4281. if (err) {
  4282. dev_err(port->phy_dev->dev, "failed to refill BM pools\n");
  4283. return 0;
  4284. }
  4285. /* Update Rx queue management counters */
  4286. mb();
  4287. mvpp2_rxq_status_update(port, rxq->id, 1, 1);
  4288. /* give packet to stack - skip on first n bytes */
  4289. data = (u8 *)dma_addr + 2 + 32;
  4290. if (rx_bytes <= 0)
  4291. return 0;
  4292. /*
  4293. * No cache invalidation needed here, since the rx_buffer's are
  4294. * located in a uncached memory region
  4295. */
  4296. *packetp = data;
  4297. return rx_bytes;
  4298. }
  4299. static int mvpp2_send(struct udevice *dev, void *packet, int length)
  4300. {
  4301. struct mvpp2_port *port = dev_get_priv(dev);
  4302. struct mvpp2_tx_queue *txq, *aggr_txq;
  4303. struct mvpp2_tx_desc *tx_desc;
  4304. int tx_done;
  4305. int timeout;
  4306. if (port->phyaddr < PHY_MAX_ADDR)
  4307. if (!port->phy_dev->link)
  4308. return 0;
  4309. txq = port->txqs[0];
  4310. aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
  4311. /* Get a descriptor for the first part of the packet */
  4312. tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
  4313. mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
  4314. mvpp2_txdesc_size_set(port, tx_desc, length);
  4315. mvpp2_txdesc_offset_set(port, tx_desc,
  4316. (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
  4317. mvpp2_txdesc_dma_addr_set(port, tx_desc,
  4318. (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
  4319. /* First and Last descriptor */
  4320. mvpp2_txdesc_cmd_set(port, tx_desc,
  4321. MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
  4322. | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
  4323. /* Flush tx data */
  4324. flush_dcache_range((unsigned long)packet,
  4325. (unsigned long)packet + ALIGN(length, PKTALIGN));
  4326. /* Enable transmit */
  4327. mb();
  4328. mvpp2_aggr_txq_pend_desc_add(port, 1);
  4329. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  4330. timeout = 0;
  4331. do {
  4332. if (timeout++ > 10000) {
  4333. printf("timeout: packet not sent from aggregated to phys TXQ\n");
  4334. return 0;
  4335. }
  4336. tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
  4337. } while (tx_done);
  4338. timeout = 0;
  4339. do {
  4340. if (timeout++ > 10000) {
  4341. printf("timeout: packet not sent\n");
  4342. return 0;
  4343. }
  4344. tx_done = mvpp2_txq_sent_desc_proc(port, txq);
  4345. } while (!tx_done);
  4346. return 0;
  4347. }
  4348. static int mvpp2_start(struct udevice *dev)
  4349. {
  4350. struct eth_pdata *pdata = dev_get_plat(dev);
  4351. struct mvpp2_port *port = dev_get_priv(dev);
  4352. /* Load current MAC address */
  4353. memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
  4354. /* Reconfigure parser accept the original MAC address */
  4355. mvpp2_prs_update_mac_da(port, port->dev_addr);
  4356. switch (port->phy_interface) {
  4357. case PHY_INTERFACE_MODE_RGMII:
  4358. case PHY_INTERFACE_MODE_RGMII_ID:
  4359. case PHY_INTERFACE_MODE_SGMII:
  4360. case PHY_INTERFACE_MODE_SGMII_2500:
  4361. case PHY_INTERFACE_MODE_1000BASEX:
  4362. case PHY_INTERFACE_MODE_2500BASEX:
  4363. mvpp2_port_power_up(port);
  4364. default:
  4365. break;
  4366. }
  4367. mvpp2_open(dev, port);
  4368. return 0;
  4369. }
  4370. static void mvpp2_stop(struct udevice *dev)
  4371. {
  4372. struct mvpp2_port *port = dev_get_priv(dev);
  4373. mvpp2_stop_dev(port);
  4374. mvpp2_cleanup_rxqs(port);
  4375. mvpp2_cleanup_txqs(port);
  4376. }
  4377. static int mvpp2_write_hwaddr(struct udevice *dev)
  4378. {
  4379. struct mvpp2_port *port = dev_get_priv(dev);
  4380. return mvpp2_prs_update_mac_da(port, port->dev_addr);
  4381. }
  4382. static int mvpp2_base_probe(struct udevice *dev)
  4383. {
  4384. struct mvpp2 *priv = dev_get_priv(dev);
  4385. void *bd_space;
  4386. u32 size = 0;
  4387. int i;
  4388. /* Save hw-version */
  4389. priv->hw_version = dev_get_driver_data(dev);
  4390. /*
  4391. * U-Boot special buffer handling:
  4392. *
  4393. * Allocate buffer area for descs and rx_buffers. This is only
  4394. * done once for all interfaces. As only one interface can
  4395. * be active. Make this area DMA-safe by disabling the D-cache
  4396. */
  4397. if (!buffer_loc_init) {
  4398. /* Align buffer area for descs and rx_buffers to 1MiB */
  4399. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  4400. mmu_set_region_dcache_behaviour((unsigned long)bd_space,
  4401. BD_SPACE, DCACHE_OFF);
  4402. buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
  4403. size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
  4404. buffer_loc.tx_descs =
  4405. (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
  4406. size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
  4407. buffer_loc.rx_descs =
  4408. (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
  4409. size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
  4410. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  4411. buffer_loc.bm_pool[i] =
  4412. (unsigned long *)((unsigned long)bd_space + size);
  4413. if (priv->hw_version == MVPP21)
  4414. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
  4415. else
  4416. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
  4417. }
  4418. for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
  4419. buffer_loc.rx_buffer[i] =
  4420. (unsigned long *)((unsigned long)bd_space + size);
  4421. size += RX_BUFFER_SIZE;
  4422. }
  4423. /* Clear the complete area so that all descriptors are cleared */
  4424. memset(bd_space, 0, size);
  4425. buffer_loc_init = 1;
  4426. }
  4427. /* Save base addresses for later use */
  4428. priv->base = (void *)devfdt_get_addr_index(dev, 0);
  4429. if (IS_ERR(priv->base))
  4430. return PTR_ERR(priv->base);
  4431. if (priv->hw_version == MVPP21) {
  4432. priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
  4433. if (IS_ERR(priv->lms_base))
  4434. return PTR_ERR(priv->lms_base);
  4435. } else {
  4436. priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
  4437. if (IS_ERR(priv->iface_base))
  4438. return PTR_ERR(priv->iface_base);
  4439. /* Store common base addresses for all ports */
  4440. priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
  4441. priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
  4442. priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
  4443. }
  4444. if (priv->hw_version == MVPP21)
  4445. priv->max_port_rxqs = 8;
  4446. else
  4447. priv->max_port_rxqs = 32;
  4448. return 0;
  4449. }
  4450. static int mvpp2_probe(struct udevice *dev)
  4451. {
  4452. struct mvpp2_port *port = dev_get_priv(dev);
  4453. struct mvpp2 *priv = dev_get_priv(dev->parent);
  4454. int err;
  4455. /* Only call the probe function for the parent once */
  4456. if (!priv->probe_done)
  4457. err = mvpp2_base_probe(dev->parent);
  4458. port->priv = priv;
  4459. err = phy_info_parse(dev, port);
  4460. if (err)
  4461. return err;
  4462. /*
  4463. * We need the port specific io base addresses at this stage, since
  4464. * gop_port_init() accesses these registers
  4465. */
  4466. if (priv->hw_version == MVPP21) {
  4467. int priv_common_regs_num = 2;
  4468. port->base = (void __iomem *)devfdt_get_addr_index(
  4469. dev->parent, priv_common_regs_num + port->id);
  4470. if (IS_ERR(port->base))
  4471. return PTR_ERR(port->base);
  4472. } else {
  4473. port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  4474. "gop-port-id", -1);
  4475. if (port->id == -1) {
  4476. dev_err(dev, "missing gop-port-id value\n");
  4477. return -EINVAL;
  4478. }
  4479. port->base = priv->iface_base + MVPP22_PORT_BASE +
  4480. port->gop_id * MVPP22_PORT_OFFSET;
  4481. /* GoP Init */
  4482. gop_port_init(port);
  4483. }
  4484. if (!priv->probe_done) {
  4485. /* Initialize network controller */
  4486. err = mvpp2_init(dev, priv);
  4487. if (err < 0) {
  4488. dev_err(dev, "failed to initialize controller\n");
  4489. return err;
  4490. }
  4491. priv->num_ports = 0;
  4492. priv->probe_done = 1;
  4493. }
  4494. err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
  4495. if (err)
  4496. return err;
  4497. if (priv->hw_version == MVPP22) {
  4498. priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
  4499. port->phy_interface);
  4500. /* Netcomplex configurations for all ports */
  4501. gop_netc_init(priv, MV_NETC_FIRST_PHASE);
  4502. gop_netc_init(priv, MV_NETC_SECOND_PHASE);
  4503. }
  4504. return 0;
  4505. }
  4506. /*
  4507. * Empty BM pool and stop its activity before the OS is started
  4508. */
  4509. static int mvpp2_remove(struct udevice *dev)
  4510. {
  4511. struct mvpp2_port *port = dev_get_priv(dev);
  4512. struct mvpp2 *priv = port->priv;
  4513. int i;
  4514. priv->num_ports--;
  4515. if (priv->num_ports)
  4516. return 0;
  4517. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
  4518. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  4519. return 0;
  4520. }
  4521. static const struct eth_ops mvpp2_ops = {
  4522. .start = mvpp2_start,
  4523. .send = mvpp2_send,
  4524. .recv = mvpp2_recv,
  4525. .stop = mvpp2_stop,
  4526. .write_hwaddr = mvpp2_write_hwaddr
  4527. };
  4528. static struct driver mvpp2_driver = {
  4529. .name = "mvpp2",
  4530. .id = UCLASS_ETH,
  4531. .probe = mvpp2_probe,
  4532. .remove = mvpp2_remove,
  4533. .ops = &mvpp2_ops,
  4534. .priv_auto = sizeof(struct mvpp2_port),
  4535. .plat_auto = sizeof(struct eth_pdata),
  4536. .flags = DM_FLAG_ACTIVE_DMA,
  4537. };
  4538. /*
  4539. * Use a MISC device to bind the n instances (child nodes) of the
  4540. * network base controller in UCLASS_ETH.
  4541. */
  4542. static int mvpp2_base_bind(struct udevice *parent)
  4543. {
  4544. const void *blob = gd->fdt_blob;
  4545. int node = dev_of_offset(parent);
  4546. struct uclass_driver *drv;
  4547. struct udevice *dev;
  4548. struct eth_pdata *plat;
  4549. char *name;
  4550. int subnode;
  4551. u32 id;
  4552. int base_id_add;
  4553. /* Lookup eth driver */
  4554. drv = lists_uclass_lookup(UCLASS_ETH);
  4555. if (!drv) {
  4556. puts("Cannot find eth driver\n");
  4557. return -ENOENT;
  4558. }
  4559. base_id_add = base_id;
  4560. fdt_for_each_subnode(subnode, blob, node) {
  4561. /* Increment base_id for all subnodes, also the disabled ones */
  4562. base_id++;
  4563. /* Skip disabled ports */
  4564. if (!fdtdec_get_is_enabled(blob, subnode))
  4565. continue;
  4566. plat = calloc(1, sizeof(*plat));
  4567. if (!plat)
  4568. return -ENOMEM;
  4569. id = fdtdec_get_int(blob, subnode, "port-id", -1);
  4570. id += base_id_add;
  4571. name = calloc(1, 16);
  4572. if (!name) {
  4573. free(plat);
  4574. return -ENOMEM;
  4575. }
  4576. sprintf(name, "mvpp2-%d", id);
  4577. /* Create child device UCLASS_ETH and bind it */
  4578. device_bind(parent, &mvpp2_driver, name, plat,
  4579. offset_to_ofnode(subnode), &dev);
  4580. }
  4581. return 0;
  4582. }
  4583. static const struct udevice_id mvpp2_ids[] = {
  4584. {
  4585. .compatible = "marvell,armada-375-pp2",
  4586. .data = MVPP21,
  4587. },
  4588. {
  4589. .compatible = "marvell,armada-7k-pp22",
  4590. .data = MVPP22,
  4591. },
  4592. { }
  4593. };
  4594. U_BOOT_DRIVER(mvpp2_base) = {
  4595. .name = "mvpp2_base",
  4596. .id = UCLASS_MISC,
  4597. .of_match = mvpp2_ids,
  4598. .bind = mvpp2_base_bind,
  4599. .priv_auto = sizeof(struct mvpp2),
  4600. };