mpc8xx_fec.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <hang.h>
  9. #include <malloc.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <asm/cpm_8xx.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <linux/delay.h>
  16. #include <phy.h>
  17. #include <linux/mii.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /* define WANT_MII when MII support is required */
  20. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
  21. #define WANT_MII
  22. #else
  23. #undef WANT_MII
  24. #endif
  25. #if defined(WANT_MII)
  26. #include <miiphy.h>
  27. #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  28. #error "CONFIG_MII has to be defined!"
  29. #endif
  30. #endif
  31. #if defined(CONFIG_RMII) && !defined(WANT_MII)
  32. #error RMII support is unusable without a working PHY.
  33. #endif
  34. #ifdef CONFIG_SYS_DISCOVER_PHY
  35. static int mii_discover_phy(struct eth_device *dev);
  36. #endif
  37. int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
  38. int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  39. u16 value);
  40. static struct ether_fcc_info_s
  41. {
  42. int ether_index;
  43. int fecp_offset;
  44. int phy_addr;
  45. int actual_phy_addr;
  46. int initialized;
  47. }
  48. ether_fcc_info[] = {
  49. #if defined(CONFIG_ETHER_ON_FEC1)
  50. {
  51. 0,
  52. offsetof(immap_t, im_cpm.cp_fec1),
  53. CONFIG_FEC1_PHY,
  54. -1,
  55. 0,
  56. },
  57. #endif
  58. #if defined(CONFIG_ETHER_ON_FEC2)
  59. {
  60. 1,
  61. offsetof(immap_t, im_cpm.cp_fec2),
  62. CONFIG_FEC2_PHY,
  63. -1,
  64. 0,
  65. },
  66. #endif
  67. };
  68. /* Ethernet Transmit and Receive Buffers */
  69. #define DBUF_LENGTH 1520
  70. #define TX_BUF_CNT 2
  71. #define TOUT_LOOP 100
  72. #define PKT_MAXBUF_SIZE 1518
  73. #define PKT_MINBUF_SIZE 64
  74. #define PKT_MAXBLR_SIZE 1520
  75. #ifdef __GNUC__
  76. static char txbuf[DBUF_LENGTH] __aligned(8);
  77. #else
  78. #error txbuf must be aligned.
  79. #endif
  80. static uint rxIdx; /* index of the current RX buffer */
  81. static uint txIdx; /* index of the current TX buffer */
  82. /*
  83. * FEC Ethernet Tx and Rx buffer descriptors allocated at the
  84. * immr->udata_bd address on Dual-Port RAM
  85. * Provide for Double Buffering
  86. */
  87. struct common_buf_desc {
  88. cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
  89. cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  90. };
  91. static struct common_buf_desc __iomem *rtx;
  92. static int fec_send(struct eth_device *dev, void *packet, int length);
  93. static int fec_recv(struct eth_device *dev);
  94. static int fec_init(struct eth_device *dev, struct bd_info *bd);
  95. static void fec_halt(struct eth_device *dev);
  96. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  97. static void __mii_init(void);
  98. #endif
  99. int fec_initialize(struct bd_info *bis)
  100. {
  101. struct eth_device *dev;
  102. struct ether_fcc_info_s *efis;
  103. int i;
  104. for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
  105. dev = malloc(sizeof(*dev));
  106. if (dev == NULL)
  107. hang();
  108. memset(dev, 0, sizeof(*dev));
  109. /* for FEC1 make sure that the name of the interface is the same
  110. as the old one for compatibility reasons */
  111. if (i == 0)
  112. strcpy(dev->name, "FEC");
  113. else
  114. sprintf(dev->name, "FEC%d",
  115. ether_fcc_info[i].ether_index + 1);
  116. efis = &ether_fcc_info[i];
  117. /*
  118. * reset actual phy addr
  119. */
  120. efis->actual_phy_addr = -1;
  121. dev->priv = efis;
  122. dev->init = fec_init;
  123. dev->halt = fec_halt;
  124. dev->send = fec_send;
  125. dev->recv = fec_recv;
  126. eth_register(dev);
  127. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  128. int retval;
  129. struct mii_dev *mdiodev = mdio_alloc();
  130. if (!mdiodev)
  131. return -ENOMEM;
  132. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  133. mdiodev->read = fec8xx_miiphy_read;
  134. mdiodev->write = fec8xx_miiphy_write;
  135. retval = mdio_register(mdiodev);
  136. if (retval < 0)
  137. return retval;
  138. #endif
  139. }
  140. return 1;
  141. }
  142. static int fec_send(struct eth_device *dev, void *packet, int length)
  143. {
  144. int j, rc;
  145. struct ether_fcc_info_s *efis = dev->priv;
  146. fec_t __iomem *fecp =
  147. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  148. /* section 16.9.23.3
  149. * Wait for ready
  150. */
  151. j = 0;
  152. while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
  153. (j < TOUT_LOOP)) {
  154. udelay(1);
  155. j++;
  156. }
  157. if (j >= TOUT_LOOP)
  158. printf("TX not ready\n");
  159. out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
  160. out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
  161. setbits_be16(&rtx->txbd[txIdx].cbd_sc,
  162. BD_ENET_TX_READY | BD_ENET_TX_LAST);
  163. /* Activate transmit Buffer Descriptor polling */
  164. /* Descriptor polling active */
  165. out_be32(&fecp->fec_x_des_active, 0x01000000);
  166. j = 0;
  167. while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
  168. (j < TOUT_LOOP)) {
  169. udelay(1);
  170. j++;
  171. }
  172. if (j >= TOUT_LOOP)
  173. printf("TX timeout\n");
  174. /* return only status bits */;
  175. rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
  176. txIdx = (txIdx + 1) % TX_BUF_CNT;
  177. return rc;
  178. }
  179. static int fec_recv(struct eth_device *dev)
  180. {
  181. struct ether_fcc_info_s *efis = dev->priv;
  182. fec_t __iomem *fecp =
  183. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  184. int length;
  185. for (;;) {
  186. /* section 16.9.23.2 */
  187. if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
  188. length = -1;
  189. break; /* nothing received - leave for() loop */
  190. }
  191. length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
  192. if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
  193. uchar *rx = net_rx_packets[rxIdx];
  194. length -= 4;
  195. #if defined(CONFIG_CMD_CDP)
  196. if ((rx[0] & 1) != 0 &&
  197. memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
  198. !is_cdp_packet((uchar *)rx))
  199. rx = NULL;
  200. #endif
  201. /*
  202. * Pass the packet up to the protocol layers.
  203. */
  204. if (rx != NULL)
  205. net_process_received_packet(rx, length);
  206. }
  207. /* Give the buffer back to the FEC. */
  208. out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
  209. /* wrap around buffer index when necessary */
  210. if ((rxIdx + 1) >= PKTBUFSRX) {
  211. out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
  212. BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  213. rxIdx = 0;
  214. } else {
  215. out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
  216. rxIdx++;
  217. }
  218. /* Try to fill Buffer Descriptors */
  219. /* Descriptor polling active */
  220. out_be32(&fecp->fec_r_des_active, 0x01000000);
  221. }
  222. return length;
  223. }
  224. /**************************************************************
  225. *
  226. * FEC Ethernet Initialization Routine
  227. *
  228. *************************************************************/
  229. #define FEC_ECNTRL_PINMUX 0x00000004
  230. #define FEC_ECNTRL_ETHER_EN 0x00000002
  231. #define FEC_ECNTRL_RESET 0x00000001
  232. #define FEC_RCNTRL_BC_REJ 0x00000010
  233. #define FEC_RCNTRL_PROM 0x00000008
  234. #define FEC_RCNTRL_MII_MODE 0x00000004
  235. #define FEC_RCNTRL_DRT 0x00000002
  236. #define FEC_RCNTRL_LOOP 0x00000001
  237. #define FEC_TCNTRL_FDEN 0x00000004
  238. #define FEC_TCNTRL_HBC 0x00000002
  239. #define FEC_TCNTRL_GTS 0x00000001
  240. #define FEC_RESET_DELAY 50
  241. #if defined(CONFIG_RMII)
  242. static inline void fec_10Mbps(struct eth_device *dev)
  243. {
  244. struct ether_fcc_info_s *efis = dev->priv;
  245. int fecidx = efis->ether_index;
  246. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  247. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  248. if ((unsigned int)fecidx >= 2)
  249. hang();
  250. setbits_be32(&immr->im_cpm.cp_cptr, mask);
  251. }
  252. static inline void fec_100Mbps(struct eth_device *dev)
  253. {
  254. struct ether_fcc_info_s *efis = dev->priv;
  255. int fecidx = efis->ether_index;
  256. uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
  257. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  258. if ((unsigned int)fecidx >= 2)
  259. hang();
  260. clrbits_be32(&immr->im_cpm.cp_cptr, mask);
  261. }
  262. #endif
  263. static inline void fec_full_duplex(struct eth_device *dev)
  264. {
  265. struct ether_fcc_info_s *efis = dev->priv;
  266. fec_t __iomem *fecp =
  267. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  268. clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
  269. setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
  270. }
  271. static inline void fec_half_duplex(struct eth_device *dev)
  272. {
  273. struct ether_fcc_info_s *efis = dev->priv;
  274. fec_t __iomem *fecp =
  275. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  276. setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
  277. clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
  278. }
  279. static void fec_pin_init(int fecidx)
  280. {
  281. struct bd_info *bd = gd->bd;
  282. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  283. /*
  284. * Set MII speed to 2.5 MHz or slightly below.
  285. *
  286. * According to the MPC860T (Rev. D) Fast ethernet controller user
  287. * manual (6.2.14),
  288. * the MII management interface clock must be less than or equal
  289. * to 2.5 MHz.
  290. * This MDC frequency is equal to system clock / (2 * MII_SPEED).
  291. * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
  292. *
  293. * All MII configuration is done via FEC1 registers:
  294. */
  295. out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
  296. ((bd->bi_intfreq + 4999999) / 5000000) << 1);
  297. #if defined(CONFIG_MPC885) && defined(WANT_MII)
  298. /* use MDC for MII */
  299. setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
  300. clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
  301. #endif
  302. if (fecidx == 0) {
  303. #if defined(CONFIG_ETHER_ON_FEC1)
  304. #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
  305. #if !defined(CONFIG_RMII)
  306. setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
  307. setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
  308. clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
  309. setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
  310. clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
  311. setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
  312. clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
  313. setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
  314. setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
  315. clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
  316. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
  317. #else
  318. #if !defined(CONFIG_FEC1_PHY_NORXERR)
  319. setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
  320. clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
  321. #endif
  322. setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
  323. setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
  324. clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
  325. setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
  326. clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
  327. setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
  328. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
  329. #endif /* !CONFIG_RMII */
  330. #else
  331. /*
  332. * Configure all of port D for MII.
  333. */
  334. out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
  335. out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
  336. #if defined(CONFIG_TARGET_MCR3000)
  337. out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
  338. out_be16(&immr->im_ioport.iop_padir, 0x04F0);
  339. out_be16(&immr->im_ioport.iop_paodr, 0x0000);
  340. out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
  341. out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
  342. out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
  343. out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
  344. out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
  345. out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
  346. out_be16(&immr->im_ioport.iop_pcint, 0x0000);
  347. out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
  348. out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
  349. setbits_be32(&immr->im_ioport.utmode, 0x80);
  350. #endif
  351. #endif
  352. #endif /* CONFIG_ETHER_ON_FEC1 */
  353. } else if (fecidx == 1) {
  354. #if defined(CONFIG_ETHER_ON_FEC2)
  355. #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
  356. #if !defined(CONFIG_RMII)
  357. setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
  358. setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
  359. clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
  360. setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
  361. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
  362. #else
  363. #if !defined(CONFIG_FEC2_PHY_NORXERR)
  364. setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
  365. setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
  366. clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
  367. #endif
  368. setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
  369. setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
  370. setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
  371. clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
  372. setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
  373. clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
  374. #endif /* CONFIG_RMII */
  375. #endif /* CONFIG_MPC885 */
  376. #endif /* CONFIG_ETHER_ON_FEC2 */
  377. }
  378. }
  379. static int fec_reset(fec_t __iomem *fecp)
  380. {
  381. int i;
  382. /* Whack a reset.
  383. * A delay is required between a reset of the FEC block and
  384. * initialization of other FEC registers because the reset takes
  385. * some time to complete. If you don't delay, subsequent writes
  386. * to FEC registers might get killed by the reset routine which is
  387. * still in progress.
  388. */
  389. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
  390. for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
  391. (i < FEC_RESET_DELAY); ++i)
  392. udelay(1);
  393. if (i == FEC_RESET_DELAY)
  394. return -1;
  395. return 0;
  396. }
  397. static int fec_init(struct eth_device *dev, struct bd_info *bd)
  398. {
  399. struct ether_fcc_info_s *efis = dev->priv;
  400. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  401. fec_t __iomem *fecp =
  402. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  403. int i;
  404. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  405. /* the MII interface is connected to FEC1
  406. * so for the miiphy_xxx function to work we must
  407. * call mii_init since fec_halt messes the thing up
  408. */
  409. if (efis->ether_index != 0)
  410. __mii_init();
  411. #endif
  412. if (fec_reset(fecp) < 0)
  413. printf("FEC_RESET_DELAY timeout\n");
  414. /* We use strictly polling mode only
  415. */
  416. out_be32(&fecp->fec_imask, 0);
  417. /* Clear any pending interrupt
  418. */
  419. out_be32(&fecp->fec_ievent, 0xffc0);
  420. /* No need to set the IVEC register */
  421. /* Set station address
  422. */
  423. #define ea dev->enetaddr
  424. out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
  425. (ea[2] << 8) | ea[3]);
  426. out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
  427. #undef ea
  428. #if defined(CONFIG_CMD_CDP)
  429. /*
  430. * Turn on multicast address hash table
  431. */
  432. out_be32(&fecp->fec_hash_table_high, 0xffffffff);
  433. out_be32(&fecp->fec_hash_table_low, 0xffffffff);
  434. #else
  435. /* Clear multicast address hash table
  436. */
  437. out_be32(&fecp->fec_hash_table_high, 0);
  438. out_be32(&fecp->fec_hash_table_low, 0);
  439. #endif
  440. /* Set maximum receive buffer size.
  441. */
  442. out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
  443. /* Set maximum frame length
  444. */
  445. out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
  446. /*
  447. * Setup Buffers and Buffer Descriptors
  448. */
  449. rxIdx = 0;
  450. txIdx = 0;
  451. if (!rtx)
  452. rtx = (struct common_buf_desc __iomem *)
  453. (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
  454. /*
  455. * Setup Receiver Buffer Descriptors (13.14.24.18)
  456. * Settings:
  457. * Empty, Wrap
  458. */
  459. for (i = 0; i < PKTBUFSRX; i++) {
  460. out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
  461. out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
  462. out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
  463. }
  464. setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
  465. /*
  466. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  467. * Settings:
  468. * Last, Tx CRC
  469. */
  470. for (i = 0; i < TX_BUF_CNT; i++) {
  471. out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
  472. out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
  473. out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
  474. }
  475. setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
  476. /* Set receive and transmit descriptor base
  477. */
  478. out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
  479. out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
  480. /* Enable MII mode
  481. */
  482. /* Half duplex mode */
  483. out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
  484. out_be32(&fecp->fec_x_cntrl, 0);
  485. /* Enable big endian and don't care about SDMA FC.
  486. */
  487. out_be32(&fecp->fec_fun_code, 0x78000000);
  488. /*
  489. * Setup the pin configuration of the FEC
  490. */
  491. fec_pin_init(efis->ether_index);
  492. rxIdx = 0;
  493. txIdx = 0;
  494. /*
  495. * Now enable the transmit and receive processing
  496. */
  497. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  498. if (efis->phy_addr == -1) {
  499. #ifdef CONFIG_SYS_DISCOVER_PHY
  500. /*
  501. * wait for the PHY to wake up after reset
  502. */
  503. efis->actual_phy_addr = mii_discover_phy(dev);
  504. if (efis->actual_phy_addr == -1) {
  505. printf("Unable to discover phy!\n");
  506. return -1;
  507. }
  508. #else
  509. efis->actual_phy_addr = -1;
  510. #endif
  511. } else {
  512. efis->actual_phy_addr = efis->phy_addr;
  513. }
  514. #if defined(CONFIG_MII) && defined(CONFIG_RMII)
  515. /*
  516. * adapt the RMII speed to the speed of the phy
  517. */
  518. if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
  519. fec_100Mbps(dev);
  520. else
  521. fec_10Mbps(dev);
  522. #endif
  523. #if defined(CONFIG_MII)
  524. /*
  525. * adapt to the half/full speed settings
  526. */
  527. if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
  528. fec_full_duplex(dev);
  529. else
  530. fec_half_duplex(dev);
  531. #endif
  532. /* And last, try to fill Rx Buffer Descriptors */
  533. /* Descriptor polling active */
  534. out_be32(&fecp->fec_r_des_active, 0x01000000);
  535. efis->initialized = 1;
  536. return 0;
  537. }
  538. static void fec_halt(struct eth_device *dev)
  539. {
  540. struct ether_fcc_info_s *efis = dev->priv;
  541. fec_t __iomem *fecp =
  542. (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
  543. int i;
  544. /* avoid halt if initialized; mii gets stuck otherwise */
  545. if (!efis->initialized)
  546. return;
  547. /* Whack a reset.
  548. * A delay is required between a reset of the FEC block and
  549. * initialization of other FEC registers because the reset takes
  550. * some time to complete. If you don't delay, subsequent writes
  551. * to FEC registers might get killed by the reset routine which is
  552. * still in progress.
  553. */
  554. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
  555. for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
  556. (i < FEC_RESET_DELAY); ++i)
  557. udelay(1);
  558. if (i == FEC_RESET_DELAY) {
  559. printf("FEC_RESET_DELAY timeout\n");
  560. return;
  561. }
  562. efis->initialized = 0;
  563. }
  564. #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  565. /* Make MII read/write commands for the FEC.
  566. */
  567. #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
  568. (REG & 0x1f) << 18))
  569. #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
  570. (REG & 0x1f) << 18) | \
  571. (VAL & 0xffff))
  572. /* Interrupt events/masks.
  573. */
  574. #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
  575. #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
  576. #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
  577. #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
  578. #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
  579. #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
  580. #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
  581. #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
  582. #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
  583. #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
  584. /* send command to phy using mii, wait for result */
  585. static uint
  586. mii_send(uint mii_cmd)
  587. {
  588. uint mii_reply;
  589. fec_t __iomem *ep;
  590. int cnt;
  591. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  592. ep = &immr->im_cpm.cp_fec;
  593. out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
  594. /* wait for mii complete */
  595. cnt = 0;
  596. while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
  597. if (++cnt > 1000) {
  598. printf("mii_send STUCK!\n");
  599. break;
  600. }
  601. }
  602. mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
  603. out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
  604. return mii_reply & 0xffff; /* data read from phy */
  605. }
  606. #endif
  607. #if defined(CONFIG_SYS_DISCOVER_PHY)
  608. static int mii_discover_phy(struct eth_device *dev)
  609. {
  610. #define MAX_PHY_PASSES 11
  611. uint phyno;
  612. int pass;
  613. uint phytype;
  614. int phyaddr;
  615. phyaddr = -1; /* didn't find a PHY yet */
  616. for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
  617. if (pass > 1) {
  618. /* PHY may need more time to recover from reset.
  619. * The LXT970 needs 50ms typical, no maximum is
  620. * specified, so wait 10ms before try again.
  621. * With 11 passes this gives it 100ms to wake up.
  622. */
  623. udelay(10000); /* wait 10ms */
  624. }
  625. for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
  626. phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
  627. if (phytype != 0xffff) {
  628. phyaddr = phyno;
  629. phytype |= mii_send(mk_mii_read(phyno,
  630. MII_PHYSID1)) << 16;
  631. }
  632. }
  633. }
  634. if (phyaddr < 0)
  635. printf("No PHY device found.\n");
  636. return phyaddr;
  637. }
  638. #endif /* CONFIG_SYS_DISCOVER_PHY */
  639. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
  640. /****************************************************************************
  641. * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
  642. * This function is a subset of eth_init
  643. ****************************************************************************
  644. */
  645. static void __mii_init(void)
  646. {
  647. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  648. fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
  649. if (fec_reset(fecp) < 0)
  650. printf("FEC_RESET_DELAY timeout\n");
  651. /* We use strictly polling mode only
  652. */
  653. out_be32(&fecp->fec_imask, 0);
  654. /* Clear any pending interrupt
  655. */
  656. out_be32(&fecp->fec_ievent, 0xffc0);
  657. /* Now enable the transmit and receive processing
  658. */
  659. out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  660. }
  661. void mii_init(void)
  662. {
  663. int i;
  664. __mii_init();
  665. /* Setup the pin configuration of the FEC(s)
  666. */
  667. for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
  668. fec_pin_init(ether_fcc_info[i].ether_index);
  669. }
  670. /*****************************************************************************
  671. * Read and write a MII PHY register, routines used by MII Utilities
  672. *
  673. * FIXME: These routines are expected to return 0 on success, but mii_send
  674. * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
  675. * no PHY connected...
  676. * For now always return 0.
  677. * FIXME: These routines only work after calling eth_init() at least once!
  678. * Otherwise they hang in mii_send() !!! Sorry!
  679. *****************************************************************************/
  680. int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
  681. {
  682. unsigned short value = 0;
  683. short rdreg; /* register working value */
  684. rdreg = mii_send(mk_mii_read(addr, reg));
  685. value = rdreg;
  686. return value;
  687. }
  688. int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
  689. u16 value)
  690. {
  691. (void)mii_send(mk_mii_write(addr, reg, value));
  692. return 0;
  693. }
  694. #endif