intel_ich6_gpio.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012 The Chromium OS Authors.
  4. */
  5. /*
  6. * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
  7. * through the PCI bus. Each PCI device has 256 bytes of configuration space,
  8. * consisting of a standard header and a device-specific set of registers. PCI
  9. * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
  10. * other things). Within the PCI configuration space, the GPIOBASE register
  11. * tells us where in the device's I/O region we can find more registers to
  12. * actually access the GPIOs.
  13. *
  14. * PCI bus/device/function 0:1f:0 => PCI config registers
  15. * PCI config register "GPIOBASE"
  16. * PCI I/O space + [GPIOBASE] => start of GPIO registers
  17. * GPIO registers => gpio pin function, direction, value
  18. *
  19. *
  20. * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
  21. * ICH versions have more, but the decoding the matrix that describes them is
  22. * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
  23. * but they will ONLY work for certain unspecified chipsets because the offset
  24. * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
  25. * reserved or subject to arcane restrictions.
  26. */
  27. #include <common.h>
  28. #include <dm.h>
  29. #include <errno.h>
  30. #include <fdtdec.h>
  31. #include <log.h>
  32. #include <pch.h>
  33. #include <pci.h>
  34. #include <asm/cpu.h>
  35. #include <asm/global_data.h>
  36. #include <asm/gpio.h>
  37. #include <asm/io.h>
  38. #include <asm/pci.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #define GPIO_PER_BANK 32
  41. struct ich6_bank_priv {
  42. /* These are I/O addresses */
  43. uint16_t use_sel;
  44. uint16_t io_sel;
  45. uint16_t lvl;
  46. u32 lvl_write_cache;
  47. bool use_lvl_write_cache;
  48. };
  49. #define GPIO_USESEL_OFFSET(x) (x)
  50. #define GPIO_IOSEL_OFFSET(x) (x + 4)
  51. #define GPIO_LVL_OFFSET(x) (x + 8)
  52. static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
  53. int value)
  54. {
  55. u32 val;
  56. if (bank->use_lvl_write_cache)
  57. val = bank->lvl_write_cache;
  58. else
  59. val = inl(bank->lvl);
  60. if (value)
  61. val |= (1UL << offset);
  62. else
  63. val &= ~(1UL << offset);
  64. outl(val, bank->lvl);
  65. if (bank->use_lvl_write_cache)
  66. bank->lvl_write_cache = val;
  67. return 0;
  68. }
  69. static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
  70. {
  71. u32 val;
  72. if (!dir) {
  73. val = inl(base);
  74. val |= (1UL << offset);
  75. outl(val, base);
  76. } else {
  77. val = inl(base);
  78. val &= ~(1UL << offset);
  79. outl(val, base);
  80. }
  81. return 0;
  82. }
  83. static int gpio_ich6_of_to_plat(struct udevice *dev)
  84. {
  85. struct ich6_bank_plat *plat = dev_get_plat(dev);
  86. u32 gpiobase;
  87. int offset;
  88. int ret;
  89. ret = pch_get_gpio_base(dev->parent, &gpiobase);
  90. if (ret)
  91. return ret;
  92. offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
  93. if (offset == -1) {
  94. debug("%s: Invalid register offset %d\n", __func__, offset);
  95. return -EINVAL;
  96. }
  97. plat->offset = offset;
  98. plat->base_addr = gpiobase + offset;
  99. plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  100. "bank-name", NULL);
  101. return 0;
  102. }
  103. static int ich6_gpio_probe(struct udevice *dev)
  104. {
  105. struct ich6_bank_plat *plat = dev_get_plat(dev);
  106. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  107. struct ich6_bank_priv *bank = dev_get_priv(dev);
  108. const void *prop;
  109. uc_priv->gpio_count = GPIO_PER_BANK;
  110. uc_priv->bank_name = plat->bank_name;
  111. bank->use_sel = plat->base_addr;
  112. bank->io_sel = plat->base_addr + 4;
  113. bank->lvl = plat->base_addr + 8;
  114. prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  115. "use-lvl-write-cache", NULL);
  116. if (prop)
  117. bank->use_lvl_write_cache = true;
  118. else
  119. bank->use_lvl_write_cache = false;
  120. bank->lvl_write_cache = 0;
  121. return 0;
  122. }
  123. static int ich6_gpio_request(struct udevice *dev, unsigned offset,
  124. const char *label)
  125. {
  126. struct ich6_bank_priv *bank = dev_get_priv(dev);
  127. u32 tmplong;
  128. /*
  129. * Make sure that the GPIO pin we want isn't already in use for some
  130. * built-in hardware function. We have to check this for every
  131. * requested pin.
  132. */
  133. tmplong = inl(bank->use_sel);
  134. if (!(tmplong & (1UL << offset))) {
  135. debug("%s: gpio %d is reserved for internal use\n", __func__,
  136. offset);
  137. return -EPERM;
  138. }
  139. return 0;
  140. }
  141. static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
  142. {
  143. struct ich6_bank_priv *bank = dev_get_priv(dev);
  144. return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
  145. }
  146. static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
  147. int value)
  148. {
  149. int ret;
  150. struct ich6_bank_priv *bank = dev_get_priv(dev);
  151. ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
  152. if (ret)
  153. return ret;
  154. return _ich6_gpio_set_value(bank, offset, value);
  155. }
  156. static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
  157. {
  158. struct ich6_bank_priv *bank = dev_get_priv(dev);
  159. u32 tmplong;
  160. int r;
  161. tmplong = inl(bank->lvl);
  162. if (bank->use_lvl_write_cache)
  163. tmplong |= bank->lvl_write_cache;
  164. r = (tmplong & (1UL << offset)) ? 1 : 0;
  165. return r;
  166. }
  167. static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
  168. int value)
  169. {
  170. struct ich6_bank_priv *bank = dev_get_priv(dev);
  171. return _ich6_gpio_set_value(bank, offset, value);
  172. }
  173. static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
  174. {
  175. struct ich6_bank_priv *bank = dev_get_priv(dev);
  176. u32 mask = 1UL << offset;
  177. if (!(inl(bank->use_sel) & mask))
  178. return GPIOF_FUNC;
  179. if (inl(bank->io_sel) & mask)
  180. return GPIOF_INPUT;
  181. else
  182. return GPIOF_OUTPUT;
  183. }
  184. static const struct dm_gpio_ops gpio_ich6_ops = {
  185. .request = ich6_gpio_request,
  186. .direction_input = ich6_gpio_direction_input,
  187. .direction_output = ich6_gpio_direction_output,
  188. .get_value = ich6_gpio_get_value,
  189. .set_value = ich6_gpio_set_value,
  190. .get_function = ich6_gpio_get_function,
  191. };
  192. static const struct udevice_id intel_ich6_gpio_ids[] = {
  193. { .compatible = "intel,ich6-gpio" },
  194. { }
  195. };
  196. U_BOOT_DRIVER(gpio_ich6) = {
  197. .name = "gpio_ich6",
  198. .id = UCLASS_GPIO,
  199. .of_match = intel_ich6_gpio_ids,
  200. .ops = &gpio_ich6_ops,
  201. .of_to_plat = gpio_ich6_of_to_plat,
  202. .probe = ich6_gpio_probe,
  203. .priv_auto = sizeof(struct ich6_bank_priv),
  204. .plat_auto = sizeof(struct ich6_bank_plat),
  205. };