clk_kendryte.c 35 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
  4. */
  5. #define LOG_CATEGORY UCLASS_CLK
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <div64.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <mapmem.h>
  13. #include <serial.h>
  14. #include <dt-bindings/clock/k210-sysctl.h>
  15. #include <dt-bindings/mfd/k210-sysctl.h>
  16. #include <kendryte/pll.h>
  17. #include <linux/bitfield.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /**
  20. * struct k210_clk_priv - K210 clock driver private data
  21. * @base: The base address of the sysctl device
  22. * @in0: The "in0" external oscillator
  23. */
  24. struct k210_clk_priv {
  25. void __iomem *base;
  26. struct clk in0;
  27. };
  28. /*
  29. * All parameters for different sub-clocks are collected into parameter arrays.
  30. * These parameters are then initialized by the clock which uses them during
  31. * probe. To save space, ids are automatically generated for each sub-clock by
  32. * using an enum. Instead of storing a parameter struct for each clock, even for
  33. * those clocks which don't use a particular type of sub-clock, we can just
  34. * store the parameters for the clocks which need them.
  35. *
  36. * So why do it like this? Arranging all the sub-clocks together makes it very
  37. * easy to find bugs in the code.
  38. */
  39. /**
  40. * enum k210_clk_div_type - The type of divider
  41. * @K210_DIV_ONE: freq = parent / (reg + 1)
  42. * @K210_DIV_EVEN: freq = parent / 2 / (reg + 1)
  43. * @K210_DIV_POWER: freq = parent / (2 << reg)
  44. * @K210_DIV_FIXED: freq = parent / factor
  45. */
  46. enum k210_clk_div_type {
  47. K210_DIV_ONE,
  48. K210_DIV_EVEN,
  49. K210_DIV_POWER,
  50. K210_DIV_FIXED,
  51. };
  52. /**
  53. * struct k210_div_params - Parameters for dividing clocks
  54. * @type: An &enum k210_clk_div_type specifying the dividing formula
  55. * @off: The offset of the divider from the sysctl base address
  56. * @shift: The offset of the LSB of the divider
  57. * @width: The number of bits in the divider
  58. * @div: The fixed divisor for this divider
  59. */
  60. struct k210_div_params {
  61. u8 type;
  62. union {
  63. struct {
  64. u8 off;
  65. u8 shift;
  66. u8 width;
  67. };
  68. u8 div;
  69. };
  70. };
  71. #define DIV_LIST \
  72. DIV(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, K210_DIV_POWER) \
  73. DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3, K210_DIV_ONE) \
  74. DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3, K210_DIV_ONE) \
  75. DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3, K210_DIV_ONE) \
  76. DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4, K210_DIV_ONE) \
  77. DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4, K210_DIV_ONE) \
  78. DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4, K210_DIV_ONE) \
  79. DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4, K210_DIV_ONE) \
  80. DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4, K210_DIV_ONE) \
  81. DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8, K210_DIV_EVEN) \
  82. DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8, K210_DIV_EVEN) \
  83. DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8, K210_DIV_EVEN) \
  84. DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8, K210_DIV_EVEN) \
  85. DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8, K210_DIV_EVEN) \
  86. DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8, K210_DIV_EVEN) \
  87. DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8, K210_DIV_EVEN) \
  88. DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16, K210_DIV_EVEN) \
  89. DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16, K210_DIV_EVEN) \
  90. DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16, K210_DIV_EVEN) \
  91. DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8, K210_DIV_EVEN) \
  92. DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8, K210_DIV_EVEN) \
  93. DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8, K210_DIV_EVEN) \
  94. DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8, K210_DIV_EVEN) \
  95. DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8, K210_DIV_EVEN) \
  96. DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8, K210_DIV_EVEN) \
  97. DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8, K210_DIV_EVEN) \
  98. DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8, K210_DIV_EVEN) \
  99. DIV_FIXED(K210_CLK_CLINT, 50) \
  100. #define _DIVIFY(id) K210_CLK_DIV_##id
  101. #define DIVIFY(id) _DIVIFY(id)
  102. enum k210_div_id {
  103. #define DIV(id, ...) DIVIFY(id),
  104. #define DIV_FIXED DIV
  105. DIV_LIST
  106. #undef DIV
  107. #undef DIV_FIXED
  108. K210_CLK_DIV_NONE,
  109. };
  110. static const struct k210_div_params k210_divs[] = {
  111. #define DIV(id, _off, _shift, _width, _type) \
  112. [DIVIFY(id)] = { \
  113. .type = (_type), \
  114. .off = (_off), \
  115. .shift = (_shift), \
  116. .width = (_width), \
  117. },
  118. #define DIV_FIXED(id, _div) \
  119. [DIVIFY(id)] = { \
  120. .type = K210_DIV_FIXED, \
  121. .div = (_div) \
  122. },
  123. DIV_LIST
  124. #undef DIV
  125. #undef DIV_FIXED
  126. };
  127. #undef DIV
  128. #undef DIV_LIST
  129. /**
  130. * struct k210_gate_params - Parameters for gated clocks
  131. * @off: The offset of the gate from the sysctl base address
  132. * @bit_idx: The index of the bit within the register
  133. */
  134. struct k210_gate_params {
  135. u8 off;
  136. u8 bit_idx;
  137. };
  138. #define GATE_LIST \
  139. GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \
  140. GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \
  141. GATE(K210_CLK_SRAM1, K210_SYSCTL_EN_CENT, 2) \
  142. GATE(K210_CLK_APB0, K210_SYSCTL_EN_CENT, 3) \
  143. GATE(K210_CLK_APB1, K210_SYSCTL_EN_CENT, 4) \
  144. GATE(K210_CLK_APB2, K210_SYSCTL_EN_CENT, 5) \
  145. GATE(K210_CLK_ROM, K210_SYSCTL_EN_PERI, 0) \
  146. GATE(K210_CLK_DMA, K210_SYSCTL_EN_PERI, 1) \
  147. GATE(K210_CLK_AI, K210_SYSCTL_EN_PERI, 2) \
  148. GATE(K210_CLK_DVP, K210_SYSCTL_EN_PERI, 3) \
  149. GATE(K210_CLK_FFT, K210_SYSCTL_EN_PERI, 4) \
  150. GATE(K210_CLK_GPIO, K210_SYSCTL_EN_PERI, 5) \
  151. GATE(K210_CLK_SPI0, K210_SYSCTL_EN_PERI, 6) \
  152. GATE(K210_CLK_SPI1, K210_SYSCTL_EN_PERI, 7) \
  153. GATE(K210_CLK_SPI2, K210_SYSCTL_EN_PERI, 8) \
  154. GATE(K210_CLK_SPI3, K210_SYSCTL_EN_PERI, 9) \
  155. GATE(K210_CLK_I2S0, K210_SYSCTL_EN_PERI, 10) \
  156. GATE(K210_CLK_I2S1, K210_SYSCTL_EN_PERI, 11) \
  157. GATE(K210_CLK_I2S2, K210_SYSCTL_EN_PERI, 12) \
  158. GATE(K210_CLK_I2C0, K210_SYSCTL_EN_PERI, 13) \
  159. GATE(K210_CLK_I2C1, K210_SYSCTL_EN_PERI, 14) \
  160. GATE(K210_CLK_I2C2, K210_SYSCTL_EN_PERI, 15) \
  161. GATE(K210_CLK_UART1, K210_SYSCTL_EN_PERI, 16) \
  162. GATE(K210_CLK_UART2, K210_SYSCTL_EN_PERI, 17) \
  163. GATE(K210_CLK_UART3, K210_SYSCTL_EN_PERI, 18) \
  164. GATE(K210_CLK_AES, K210_SYSCTL_EN_PERI, 19) \
  165. GATE(K210_CLK_FPIOA, K210_SYSCTL_EN_PERI, 20) \
  166. GATE(K210_CLK_TIMER0, K210_SYSCTL_EN_PERI, 21) \
  167. GATE(K210_CLK_TIMER1, K210_SYSCTL_EN_PERI, 22) \
  168. GATE(K210_CLK_TIMER2, K210_SYSCTL_EN_PERI, 23) \
  169. GATE(K210_CLK_WDT0, K210_SYSCTL_EN_PERI, 24) \
  170. GATE(K210_CLK_WDT1, K210_SYSCTL_EN_PERI, 25) \
  171. GATE(K210_CLK_SHA, K210_SYSCTL_EN_PERI, 26) \
  172. GATE(K210_CLK_OTP, K210_SYSCTL_EN_PERI, 27) \
  173. GATE(K210_CLK_RTC, K210_SYSCTL_EN_PERI, 29)
  174. #define _GATEIFY(id) K210_CLK_GATE_##id
  175. #define GATEIFY(id) _GATEIFY(id)
  176. enum k210_gate_id {
  177. #define GATE(id, ...) GATEIFY(id),
  178. GATE_LIST
  179. #undef GATE
  180. K210_CLK_GATE_NONE,
  181. };
  182. static const struct k210_gate_params k210_gates[] = {
  183. #define GATE(id, _off, _idx) \
  184. [GATEIFY(id)] = { \
  185. .off = (_off), \
  186. .bit_idx = (_idx), \
  187. },
  188. GATE_LIST
  189. #undef GATE
  190. };
  191. #undef GATE_LIST
  192. /* The most parents is PLL2 */
  193. #define K210_CLK_MAX_PARENTS 3
  194. /**
  195. * struct k210_mux_params - Parameters for muxed clocks
  196. * @parents: A list of parent clock ids
  197. * @num_parents: The number of parent clocks
  198. * @off: The offset of the mux from the base sysctl address
  199. * @shift: The offset of the LSB of the mux selector
  200. * @width: The number of bits in the mux selector
  201. */
  202. struct k210_mux_params {
  203. u8 parents[K210_CLK_MAX_PARENTS];
  204. u8 num_parents;
  205. u8 off;
  206. u8 shift;
  207. u8 width;
  208. };
  209. #define MUX(id, reg, shift, width) \
  210. MUX_PARENTS(id, reg, shift, width, K210_CLK_IN0, K210_CLK_PLL0)
  211. #define MUX_LIST \
  212. MUX_PARENTS(K210_CLK_PLL2, K210_SYSCTL_PLL2, 26, 2, \
  213. K210_CLK_IN0, K210_CLK_PLL0, K210_CLK_PLL1) \
  214. MUX(K210_CLK_ACLK, K210_SYSCTL_SEL0, 0, 1) \
  215. MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \
  216. MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \
  217. MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \
  218. MUX(K210_CLK_TIMER2, K210_SYSCTL_SEL0, 15, 1)
  219. #define _MUXIFY(id) K210_CLK_MUX_##id
  220. #define MUXIFY(id) _MUXIFY(id)
  221. enum k210_mux_id {
  222. #define MUX_PARENTS(id, ...) MUXIFY(id),
  223. MUX_LIST
  224. #undef MUX_PARENTS
  225. K210_CLK_MUX_NONE,
  226. };
  227. static const struct k210_mux_params k210_muxes[] = {
  228. #define MUX_PARENTS(id, _off, _shift, _width, ...) \
  229. [MUXIFY(id)] = { \
  230. .parents = { __VA_ARGS__ }, \
  231. .num_parents = __count_args(__VA_ARGS__), \
  232. .off = (_off), \
  233. .shift = (_shift), \
  234. .width = (_width), \
  235. },
  236. MUX_LIST
  237. #undef MUX_PARENTS
  238. };
  239. #undef MUX
  240. #undef MUX_LIST
  241. /**
  242. * struct k210_pll_params - K210 PLL parameters
  243. * @off: The offset of the PLL from the base sysctl address
  244. * @shift: The offset of the LSB of the lock status
  245. * @width: The number of bits in the lock status
  246. */
  247. struct k210_pll_params {
  248. u8 off;
  249. u8 shift;
  250. u8 width;
  251. };
  252. static const struct k210_pll_params k210_plls[] = {
  253. #define PLL(_off, _shift, _width) { \
  254. .off = (_off), \
  255. .shift = (_shift), \
  256. .width = (_width), \
  257. }
  258. [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
  259. [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
  260. [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
  261. #undef PLL
  262. };
  263. /**
  264. * enum k210_clk_flags - The type of a K210 clock
  265. * @K210_CLKF_MUX: This clock has a mux and not a static parent
  266. * @K210_CLKF_PLL: This clock is a PLL
  267. */
  268. enum k210_clk_flags {
  269. K210_CLKF_MUX = BIT(0),
  270. K210_CLKF_PLL = BIT(1),
  271. };
  272. /**
  273. * struct k210_clk_params - The parameters defining a K210 clock
  274. * @name: The name of the clock
  275. * @flags: A set of &enum k210_clk_flags defining which fields are valid
  276. * @mux: An &enum k210_mux_id of this clock's mux
  277. * @parent: The clock id of this clock's parent
  278. * @pll: The id of the PLL (if this clock is a PLL)
  279. * @div: An &enum k210_div_id of this clock's divider
  280. * @gate: An &enum k210_gate_id of this clock's gate
  281. */
  282. struct k210_clk_params {
  283. #if CONFIG_IS_ENABLED(CMD_CLK)
  284. const char *name;
  285. #endif
  286. u8 flags;
  287. union {
  288. u8 parent;
  289. u8 mux;
  290. };
  291. union {
  292. u8 pll;
  293. struct {
  294. u8 div;
  295. u8 gate;
  296. };
  297. };
  298. };
  299. static const struct k210_clk_params k210_clks[] = {
  300. #if CONFIG_IS_ENABLED(CMD_CLK)
  301. #define NAME(_name) .name = (_name),
  302. #else
  303. #define NAME(name)
  304. #endif
  305. #define CLK(id, _name, _parent, _div, _gate) \
  306. [id] = { \
  307. NAME(_name) \
  308. .parent = (_parent), \
  309. .div = (_div), \
  310. .gate = (_gate), \
  311. }
  312. #define CLK_MUX(id, _name, _mux, _div, _gate) \
  313. [id] = { \
  314. NAME(_name) \
  315. .flags = K210_CLKF_MUX, \
  316. .mux = (_mux), \
  317. .div = (_div), \
  318. .gate = (_gate), \
  319. }
  320. #define CLK_PLL(id, _pll, _parent) \
  321. [id] = { \
  322. NAME("pll" #_pll) \
  323. .flags = K210_CLKF_PLL, \
  324. .parent = (_parent), \
  325. .pll = (_pll), \
  326. }
  327. #define CLK_FULL(id, name) \
  328. CLK_MUX(id, name, MUXIFY(id), DIVIFY(id), GATEIFY(id))
  329. #define CLK_NOMUX(id, name, parent) \
  330. CLK(id, name, parent, DIVIFY(id), GATEIFY(id))
  331. #define CLK_DIV(id, name, parent) \
  332. CLK(id, name, parent, DIVIFY(id), K210_CLK_GATE_NONE)
  333. #define CLK_GATE(id, name, parent) \
  334. CLK(id, name, parent, K210_CLK_DIV_NONE, GATEIFY(id))
  335. CLK_PLL(K210_CLK_PLL0, 0, K210_CLK_IN0),
  336. CLK_PLL(K210_CLK_PLL1, 1, K210_CLK_IN0),
  337. [K210_CLK_PLL2] = {
  338. NAME("pll2")
  339. .flags = K210_CLKF_MUX | K210_CLKF_PLL,
  340. .mux = MUXIFY(K210_CLK_PLL2),
  341. .pll = 2,
  342. },
  343. CLK_MUX(K210_CLK_ACLK, "aclk", MUXIFY(K210_CLK_ACLK),
  344. DIVIFY(K210_CLK_ACLK), K210_CLK_GATE_NONE),
  345. CLK_FULL(K210_CLK_SPI3, "spi3"),
  346. CLK_FULL(K210_CLK_TIMER0, "timer0"),
  347. CLK_FULL(K210_CLK_TIMER1, "timer1"),
  348. CLK_FULL(K210_CLK_TIMER2, "timer2"),
  349. CLK_NOMUX(K210_CLK_SRAM0, "sram0", K210_CLK_ACLK),
  350. CLK_NOMUX(K210_CLK_SRAM1, "sram1", K210_CLK_ACLK),
  351. CLK_NOMUX(K210_CLK_ROM, "rom", K210_CLK_ACLK),
  352. CLK_NOMUX(K210_CLK_DVP, "dvp", K210_CLK_ACLK),
  353. CLK_NOMUX(K210_CLK_APB0, "apb0", K210_CLK_ACLK),
  354. CLK_NOMUX(K210_CLK_APB1, "apb1", K210_CLK_ACLK),
  355. CLK_NOMUX(K210_CLK_APB2, "apb2", K210_CLK_ACLK),
  356. CLK_NOMUX(K210_CLK_AI, "ai", K210_CLK_PLL1),
  357. CLK_NOMUX(K210_CLK_I2S0, "i2s0", K210_CLK_PLL2),
  358. CLK_NOMUX(K210_CLK_I2S1, "i2s1", K210_CLK_PLL2),
  359. CLK_NOMUX(K210_CLK_I2S2, "i2s2", K210_CLK_PLL2),
  360. CLK_NOMUX(K210_CLK_WDT0, "wdt0", K210_CLK_IN0),
  361. CLK_NOMUX(K210_CLK_WDT1, "wdt1", K210_CLK_IN0),
  362. CLK_NOMUX(K210_CLK_SPI0, "spi0", K210_CLK_PLL0),
  363. CLK_NOMUX(K210_CLK_SPI1, "spi1", K210_CLK_PLL0),
  364. CLK_NOMUX(K210_CLK_SPI2, "spi2", K210_CLK_PLL0),
  365. CLK_NOMUX(K210_CLK_I2C0, "i2c0", K210_CLK_PLL0),
  366. CLK_NOMUX(K210_CLK_I2C1, "i2c1", K210_CLK_PLL0),
  367. CLK_NOMUX(K210_CLK_I2C2, "i2c2", K210_CLK_PLL0),
  368. CLK_DIV(K210_CLK_I2S0_M, "i2s0_m", K210_CLK_PLL2),
  369. CLK_DIV(K210_CLK_I2S1_M, "i2s1_m", K210_CLK_PLL2),
  370. CLK_DIV(K210_CLK_I2S2_M, "i2s2_m", K210_CLK_PLL2),
  371. CLK_DIV(K210_CLK_CLINT, "clint", K210_CLK_ACLK),
  372. CLK_GATE(K210_CLK_CPU, "cpu", K210_CLK_ACLK),
  373. CLK_GATE(K210_CLK_DMA, "dma", K210_CLK_ACLK),
  374. CLK_GATE(K210_CLK_FFT, "fft", K210_CLK_ACLK),
  375. CLK_GATE(K210_CLK_GPIO, "gpio", K210_CLK_APB0),
  376. CLK_GATE(K210_CLK_UART1, "uart1", K210_CLK_APB0),
  377. CLK_GATE(K210_CLK_UART2, "uart2", K210_CLK_APB0),
  378. CLK_GATE(K210_CLK_UART3, "uart3", K210_CLK_APB0),
  379. CLK_GATE(K210_CLK_FPIOA, "fpioa", K210_CLK_APB0),
  380. CLK_GATE(K210_CLK_SHA, "sha", K210_CLK_APB0),
  381. CLK_GATE(K210_CLK_AES, "aes", K210_CLK_APB1),
  382. CLK_GATE(K210_CLK_OTP, "otp", K210_CLK_APB1),
  383. CLK_GATE(K210_CLK_RTC, "rtc", K210_CLK_IN0),
  384. #undef NAME
  385. #undef CLK_PLL
  386. #undef CLK
  387. #undef CLK_FULL
  388. #undef CLK_NOMUX
  389. #undef CLK_DIV
  390. #undef CLK_GATE
  391. #undef CLK_LIST
  392. };
  393. #define K210_PLL_CLKR GENMASK(3, 0)
  394. #define K210_PLL_CLKF GENMASK(9, 4)
  395. #define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
  396. #define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
  397. #define K210_PLL_RESET BIT(20)
  398. #define K210_PLL_PWRD BIT(21) /* PoWeReD */
  399. #define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
  400. #define K210_PLL_BYPASS BIT(23)
  401. #define K210_PLL_TEST BIT(24)
  402. #define K210_PLL_EN BIT(25)
  403. #define K210_PLL_TEST_EN BIT(26)
  404. #define K210_PLL_LOCK 0
  405. #define K210_PLL_CLEAR_SLIP 2
  406. #define K210_PLL_TEST_OUT 3
  407. #ifdef CONFIG_CLK_K210_SET_RATE
  408. static int k210_pll_enable(struct k210_clk_priv *priv, int id);
  409. static int k210_pll_disable(struct k210_clk_priv *priv, int id);
  410. static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in);
  411. /*
  412. * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
  413. * General-Purpose PLL. The logical layout of the PLL with internal feedback is
  414. * approximately the following:
  415. *
  416. * +---------------+
  417. * |reference clock|
  418. * +---------------+
  419. * |
  420. * v
  421. * +--+
  422. * |/r|
  423. * +--+
  424. * |
  425. * v
  426. * +-------------+
  427. * |divided clock|
  428. * +-------------+
  429. * |
  430. * v
  431. * +--------------+
  432. * |phase detector|<---+
  433. * +--------------+ |
  434. * | |
  435. * v +--------------+
  436. * +---+ |feedback clock|
  437. * |VCO| +--------------+
  438. * +---+ ^
  439. * | +--+ |
  440. * +--->|/f|---+
  441. * | +--+
  442. * v
  443. * +---+
  444. * |/od|
  445. * +---+
  446. * |
  447. * v
  448. * +------+
  449. * |output|
  450. * +------+
  451. *
  452. * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
  453. * the effect of the division by f is to multiply the input frequency. The
  454. * equation for the output rate is
  455. * rate = (rate_in * f) / (r * od).
  456. * Moving knowns to one side of the equation, we get
  457. * rate / rate_in = f / (r * od)
  458. * Rearranging slightly,
  459. * abs_error = abs((rate / rate_in) - (f / (r * od))).
  460. * To get relative, error, we divide by the expected ratio
  461. * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
  462. * Simplifying,
  463. * error = abs(1 - f / (r * od)) / (rate / rate_in)
  464. * error = abs(1 - (f * rate_in) / (r * od * rate))
  465. * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
  466. * error = abs((f * inv_ratio) / (r * od) - 1)
  467. * This is the error used in evaluating parameters.
  468. *
  469. * r and od are four bits each, while f is six bits. Because r and od are
  470. * multiplied together, instead of the full 256 values possible if both bits
  471. * were used fully, there are only 97 distinct products. Combined with f, there
  472. * are 6208 theoretical settings for the PLL. However, most of these settings
  473. * can be ruled out immediately because they do not have the correct ratio.
  474. *
  475. * In addition to the constraint of approximating the desired ratio, parameters
  476. * must also keep internal pll frequencies within acceptable ranges. The divided
  477. * clock's minimum and maximum frequencies have a ratio of around 128. This
  478. * leaves fairly substantial room to work with, especially since the only
  479. * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
  480. * of 5, which is considerably more restrictive.
  481. *
  482. * The r and od factors are stored in a table. This is to make it easy to find
  483. * the next-largest product. Some products have multiple factorizations, but
  484. * only when one factor has at least a 2.5x ratio to the factors of the other
  485. * factorization. This is because any smaller ratio would not make a difference
  486. * when ensuring the VCO's frequency is within spec.
  487. *
  488. * Throughout the calculation function, fixed point arithmetic is used. Because
  489. * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
  490. * 32.32 fixed-point numbers are used to represent ratios. In general, to
  491. * implement division, the numerator is first multiplied by 2^32. This gives a
  492. * result where the whole number part is in the upper 32 bits, and the fraction
  493. * is in the lower 32 bits.
  494. *
  495. * In general, rounding is done to the closest integer. This helps find the best
  496. * approximation for the ratio. Rounding in one direction (e.g down) could cause
  497. * the function to miss a better ratio with one of the parameters increased by
  498. * one.
  499. */
  500. /*
  501. * The factors table was generated with the following python code:
  502. *
  503. * def p(x, y):
  504. * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
  505. *
  506. * factors = {}
  507. * for i in range(1, 17):
  508. * for j in range(1, 17):
  509. * fs = factors.get(i*j) or []
  510. * if fs == [] or all([
  511. * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
  512. * for (x, y) in fs]):
  513. * fs.append((i, j))
  514. * factors[i*j] = fs
  515. *
  516. * for k, l in sorted(factors.items()):
  517. * for v in l:
  518. * print("PACK(%s, %s)," % v)
  519. */
  520. #define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
  521. #define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
  522. #define UNPACK_OD(val) (((val) & 0xF) + 1)
  523. static const u8 factors[] = {
  524. PACK(1, 1),
  525. PACK(1, 2),
  526. PACK(1, 3),
  527. PACK(1, 4),
  528. PACK(1, 5),
  529. PACK(1, 6),
  530. PACK(1, 7),
  531. PACK(1, 8),
  532. PACK(1, 9),
  533. PACK(3, 3),
  534. PACK(1, 10),
  535. PACK(1, 11),
  536. PACK(1, 12),
  537. PACK(3, 4),
  538. PACK(1, 13),
  539. PACK(1, 14),
  540. PACK(1, 15),
  541. PACK(3, 5),
  542. PACK(1, 16),
  543. PACK(4, 4),
  544. PACK(2, 9),
  545. PACK(2, 10),
  546. PACK(3, 7),
  547. PACK(2, 11),
  548. PACK(2, 12),
  549. PACK(5, 5),
  550. PACK(2, 13),
  551. PACK(3, 9),
  552. PACK(2, 14),
  553. PACK(2, 15),
  554. PACK(2, 16),
  555. PACK(3, 11),
  556. PACK(5, 7),
  557. PACK(3, 12),
  558. PACK(3, 13),
  559. PACK(4, 10),
  560. PACK(3, 14),
  561. PACK(4, 11),
  562. PACK(3, 15),
  563. PACK(3, 16),
  564. PACK(7, 7),
  565. PACK(5, 10),
  566. PACK(4, 13),
  567. PACK(6, 9),
  568. PACK(5, 11),
  569. PACK(4, 14),
  570. PACK(4, 15),
  571. PACK(7, 9),
  572. PACK(4, 16),
  573. PACK(5, 13),
  574. PACK(6, 11),
  575. PACK(5, 14),
  576. PACK(6, 12),
  577. PACK(5, 15),
  578. PACK(7, 11),
  579. PACK(6, 13),
  580. PACK(5, 16),
  581. PACK(9, 9),
  582. PACK(6, 14),
  583. PACK(8, 11),
  584. PACK(6, 15),
  585. PACK(7, 13),
  586. PACK(6, 16),
  587. PACK(7, 14),
  588. PACK(9, 11),
  589. PACK(10, 10),
  590. PACK(8, 13),
  591. PACK(7, 15),
  592. PACK(9, 12),
  593. PACK(10, 11),
  594. PACK(7, 16),
  595. PACK(9, 13),
  596. PACK(8, 15),
  597. PACK(11, 11),
  598. PACK(9, 14),
  599. PACK(8, 16),
  600. PACK(10, 13),
  601. PACK(11, 12),
  602. PACK(9, 15),
  603. PACK(10, 14),
  604. PACK(11, 13),
  605. PACK(9, 16),
  606. PACK(10, 15),
  607. PACK(11, 14),
  608. PACK(12, 13),
  609. PACK(10, 16),
  610. PACK(11, 15),
  611. PACK(12, 14),
  612. PACK(13, 13),
  613. PACK(11, 16),
  614. PACK(12, 15),
  615. PACK(13, 14),
  616. PACK(12, 16),
  617. PACK(13, 15),
  618. PACK(14, 14),
  619. PACK(13, 16),
  620. PACK(14, 15),
  621. PACK(14, 16),
  622. PACK(15, 15),
  623. PACK(15, 16),
  624. PACK(16, 16),
  625. };
  626. TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
  627. struct k210_pll_config *best)
  628. {
  629. int i;
  630. s64 error, best_error;
  631. u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
  632. u64 max_r;
  633. u64 r, f, od;
  634. /*
  635. * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
  636. * VCO frequency. These are not the same limits as below because od can
  637. * reduce the output frequency by 16.
  638. */
  639. if (rate > 1750000000 || rate < 21250000)
  640. return -EINVAL;
  641. /* Similar restrictions on the input rate */
  642. if (rate_in > 1750000000 || rate_in < 13300000)
  643. return -EINVAL;
  644. ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
  645. inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
  646. /* Can't increase by more than 64 or reduce by more than 256 */
  647. if (rate > rate_in && ratio > (64ULL << 32))
  648. return -EINVAL;
  649. else if (rate <= rate_in && inv_ratio > (256ULL << 32))
  650. return -EINVAL;
  651. /*
  652. * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
  653. * MHz. There is no minimum, since the only way to get a higher input
  654. * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
  655. * cannot output frequencies greater than 1.75 GHz, the minimum would
  656. * never be greater than one.
  657. */
  658. max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
  659. /* Variables get immediately incremented, so start at -1th iteration */
  660. i = -1;
  661. f = 0;
  662. r = 0;
  663. od = 0;
  664. best_error = S64_MAX;
  665. error = best_error;
  666. /* do-while here so we always try at least one ratio */
  667. do {
  668. /*
  669. * Whether we swapped r and od while enforcing frequency limits
  670. */
  671. bool swapped = false;
  672. u64 last_od = od;
  673. u64 last_r = r;
  674. /*
  675. * Try the next largest value for f (or r and od) and
  676. * recalculate the other parameters based on that
  677. */
  678. if (rate > rate_in) {
  679. /*
  680. * Skip factors of the same product if we already tried
  681. * out that product
  682. */
  683. do {
  684. i++;
  685. r = UNPACK_R(factors[i]);
  686. od = UNPACK_OD(factors[i]);
  687. } while (i + 1 < ARRAY_SIZE(factors) &&
  688. r * od == last_r * last_od);
  689. /* Round close */
  690. f = (r * od * ratio + BIT(31)) >> 32;
  691. if (f > 64)
  692. f = 64;
  693. } else {
  694. u64 tmp = ++f * inv_ratio;
  695. bool round_up = !!(tmp & BIT(31));
  696. u32 goal = (tmp >> 32) + round_up;
  697. u32 err, last_err;
  698. /* Get the next r/od pair in factors */
  699. while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
  700. i++;
  701. r = UNPACK_R(factors[i]);
  702. od = UNPACK_OD(factors[i]);
  703. }
  704. /*
  705. * This is a case of double rounding. If we rounded up
  706. * above, we need to round down (in cases of ties) here.
  707. * This prevents off-by-one errors resulting from
  708. * choosing X+2 over X when X.Y rounds up to X+1 and
  709. * there is no r * od = X+1. For the converse, when X.Y
  710. * is rounded down to X, we should choose X+1 over X-1.
  711. */
  712. err = abs(r * od - goal);
  713. last_err = abs(last_r * last_od - goal);
  714. if (last_err < err || (round_up && last_err == err)) {
  715. i--;
  716. r = last_r;
  717. od = last_od;
  718. }
  719. }
  720. /*
  721. * Enforce limits on internal clock frequencies. If we
  722. * aren't in spec, try swapping r and od. If everything is
  723. * in-spec, calculate the relative error.
  724. */
  725. while (true) {
  726. /*
  727. * Whether the intermediate frequencies are out-of-spec
  728. */
  729. bool out_of_spec = false;
  730. if (r > max_r) {
  731. out_of_spec = true;
  732. } else {
  733. /*
  734. * There is no way to only divide once; we need
  735. * to examine the frequency with and without the
  736. * effect of od.
  737. */
  738. u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
  739. if (vco > 1750000000 || vco < 340000000)
  740. out_of_spec = true;
  741. }
  742. if (out_of_spec) {
  743. if (!swapped) {
  744. u64 tmp = r;
  745. r = od;
  746. od = tmp;
  747. swapped = true;
  748. continue;
  749. } else {
  750. /*
  751. * Try looking ahead to see if there are
  752. * additional factors for the same
  753. * product.
  754. */
  755. if (i + 1 < ARRAY_SIZE(factors)) {
  756. u64 new_r, new_od;
  757. i++;
  758. new_r = UNPACK_R(factors[i]);
  759. new_od = UNPACK_OD(factors[i]);
  760. if (r * od == new_r * new_od) {
  761. r = new_r;
  762. od = new_od;
  763. swapped = false;
  764. continue;
  765. }
  766. i--;
  767. }
  768. break;
  769. }
  770. }
  771. error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
  772. /* The lower 16 bits are spurious */
  773. error = abs((error - BIT(32))) >> 16;
  774. if (error < best_error) {
  775. best->r = r;
  776. best->f = f;
  777. best->od = od;
  778. best_error = error;
  779. }
  780. break;
  781. }
  782. } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
  783. if (best_error == S64_MAX)
  784. return -EINVAL;
  785. log_debug("best error %lld\n", best_error);
  786. return 0;
  787. }
  788. static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
  789. ulong rate_in)
  790. {
  791. int err;
  792. const struct k210_pll_params *pll = &k210_plls[id];
  793. struct k210_pll_config config = {};
  794. u32 reg;
  795. ulong calc_rate;
  796. if (rate_in < 0)
  797. return rate_in;
  798. err = k210_pll_calc_config(rate, rate_in, &config);
  799. if (err)
  800. return err;
  801. log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
  802. /* Don't bother setting the rate if we're already at that rate */
  803. calc_rate = DIV_ROUND_DOWN_ULL(((u64)rate_in) * config.f,
  804. config.r * config.od);
  805. if (calc_rate == k210_pll_get_rate(priv, id, rate))
  806. return calc_rate;
  807. k210_pll_disable(priv, id);
  808. reg = readl(priv->base + pll->off);
  809. reg &= ~K210_PLL_CLKR
  810. & ~K210_PLL_CLKF
  811. & ~K210_PLL_CLKOD
  812. & ~K210_PLL_BWADJ;
  813. reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
  814. | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
  815. | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
  816. | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
  817. writel(reg, priv->base + pll->off);
  818. k210_pll_enable(priv, id);
  819. serial_setbrg();
  820. return k210_pll_get_rate(priv, id, rate);
  821. }
  822. #else
  823. static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
  824. ulong rate_in)
  825. {
  826. return -ENOSYS;
  827. }
  828. #endif /* CONFIG_CLK_K210_SET_RATE */
  829. static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id,
  830. ulong rate_in)
  831. {
  832. u64 r, f, od;
  833. u32 reg = readl(priv->base + k210_plls[id].off);
  834. if (rate_in < 0 || (reg & K210_PLL_BYPASS))
  835. return rate_in;
  836. if (!(reg & K210_PLL_PWRD))
  837. return 0;
  838. r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
  839. f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
  840. od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
  841. return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
  842. }
  843. /*
  844. * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
  845. * slip before retrying
  846. */
  847. static void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id)
  848. {
  849. const struct k210_pll_params *pll = &k210_plls[id];
  850. u32 mask = (BIT(pll->width) - 1) << pll->shift;
  851. while (true) {
  852. u32 reg = readl(priv->base + K210_SYSCTL_PLL_LOCK);
  853. if ((reg & mask) == mask)
  854. break;
  855. reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
  856. writel(reg, priv->base + K210_SYSCTL_PLL_LOCK);
  857. }
  858. }
  859. static bool k210_pll_enabled(u32 reg)
  860. {
  861. return (reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
  862. !(reg & K210_PLL_RESET);
  863. }
  864. /* Adapted from sysctl_pll_enable */
  865. static int k210_pll_enable(struct k210_clk_priv *priv, int id)
  866. {
  867. const struct k210_pll_params *pll = &k210_plls[id];
  868. u32 reg = readl(priv->base + pll->off);
  869. if (k210_pll_enabled(reg))
  870. return 0;
  871. reg |= K210_PLL_PWRD;
  872. writel(reg, priv->base + pll->off);
  873. /* Ensure reset is low before asserting it */
  874. reg &= ~K210_PLL_RESET;
  875. writel(reg, priv->base + pll->off);
  876. reg |= K210_PLL_RESET;
  877. writel(reg, priv->base + pll->off);
  878. nop();
  879. nop();
  880. reg &= ~K210_PLL_RESET;
  881. writel(reg, priv->base + pll->off);
  882. k210_pll_waitfor_lock(priv, id);
  883. reg &= ~K210_PLL_BYPASS;
  884. reg |= K210_PLL_EN;
  885. writel(reg, priv->base + pll->off);
  886. return 0;
  887. }
  888. static int k210_pll_disable(struct k210_clk_priv *priv, int id)
  889. {
  890. const struct k210_pll_params *pll = &k210_plls[id];
  891. u32 reg = readl(priv->base + pll->off);
  892. /*
  893. * Bypassing before powering off is important so child clocks don't stop
  894. * working. This is especially important for pll0, the indirect parent
  895. * of the cpu clock.
  896. */
  897. reg |= K210_PLL_BYPASS;
  898. writel(reg, priv->base + pll->off);
  899. reg &= ~K210_PLL_PWRD;
  900. reg &= ~K210_PLL_EN;
  901. writel(reg, priv->base + pll->off);
  902. return 0;
  903. }
  904. static u32 k210_clk_readl(struct k210_clk_priv *priv, u8 off, u8 shift,
  905. u8 width)
  906. {
  907. u32 reg = readl(priv->base + off);
  908. return (reg >> shift) & (BIT(width) - 1);
  909. }
  910. static void k210_clk_writel(struct k210_clk_priv *priv, u8 off, u8 shift,
  911. u8 width, u32 val)
  912. {
  913. u32 reg = readl(priv->base + off);
  914. u32 mask = (BIT(width) - 1) << shift;
  915. reg &= ~mask;
  916. reg |= mask & (val << shift);
  917. writel(reg, priv->base + off);
  918. }
  919. static int k210_clk_get_parent(struct k210_clk_priv *priv, int id)
  920. {
  921. u32 sel;
  922. const struct k210_mux_params *mux;
  923. if (!(k210_clks[id].flags & K210_CLKF_MUX))
  924. return k210_clks[id].parent;
  925. mux = &k210_muxes[k210_clks[id].mux];
  926. sel = k210_clk_readl(priv, mux->off, mux->shift, mux->width);
  927. assert(sel < mux->num_parents);
  928. return mux->parents[sel];
  929. }
  930. static ulong do_k210_clk_get_rate(struct k210_clk_priv *priv, int id)
  931. {
  932. int parent;
  933. u32 val;
  934. ulong parent_rate;
  935. const struct k210_div_params *div;
  936. if (id == K210_CLK_IN0)
  937. return clk_get_rate(&priv->in0);
  938. parent = k210_clk_get_parent(priv, id);
  939. parent_rate = do_k210_clk_get_rate(priv, parent);
  940. if (k210_clks[id].flags & K210_CLKF_PLL)
  941. return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate);
  942. if (k210_clks[id].div == K210_CLK_DIV_NONE)
  943. return parent_rate;
  944. div = &k210_divs[k210_clks[id].div];
  945. if (div->type == K210_DIV_FIXED)
  946. return parent_rate / div->div;
  947. val = k210_clk_readl(priv, div->off, div->shift, div->width);
  948. switch (div->type) {
  949. case K210_DIV_ONE:
  950. return parent_rate / (val + 1);
  951. case K210_DIV_EVEN:
  952. return parent_rate / 2 / (val + 1);
  953. case K210_DIV_POWER:
  954. /* This is ACLK, which has no divider on IN0 */
  955. if (parent == K210_CLK_IN0)
  956. return parent_rate;
  957. return parent_rate / (2 << val);
  958. default:
  959. assert(false);
  960. return -EINVAL;
  961. };
  962. }
  963. static ulong k210_clk_get_rate(struct clk *clk)
  964. {
  965. return do_k210_clk_get_rate(dev_get_priv(clk->dev), clk->id);
  966. }
  967. static int do_k210_clk_set_parent(struct k210_clk_priv *priv, int id, int new)
  968. {
  969. int i;
  970. const struct k210_mux_params *mux;
  971. if (!(k210_clks[id].flags & K210_CLKF_MUX))
  972. return -ENOSYS;
  973. mux = &k210_muxes[k210_clks[id].mux];
  974. for (i = 0; i < mux->num_parents; i++) {
  975. if (mux->parents[i] == new) {
  976. k210_clk_writel(priv, mux->off, mux->shift, mux->width,
  977. i);
  978. return 0;
  979. }
  980. }
  981. return -EINVAL;
  982. }
  983. static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
  984. {
  985. return do_k210_clk_set_parent(dev_get_priv(clk->dev), clk->id,
  986. parent->id);
  987. }
  988. static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
  989. {
  990. int parent, ret, err;
  991. ulong rate_in, val;
  992. const struct k210_div_params *div;
  993. struct k210_clk_priv *priv = dev_get_priv(clk->dev);
  994. if (clk->id == K210_CLK_IN0)
  995. return clk_set_rate(&priv->in0, rate);
  996. parent = k210_clk_get_parent(priv, clk->id);
  997. rate_in = do_k210_clk_get_rate(priv, parent);
  998. log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in);
  999. if (clk->id == K210_CLK_PLL0) {
  1000. /* Bypass ACLK so the CPU keeps going */
  1001. ret = do_k210_clk_set_parent(priv, K210_CLK_ACLK, K210_CLK_IN0);
  1002. if (ret)
  1003. return ret;
  1004. } else if (clk->id == K210_CLK_PLL1 && gd->flags & GD_FLG_RELOC) {
  1005. /*
  1006. * We can't bypass the AI clock like we can ACLK, and after
  1007. * relocation we are using the AI ram.
  1008. */
  1009. return -EPERM;
  1010. }
  1011. if (k210_clks[clk->id].flags & K210_CLKF_PLL) {
  1012. ret = k210_pll_set_rate(priv, k210_clks[clk->id].pll, rate,
  1013. rate_in);
  1014. if (!IS_ERR_VALUE(ret) && clk->id == K210_CLK_PLL0) {
  1015. /*
  1016. * This may have the side effect of reparenting ACLK,
  1017. * but I don't really want to keep track of what the old
  1018. * parent was.
  1019. */
  1020. err = do_k210_clk_set_parent(priv, K210_CLK_ACLK,
  1021. K210_CLK_PLL0);
  1022. if (err)
  1023. return err;
  1024. }
  1025. return ret;
  1026. }
  1027. if (k210_clks[clk->id].div == K210_CLK_DIV_NONE)
  1028. return -ENOSYS;
  1029. div = &k210_divs[k210_clks[clk->id].div];
  1030. switch (div->type) {
  1031. case K210_DIV_ONE:
  1032. val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate);
  1033. val = val ? val - 1 : 0;
  1034. break;
  1035. case K210_DIV_EVEN:
  1036. val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, 2 * rate);
  1037. break;
  1038. case K210_DIV_POWER:
  1039. /* This is ACLK, which has no divider on IN0 */
  1040. if (parent == K210_CLK_IN0)
  1041. return -ENOSYS;
  1042. val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate);
  1043. val = __ffs(val);
  1044. break;
  1045. default:
  1046. assert(false);
  1047. return -EINVAL;
  1048. };
  1049. val = val ? val - 1 : 0;
  1050. k210_clk_writel(priv, div->off, div->shift, div->width, val);
  1051. return do_k210_clk_get_rate(priv, clk->id);
  1052. }
  1053. static int k210_clk_endisable(struct k210_clk_priv *priv, int id, bool enable)
  1054. {
  1055. int parent = k210_clk_get_parent(priv, id);
  1056. const struct k210_gate_params *gate;
  1057. if (id == K210_CLK_IN0) {
  1058. if (enable)
  1059. return clk_enable(&priv->in0);
  1060. else
  1061. return clk_disable(&priv->in0);
  1062. }
  1063. /* Only recursively enable clocks since we don't track refcounts */
  1064. if (enable) {
  1065. int ret = k210_clk_endisable(priv, parent, true);
  1066. if (ret && ret != -ENOSYS)
  1067. return ret;
  1068. }
  1069. if (k210_clks[id].flags & K210_CLKF_PLL) {
  1070. if (enable)
  1071. return k210_pll_enable(priv, k210_clks[id].pll);
  1072. else
  1073. return k210_pll_disable(priv, k210_clks[id].pll);
  1074. }
  1075. if (k210_clks[id].gate == K210_CLK_GATE_NONE)
  1076. return -ENOSYS;
  1077. gate = &k210_gates[k210_clks[id].gate];
  1078. k210_clk_writel(priv, gate->off, gate->bit_idx, 1, enable);
  1079. return 0;
  1080. }
  1081. static int k210_clk_enable(struct clk *clk)
  1082. {
  1083. return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, true);
  1084. }
  1085. static int k210_clk_disable(struct clk *clk)
  1086. {
  1087. return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, false);
  1088. }
  1089. static int k210_clk_request(struct clk *clk)
  1090. {
  1091. if (clk->id >= ARRAY_SIZE(k210_clks))
  1092. return -EINVAL;
  1093. return 0;
  1094. }
  1095. static const struct clk_ops k210_clk_ops = {
  1096. .request = k210_clk_request,
  1097. .set_rate = k210_clk_set_rate,
  1098. .get_rate = k210_clk_get_rate,
  1099. .set_parent = k210_clk_set_parent,
  1100. .enable = k210_clk_enable,
  1101. .disable = k210_clk_disable,
  1102. };
  1103. static int k210_clk_probe(struct udevice *dev)
  1104. {
  1105. int ret;
  1106. struct k210_clk_priv *priv = dev_get_priv(dev);
  1107. priv->base = dev_read_addr_ptr(dev_get_parent(dev));
  1108. if (!priv->base)
  1109. return -EINVAL;
  1110. ret = clk_get_by_index(dev, 0, &priv->in0);
  1111. if (ret)
  1112. return ret;
  1113. /*
  1114. * Force setting defaults, even before relocation. This is so we can
  1115. * set the clock rate for PLL1 before we relocate into aisram.
  1116. */
  1117. if (!(gd->flags & GD_FLG_RELOC))
  1118. clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
  1119. return 0;
  1120. }
  1121. static const struct udevice_id k210_clk_ids[] = {
  1122. { .compatible = "kendryte,k210-clk" },
  1123. { },
  1124. };
  1125. U_BOOT_DRIVER(k210_clk) = {
  1126. .name = "k210_clk",
  1127. .id = UCLASS_CLK,
  1128. .of_match = k210_clk_ids,
  1129. .ops = &k210_clk_ops,
  1130. .probe = k210_clk_probe,
  1131. .priv_auto = sizeof(struct k210_clk_priv),
  1132. };
  1133. #if CONFIG_IS_ENABLED(CMD_CLK)
  1134. static char show_enabled(struct k210_clk_priv *priv, int id)
  1135. {
  1136. bool enabled;
  1137. if (k210_clks[id].flags & K210_CLKF_PLL) {
  1138. const struct k210_pll_params *pll =
  1139. &k210_plls[k210_clks[id].pll];
  1140. enabled = k210_pll_enabled(readl(priv->base + pll->off));
  1141. } else if (k210_clks[id].gate == K210_CLK_GATE_NONE) {
  1142. return '-';
  1143. } else {
  1144. const struct k210_gate_params *gate =
  1145. &k210_gates[k210_clks[id].gate];
  1146. enabled = k210_clk_readl(priv, gate->off, gate->bit_idx, 1);
  1147. }
  1148. return enabled ? 'y' : 'n';
  1149. }
  1150. static void show_clks(struct k210_clk_priv *priv, int id, int depth)
  1151. {
  1152. int i;
  1153. for (i = 0; i < ARRAY_SIZE(k210_clks); i++) {
  1154. if (k210_clk_get_parent(priv, i) != id)
  1155. continue;
  1156. printf(" %-9lu %-7c %*s%s\n", do_k210_clk_get_rate(priv, i),
  1157. show_enabled(priv, i), depth * 4, "",
  1158. k210_clks[i].name);
  1159. show_clks(priv, i, depth + 1);
  1160. }
  1161. }
  1162. int soc_clk_dump(void)
  1163. {
  1164. int ret;
  1165. struct udevice *dev;
  1166. struct k210_clk_priv *priv;
  1167. ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk),
  1168. &dev);
  1169. if (ret)
  1170. return ret;
  1171. priv = dev_get_priv(dev);
  1172. puts(" Rate Enabled Name\n");
  1173. puts("------------------------\n");
  1174. printf(" %-9lu %-7c %*s%s\n", clk_get_rate(&priv->in0), 'y', 0, "",
  1175. priv->in0.dev->name);
  1176. show_clks(priv, K210_CLK_IN0, 1);
  1177. return 0;
  1178. }
  1179. #endif