csr.h 5.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2015 Regents of the University of California
  4. *
  5. * Taken from Linux arch/riscv/include/asm/csr.h
  6. */
  7. #ifndef _ASM_RISCV_CSR_H
  8. #define _ASM_RISCV_CSR_H
  9. #include <asm/asm.h>
  10. #include <linux/const.h>
  11. /* Status register flags */
  12. #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
  13. #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
  14. #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
  15. #ifdef CONFIG_RISCV_PRIV_1_9
  16. #define SR_PUM _AC(0x00040000, UL) /* Protect User Memory Access */
  17. #else
  18. #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
  19. #endif
  20. #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
  21. #define SR_FS_OFF _AC(0x00000000, UL)
  22. #define SR_FS_INITIAL _AC(0x00002000, UL)
  23. #define SR_FS_CLEAN _AC(0x00004000, UL)
  24. #define SR_FS_DIRTY _AC(0x00006000, UL)
  25. #define SR_XS _AC(0x00018000, UL) /* Extension Status */
  26. #define SR_XS_OFF _AC(0x00000000, UL)
  27. #define SR_XS_INITIAL _AC(0x00008000, UL)
  28. #define SR_XS_CLEAN _AC(0x00010000, UL)
  29. #define SR_XS_DIRTY _AC(0x00018000, UL)
  30. #ifdef CONFIG_RISCV_PRIV_1_9
  31. #define SR_VM _AC(0x1F000000, UL) /* Virtualization Management */
  32. #define SR_VM_MODE_BARE _AC(0x00000000, UL) /* No translation or protection */
  33. #define SR_VM_MODE_BB _AC(0x01000000, UL) /* Single base-and-bound */
  34. /* Separate instruction and data base-and-bound */
  35. #define SR_VM_MODE_BBID _AC(0x02000000, UL)
  36. #ifndef CONFIG_64BIT
  37. #define SR_VM_MODE_32 _AC(0x08000000, UL)
  38. #define SR_VM_MODE SR_VM_MODE_32
  39. #else
  40. #define SR_VM_MODE_39 _AC(0x09000000, UL)
  41. #define SR_VM_MODE_48 _AC(0x0A000000, UL)
  42. #define SR_VM_MODE SR_VM_MODE_39
  43. #endif
  44. #endif
  45. #ifndef CONFIG_64BIT
  46. #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
  47. #else
  48. #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
  49. #endif
  50. /* SATP flags */
  51. #ifndef CONFIG_RISCV_PRIV_1_9
  52. #ifndef CONFIG_64BIT
  53. #define SATP_PPN _AC(0x003FFFFF, UL)
  54. #define SATP_MODE_32 _AC(0x80000000, UL)
  55. #define SATP_MODE SATP_MODE_32
  56. #else
  57. #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
  58. #define SATP_MODE_39 _AC(0x8000000000000000, UL)
  59. #define SATP_MODE SATP_MODE_39
  60. #endif
  61. #endif
  62. /* SCAUSE */
  63. #define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
  64. #define IRQ_U_SOFT 0
  65. #define IRQ_S_SOFT 1
  66. #define IRQ_M_SOFT 3
  67. #define IRQ_U_TIMER 4
  68. #define IRQ_S_TIMER 5
  69. #define IRQ_M_TIMER 7
  70. #define IRQ_U_EXT 8
  71. #define IRQ_S_EXT 9
  72. #define IRQ_M_EXT 11
  73. #define EXC_INST_MISALIGNED 0
  74. #define EXC_INST_ACCESS 1
  75. #define EXC_BREAKPOINT 3
  76. #define EXC_LOAD_ACCESS 5
  77. #define EXC_STORE_ACCESS 7
  78. #define EXC_SYSCALL 8
  79. #define EXC_INST_PAGE_FAULT 12
  80. #define EXC_LOAD_PAGE_FAULT 13
  81. #define EXC_STORE_PAGE_FAULT 15
  82. /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
  83. #define MIE_MSIE (_AC(0x1, UL) << IRQ_M_SOFT)
  84. #define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT)
  85. #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER)
  86. #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT)
  87. #define CSR_FCSR 0x003
  88. #define CSR_CYCLE 0xc00
  89. #define CSR_TIME 0xc01
  90. #define CSR_INSTRET 0xc02
  91. #define CSR_SSTATUS 0x100
  92. #define CSR_SIE 0x104
  93. #define CSR_STVEC 0x105
  94. #define CSR_SCOUNTEREN 0x106
  95. #define CSR_SSCRATCH 0x140
  96. #define CSR_SEPC 0x141
  97. #define CSR_SCAUSE 0x142
  98. #define CSR_STVAL 0x143
  99. #define CSR_SIP 0x144
  100. #ifdef CONFIG_RISCV_PRIV_1_9
  101. #define CSR_SPTBR 0x180
  102. #else
  103. #define CSR_SATP 0x180
  104. #endif
  105. #define CSR_MSTATUS 0x300
  106. #define CSR_MISA 0x301
  107. #define CSR_MIE 0x304
  108. #define CSR_MTVEC 0x305
  109. #ifdef CONFIG_RISCV_PRIV_1_9
  110. #define CSR_MUCOUNTEREN 0x320
  111. #define CSR_MSCOUNTEREN 0x321
  112. #define CSR_MHCOUNTEREN 0x322
  113. #else
  114. #define CSR_MCOUNTEREN 0x306
  115. #endif
  116. #define CSR_MSCRATCH 0x340
  117. #define CSR_MEPC 0x341
  118. #define CSR_MCAUSE 0x342
  119. #define CSR_MTVAL 0x343
  120. #define CSR_MIP 0x344
  121. #ifdef CONFIG_RISCV_PRIV_1_9
  122. #define CSR_MBASE 0x380
  123. #define CSR_MBOUND 0x381
  124. #define CSR_MIBASE 0x382
  125. #define CSR_MIBOUND 0x383
  126. #define CSR_MDBASE 0x384
  127. #define CSR_MDBOUND 0x385
  128. #endif
  129. #define CSR_CYCLEH 0xc80
  130. #define CSR_TIMEH 0xc81
  131. #define CSR_INSTRETH 0xc82
  132. #define CSR_MHARTID 0xf14
  133. #ifndef __ASSEMBLY__
  134. #define csr_swap(csr, val) \
  135. ({ \
  136. unsigned long __v = (unsigned long)(val); \
  137. __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
  138. : "=r" (__v) : "rK" (__v) \
  139. : "memory"); \
  140. __v; \
  141. })
  142. #define csr_read(csr) \
  143. ({ \
  144. register unsigned long __v; \
  145. __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
  146. : "=r" (__v) : \
  147. : "memory"); \
  148. __v; \
  149. })
  150. #define csr_write(csr, val) \
  151. ({ \
  152. unsigned long __v = (unsigned long)(val); \
  153. __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
  154. : : "rK" (__v) \
  155. : "memory"); \
  156. })
  157. #define csr_read_set(csr, val) \
  158. ({ \
  159. unsigned long __v = (unsigned long)(val); \
  160. __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
  161. : "=r" (__v) : "rK" (__v) \
  162. : "memory"); \
  163. __v; \
  164. })
  165. #define csr_set(csr, val) \
  166. ({ \
  167. unsigned long __v = (unsigned long)(val); \
  168. __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
  169. : : "rK" (__v) \
  170. : "memory"); \
  171. })
  172. #define csr_read_clear(csr, val) \
  173. ({ \
  174. unsigned long __v = (unsigned long)(val); \
  175. __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
  176. : "=r" (__v) : "rK" (__v) \
  177. : "memory"); \
  178. __v; \
  179. })
  180. #define csr_clear(csr, val) \
  181. ({ \
  182. unsigned long __v = (unsigned long)(val); \
  183. __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
  184. : : "rK" (__v) \
  185. : "memory"); \
  186. })
  187. #endif /* __ASSEMBLY__ */
  188. #endif /* _ASM_RISCV_CSR_H */