barrier.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2012 ARM Ltd.
  4. * Copyright (C) 2013 Regents of the University of California
  5. * Copyright (C) 2017 SiFive
  6. *
  7. * Taken from Linux arch/riscv/include/asm/barrier.h, which is based on
  8. * arch/arm/include/asm/barrier.h
  9. */
  10. #ifndef _ASM_RISCV_BARRIER_H
  11. #define _ASM_RISCV_BARRIER_H
  12. #ifndef __ASSEMBLY__
  13. #define nop() __asm__ __volatile__ ("nop")
  14. #define RISCV_FENCE(p, s) \
  15. __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
  16. /* These barriers need to enforce ordering on both devices or memory. */
  17. #define mb() RISCV_FENCE(iorw,iorw)
  18. #define rmb() RISCV_FENCE(ir,ir)
  19. #define wmb() RISCV_FENCE(ow,ow)
  20. /* These barriers do not need to enforce ordering on devices, just memory. */
  21. #define __smp_mb() RISCV_FENCE(rw,rw)
  22. #define __smp_rmb() RISCV_FENCE(r,r)
  23. #define __smp_wmb() RISCV_FENCE(w,w)
  24. #define __smp_store_release(p, v) \
  25. do { \
  26. compiletime_assert_atomic_type(*p); \
  27. RISCV_FENCE(rw,w); \
  28. WRITE_ONCE(*p, v); \
  29. } while (0)
  30. #define __smp_load_acquire(p) \
  31. ({ \
  32. typeof(*p) ___p1 = READ_ONCE(*p); \
  33. compiletime_assert_atomic_type(*p); \
  34. RISCV_FENCE(r,rw); \
  35. ___p1; \
  36. })
  37. /*
  38. * This is a very specific barrier: it's currently only used in two places in
  39. * the kernel, both in the scheduler. See include/linux/spinlock.h for the two
  40. * orderings it guarantees, but the "critical section is RCsc" guarantee
  41. * mandates a barrier on RISC-V. The sequence looks like:
  42. *
  43. * lr.aq lock
  44. * sc lock <= LOCKED
  45. * smp_mb__after_spinlock()
  46. * // critical section
  47. * lr lock
  48. * sc.rl lock <= UNLOCKED
  49. *
  50. * The AQ/RL pair provides a RCpc critical section, but there's not really any
  51. * way we can take advantage of that here because the ordering is only enforced
  52. * on that one lock. Thus, we're just doing a full fence.
  53. */
  54. #define smp_mb__after_spinlock() RISCV_FENCE(rw,rw)
  55. #endif /* __ASSEMBLY__ */
  56. #endif /* _ASM_RISCV_BARRIER_H */