fu740-c000-u-boot.dtsi 2.2 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * (C) Copyright 2020-2021 SiFive, Inc
  4. */
  5. #include <dt-bindings/reset/sifive-fu740-prci.h>
  6. / {
  7. cpus {
  8. assigned-clocks = <&prci PRCI_CLK_COREPLL>;
  9. assigned-clock-rates = <1200000000>;
  10. u-boot,dm-spl;
  11. cpu0: cpu@0 {
  12. clocks = <&prci PRCI_CLK_COREPLL>;
  13. u-boot,dm-spl;
  14. status = "okay";
  15. cpu0_intc: interrupt-controller {
  16. u-boot,dm-spl;
  17. };
  18. };
  19. cpu1: cpu@1 {
  20. clocks = <&prci PRCI_CLK_COREPLL>;
  21. u-boot,dm-spl;
  22. cpu1_intc: interrupt-controller {
  23. u-boot,dm-spl;
  24. };
  25. };
  26. cpu2: cpu@2 {
  27. clocks = <&prci PRCI_CLK_COREPLL>;
  28. u-boot,dm-spl;
  29. cpu2_intc: interrupt-controller {
  30. u-boot,dm-spl;
  31. };
  32. };
  33. cpu3: cpu@3 {
  34. clocks = <&prci PRCI_CLK_COREPLL>;
  35. u-boot,dm-spl;
  36. cpu3_intc: interrupt-controller {
  37. u-boot,dm-spl;
  38. };
  39. };
  40. cpu4: cpu@4 {
  41. clocks = <&prci PRCI_CLK_COREPLL>;
  42. u-boot,dm-spl;
  43. cpu4_intc: interrupt-controller {
  44. u-boot,dm-spl;
  45. };
  46. };
  47. };
  48. soc {
  49. u-boot,dm-spl;
  50. clint: clint@2000000 {
  51. compatible = "riscv,clint0";
  52. interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
  53. &cpu1_intc 3 &cpu1_intc 7
  54. &cpu2_intc 3 &cpu2_intc 7
  55. &cpu3_intc 3 &cpu3_intc 7
  56. &cpu4_intc 3 &cpu4_intc 7>;
  57. reg = <0x0 0x2000000 0x0 0x10000>;
  58. u-boot,dm-spl;
  59. };
  60. prci: clock-controller@10000000 {
  61. #reset-cells = <1>;
  62. resets = <&prci PRCI_RST_DDR_CTRL_N>,
  63. <&prci PRCI_RST_DDR_AXI_N>,
  64. <&prci PRCI_RST_DDR_AHB_N>,
  65. <&prci PRCI_RST_DDR_PHY_N>,
  66. <&prci PRCI_RST_GEMGXL_N>,
  67. <&prci PRCI_RST_CLTX_N>;
  68. reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
  69. "ddr_phy", "gemgxl_reset", "cltx_reset";
  70. };
  71. dmc: dmc@100b0000 {
  72. compatible = "sifive,fu740-c000-ddr";
  73. reg = <0x0 0x100b0000 0x0 0x0800
  74. 0x0 0x100b2000 0x0 0x2000
  75. 0x0 0x100b8000 0x0 0x1000>;
  76. clocks = <&prci PRCI_CLK_DDRPLL>;
  77. clock-frequency = <933333324>;
  78. u-boot,dm-spl;
  79. };
  80. };
  81. };
  82. &prci {
  83. u-boot,dm-spl;
  84. };
  85. &uart0 {
  86. u-boot,dm-spl;
  87. };
  88. &spi0 {
  89. u-boot,dm-spl;
  90. };
  91. &i2c0 {
  92. u-boot,dm-spl;
  93. };
  94. &eth0 {
  95. assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
  96. assigned-clock-rates = <125125000>;
  97. };
  98. &ccache {
  99. status = "okay";
  100. };