u-boot-spl.lds 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Based on arch/riscv/cpu/u-boot.lds, which is
  4. * Copyright (C) 2017 Andes Technology Corporation
  5. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  6. *
  7. * and arch/mips/cpu/u-boot-spl.lds.
  8. */
  9. MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
  10. MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
  11. LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
  12. OUTPUT_ARCH("riscv")
  13. ENTRY(_start)
  14. SECTIONS
  15. {
  16. . = ALIGN(4);
  17. .text : {
  18. arch/riscv/cpu/start.o (.text)
  19. *(.text*)
  20. } > .spl_mem
  21. . = ALIGN(4);
  22. .rodata : {
  23. *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
  24. } > .spl_mem
  25. . = ALIGN(4);
  26. .data : {
  27. *(.data*)
  28. } > .spl_mem
  29. . = ALIGN(4);
  30. .got : {
  31. __got_start = .;
  32. *(.got.plt) *(.got)
  33. __got_end = .;
  34. } > .spl_mem
  35. . = ALIGN(4);
  36. .u_boot_list : {
  37. KEEP(*(SORT(.u_boot_list*)));
  38. } > .spl_mem
  39. . = ALIGN(4);
  40. .binman_sym_table : {
  41. __binman_sym_start = .;
  42. KEEP(*(SORT(.binman_sym*)));
  43. __binman_sym_end = .;
  44. } > .spl_mem
  45. . = ALIGN(4);
  46. /DISCARD/ : { *(.rela.plt*) }
  47. .rela.dyn : {
  48. __rel_dyn_start = .;
  49. *(.rela*)
  50. __rel_dyn_end = .;
  51. } > .spl_mem
  52. . = ALIGN(4);
  53. .dynsym : {
  54. __dyn_sym_start = .;
  55. *(.dynsym)
  56. __dyn_sym_end = .;
  57. } > .spl_mem
  58. . = ALIGN(4);
  59. _end = .;
  60. _image_binary_end = .;
  61. .bss : {
  62. __bss_start = .;
  63. *(.bss*)
  64. . = ALIGN(8);
  65. __bss_end = .;
  66. } > .bss_mem
  67. }