Kconfig 9.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386
  1. menu "RISC-V architecture"
  2. depends on RISCV
  3. config SYS_ARCH
  4. default "riscv"
  5. choice
  6. prompt "Target select"
  7. optional
  8. config TARGET_AX25_AE350
  9. bool "Support ax25-ae350"
  10. config TARGET_MICROCHIP_ICICLE
  11. bool "Support Microchip PolarFire-SoC Icicle Board"
  12. config TARGET_QEMU_VIRT
  13. bool "Support QEMU Virt Board"
  14. config TARGET_SIFIVE_UNLEASHED
  15. bool "Support SiFive Unleashed Board"
  16. config TARGET_SIFIVE_UNMATCHED
  17. bool "Support SiFive Unmatched Board"
  18. config TARGET_STARFIVE_VISIONFIVE
  19. bool "Support StarFive VisionFive Board"
  20. config TARGET_STARFIVE_EVB
  21. bool "Support StarFive Evb Board"
  22. config TARGET_SIPEED_MAIX
  23. bool "Support Sipeed Maix Board"
  24. config TARGET_OPENPITON_RISCV64
  25. bool "Support RISC-V cores on OpenPiton SoC"
  26. endchoice
  27. config SYS_ICACHE_OFF
  28. bool "Do not enable icache"
  29. default n
  30. help
  31. Do not enable instruction cache in U-Boot.
  32. config SPL_SYS_ICACHE_OFF
  33. bool "Do not enable icache in SPL"
  34. depends on SPL
  35. default SYS_ICACHE_OFF
  36. help
  37. Do not enable instruction cache in SPL.
  38. config SYS_DCACHE_OFF
  39. bool "Do not enable dcache"
  40. default n
  41. help
  42. Do not enable data cache in U-Boot.
  43. config SPL_SYS_DCACHE_OFF
  44. bool "Do not enable dcache in SPL"
  45. depends on SPL
  46. default SYS_DCACHE_OFF
  47. help
  48. Do not enable data cache in SPL.
  49. # board-specific options below
  50. source "board/AndesTech/ax25-ae350/Kconfig"
  51. source "board/emulation/qemu-riscv/Kconfig"
  52. source "board/microchip/mpfs_icicle/Kconfig"
  53. source "board/sifive/unleashed/Kconfig"
  54. source "board/sifive/unmatched/Kconfig"
  55. source "board/openpiton/riscv64/Kconfig"
  56. source "board/sipeed/maix/Kconfig"
  57. source "board/starfive/visionfive/Kconfig"
  58. source "board/starfive/evb/Kconfig"
  59. # platform-specific options below
  60. source "arch/riscv/cpu/ax25/Kconfig"
  61. source "arch/riscv/cpu/fu540/Kconfig"
  62. source "arch/riscv/cpu/fu740/Kconfig"
  63. source "arch/riscv/cpu/generic/Kconfig"
  64. source "arch/riscv/cpu/jh7110/Kconfig"
  65. # architecture-specific options below
  66. choice
  67. prompt "Base ISA"
  68. default ARCH_RV32I
  69. config ARCH_RV32I
  70. bool "RV32I"
  71. select 32BIT
  72. help
  73. Choose this option to target the RV32I base integer instruction set.
  74. config ARCH_RV64I
  75. bool "RV64I"
  76. select 64BIT
  77. select PHYS_64BIT
  78. help
  79. Choose this option to target the RV64I base integer instruction set.
  80. endchoice
  81. choice
  82. prompt "Code Model"
  83. default CMODEL_MEDLOW
  84. config CMODEL_MEDLOW
  85. bool "medium low code model"
  86. help
  87. U-Boot and its statically defined symbols must lie within a single 2 GiB
  88. address range and must lie between absolute addresses -2 GiB and +2 GiB.
  89. config CMODEL_MEDANY
  90. bool "medium any code model"
  91. help
  92. U-Boot and its statically defined symbols must be within any single 2 GiB
  93. address range.
  94. endchoice
  95. choice
  96. prompt "Run Mode"
  97. default RISCV_MMODE
  98. config RISCV_MMODE
  99. bool "Machine"
  100. help
  101. Choose this option to build U-Boot for RISC-V M-Mode.
  102. config RISCV_SMODE
  103. bool "Supervisor"
  104. help
  105. Choose this option to build U-Boot for RISC-V S-Mode.
  106. endchoice
  107. choice
  108. prompt "SPL Run Mode"
  109. default SPL_RISCV_MMODE
  110. depends on SPL
  111. config SPL_RISCV_MMODE
  112. bool "Machine"
  113. help
  114. Choose this option to build U-Boot SPL for RISC-V M-Mode.
  115. config SPL_RISCV_SMODE
  116. bool "Supervisor"
  117. help
  118. Choose this option to build U-Boot SPL for RISC-V S-Mode.
  119. endchoice
  120. config RISCV_ISA_C
  121. bool "Emit compressed instructions"
  122. default y
  123. help
  124. Adds "C" to the ISA subsets that the toolchain is allowed to emit
  125. when building U-Boot, which results in compressed instructions in the
  126. U-Boot binary.
  127. config RISCV_ISA_A
  128. def_bool y
  129. config 32BIT
  130. bool
  131. config 64BIT
  132. bool
  133. config DMA_ADDR_T_64BIT
  134. bool
  135. default y if 64BIT
  136. config SIFIVE_CLINT
  137. bool
  138. depends on RISCV_MMODE
  139. help
  140. The SiFive CLINT block holds memory-mapped control and status registers
  141. associated with software and timer interrupts.
  142. config SPL_SIFIVE_CLINT
  143. bool
  144. depends on SPL_RISCV_MMODE
  145. help
  146. The SiFive CLINT block holds memory-mapped control and status registers
  147. associated with software and timer interrupts.
  148. config SIFIVE_CACHE
  149. bool
  150. help
  151. This enables the operations to configure SiFive cache
  152. config ANDES_PLIC
  153. bool
  154. depends on RISCV_MMODE || SPL_RISCV_MMODE
  155. select REGMAP
  156. select SYSCON
  157. select SPL_REGMAP if SPL
  158. select SPL_SYSCON if SPL
  159. help
  160. The Andes PLIC block holds memory-mapped claim and pending registers
  161. associated with software interrupt.
  162. config SYS_MALLOC_F_LEN
  163. default 0x1000
  164. config SMP
  165. bool "Symmetric Multi-Processing"
  166. depends on SBI_V01 || !RISCV_SMODE
  167. help
  168. This enables support for systems with more than one CPU. If
  169. you say N here, U-Boot will run on single and multiprocessor
  170. machines, but will use only one CPU of a multiprocessor
  171. machine. If you say Y here, U-Boot will run on many, but not
  172. all, single processor machines.
  173. config SPL_SMP
  174. bool "Symmetric Multi-Processing in SPL"
  175. depends on SPL && SPL_RISCV_MMODE
  176. default y
  177. help
  178. This enables support for systems with more than one CPU in SPL.
  179. If you say N here, U-Boot SPL will run on single and multiprocessor
  180. machines, but will use only one CPU of a multiprocessor
  181. machine. If you say Y here, U-Boot SPL will run on many, but not
  182. all, single processor machines.
  183. config NR_CPUS
  184. int "Maximum number of CPUs (2-32)"
  185. range 2 32
  186. depends on SMP || SPL_SMP
  187. default 8
  188. help
  189. On multiprocessor machines, U-Boot sets up a stack for each CPU.
  190. Stack memory is pre-allocated. U-Boot must therefore know the
  191. maximum number of CPUs that may be present.
  192. config SBI
  193. bool
  194. default y if RISCV_SMODE || SPL_RISCV_SMODE
  195. choice
  196. prompt "SBI support"
  197. default SBI_V02
  198. config SBI_V01
  199. bool "SBI v0.1 support"
  200. depends on SBI
  201. help
  202. This config allows kernel to use SBI v0.1 APIs. This will be
  203. deprecated in future once legacy M-mode software are no longer in use.
  204. config SBI_V02
  205. bool "SBI v0.2 support"
  206. depends on SBI
  207. help
  208. This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more
  209. scalable and extendable to handle future needs for RISC-V supervisor
  210. interfaces. For example, with SBI v0.2 HSM extension, only a single
  211. hart need to boot and enter operating system. The booting hart can
  212. bring up secondary harts one by one afterwards.
  213. Choose this option if OpenSBI v0.7 or above release is used together
  214. with U-Boot.
  215. endchoice
  216. config SBI_IPI
  217. bool
  218. depends on SBI
  219. default y if RISCV_SMODE || SPL_RISCV_SMODE
  220. depends on SMP
  221. config XIP
  222. bool "XIP mode"
  223. help
  224. XIP (eXecute In Place) is a method for executing code directly
  225. from a NOR flash memory without copying the code to ram.
  226. Say yes here if U-Boot boots from flash directly.
  227. config SHOW_REGS
  228. bool "Show registers on unhandled exception"
  229. config RISCV_PRIV_1_9
  230. bool "Use version 1.9 of the RISC-V priviledged specification"
  231. help
  232. Older versions of the RISC-V priviledged specification had
  233. separate counter enable CSRs for each privilege mode. Writing
  234. to the unified mcounteren CSR on a processor implementing the
  235. old specification will result in an illegal instruction
  236. exception. In addition to counter CSR changes, the way virtual
  237. memory is configured was also changed.
  238. config STACK_SIZE_SHIFT
  239. int
  240. default 14
  241. config OF_BOARD_FIXUP
  242. default y if OF_SEPARATE && RISCV_SMODE
  243. menu "Use assembly optimized implementation of memory routines"
  244. config USE_ARCH_MEMCPY
  245. bool "Use an assembly optimized implementation of memcpy"
  246. default y
  247. help
  248. Enable the generation of an optimized version of memcpy.
  249. Such an implementation may be faster under some conditions
  250. but may increase the binary size.
  251. config SPL_USE_ARCH_MEMCPY
  252. bool "Use an assembly optimized implementation of memcpy for SPL"
  253. default y if USE_ARCH_MEMCPY
  254. depends on SPL
  255. help
  256. Enable the generation of an optimized version of memcpy.
  257. Such an implementation may be faster under some conditions
  258. but may increase the binary size.
  259. config TPL_USE_ARCH_MEMCPY
  260. bool "Use an assembly optimized implementation of memcpy for TPL"
  261. default y if USE_ARCH_MEMCPY
  262. depends on TPL
  263. help
  264. Enable the generation of an optimized version of memcpy.
  265. Such an implementation may be faster under some conditions
  266. but may increase the binary size.
  267. config USE_ARCH_MEMMOVE
  268. bool "Use an assembly optimized implementation of memmove"
  269. default y
  270. help
  271. Enable the generation of an optimized version of memmove.
  272. Such an implementation may be faster under some conditions
  273. but may increase the binary size.
  274. config SPL_USE_ARCH_MEMMOVE
  275. bool "Use an assembly optimized implementation of memmove for SPL"
  276. default y if USE_ARCH_MEMCPY
  277. depends on SPL
  278. help
  279. Enable the generation of an optimized version of memmove.
  280. Such an implementation may be faster under some conditions
  281. but may increase the binary size.
  282. config TPL_USE_ARCH_MEMMOVE
  283. bool "Use an assembly optimized implementation of memmove for TPL"
  284. default y if USE_ARCH_MEMCPY
  285. depends on TPL
  286. help
  287. Enable the generation of an optimized version of memmove.
  288. Such an implementation may be faster under some conditions
  289. but may increase the binary size.
  290. config USE_ARCH_MEMSET
  291. bool "Use an assembly optimized implementation of memset"
  292. default y
  293. help
  294. Enable the generation of an optimized version of memset.
  295. Such an implementation may be faster under some conditions
  296. but may increase the binary size.
  297. config SPL_USE_ARCH_MEMSET
  298. bool "Use an assembly optimized implementation of memset for SPL"
  299. default y if USE_ARCH_MEMSET
  300. depends on SPL
  301. help
  302. Enable the generation of an optimized version of memset.
  303. Such an implementation may be faster under some conditions
  304. but may increase the binary size.
  305. config TPL_USE_ARCH_MEMSET
  306. bool "Use an assembly optimized implementation of memset for TPL"
  307. default y if USE_ARCH_MEMSET
  308. depends on TPL
  309. help
  310. Enable the generation of an optimized version of memset.
  311. Such an implementation may be faster under some conditions
  312. but may increase the binary size.
  313. endmenu
  314. endmenu