seps525.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FB driver for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display
  4. * using the SEPS525 (Syncoam) LCD Controller
  5. *
  6. * Copyright (C) 2020 Xilinx Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <spi.h>
  14. #include <video.h>
  15. #include <asm/gpio.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/delay.h>
  18. #define WIDTH 160
  19. #define HEIGHT 128
  20. #define SEPS525_INDEX 0x00
  21. #define SEPS525_STATUS_RD 0x01
  22. #define SEPS525_OSC_CTL 0x02
  23. #define SEPS525_IREF 0x80
  24. #define SEPS525_CLOCK_DIV 0x03
  25. #define SEPS525_REDUCE_CURRENT 0x04
  26. #define SEPS525_SOFT_RST 0x05
  27. #define SEPS525_DISP_ONOFF 0x06
  28. #define SEPS525_PRECHARGE_TIME_R 0x08
  29. #define SEPS525_PRECHARGE_TIME_G 0x09
  30. #define SEPS525_PRECHARGE_TIME_B 0x0A
  31. #define SEPS525_PRECHARGE_CURRENT_R 0x0B
  32. #define SEPS525_PRECHARGE_CURRENT_G 0x0C
  33. #define SEPS525_PRECHARGE_CURRENT_B 0x0D
  34. #define SEPS525_DRIVING_CURRENT_R 0x10
  35. #define SEPS525_DRIVING_CURRENT_G 0x11
  36. #define SEPS525_DRIVING_CURRENT_B 0x12
  37. #define SEPS525_DISPLAYMODE_SET 0x13
  38. #define SEPS525_RGBIF 0x14
  39. #define SEPS525_RGB_POL 0x15
  40. #define SEPS525_MEMORY_WRITEMODE 0x16
  41. #define SEPS525_MX1_ADDR 0x17
  42. #define SEPS525_MX2_ADDR 0x18
  43. #define SEPS525_MY1_ADDR 0x19
  44. #define SEPS525_MY2_ADDR 0x1A
  45. #define SEPS525_MEMORY_ACCESS_POINTER_X 0x20
  46. #define SEPS525_MEMORY_ACCESS_POINTER_Y 0x21
  47. #define SEPS525_DDRAM_DATA_ACCESS_PORT 0x22
  48. #define SEPS525_GRAY_SCALE_TABLE_INDEX 0x50
  49. #define SEPS525_GRAY_SCALE_TABLE_DATA 0x51
  50. #define SEPS525_DUTY 0x28
  51. #define SEPS525_DSL 0x29
  52. #define SEPS525_D1_DDRAM_FAC 0x2E
  53. #define SEPS525_D1_DDRAM_FAR 0x2F
  54. #define SEPS525_D2_DDRAM_SAC 0x31
  55. #define SEPS525_D2_DDRAM_SAR 0x32
  56. #define SEPS525_SCR1_FX1 0x33
  57. #define SEPS525_SCR1_FX2 0x34
  58. #define SEPS525_SCR1_FY1 0x35
  59. #define SEPS525_SCR1_FY2 0x36
  60. #define SEPS525_SCR2_SX1 0x37
  61. #define SEPS525_SCR2_SX2 0x38
  62. #define SEPS525_SCR2_SY1 0x39
  63. #define SEPS525_SCR2_SY2 0x3A
  64. #define SEPS525_SCREEN_SAVER_CONTEROL 0x3B
  65. #define SEPS525_SS_SLEEP_TIMER 0x3C
  66. #define SEPS525_SCREEN_SAVER_MODE 0x3D
  67. #define SEPS525_SS_SCR1_FU 0x3E
  68. #define SEPS525_SS_SCR1_MXY 0x3F
  69. #define SEPS525_SS_SCR2_FU 0x40
  70. #define SEPS525_SS_SCR2_MXY 0x41
  71. #define SEPS525_MOVING_DIRECTION 0x42
  72. #define SEPS525_SS_SCR2_SX1 0x47
  73. #define SEPS525_SS_SCR2_SX2 0x48
  74. #define SEPS525_SS_SCR2_SY1 0x49
  75. #define SEPS525_SS_SCR2_SY2 0x4A
  76. /* SEPS525_DISPLAYMODE_SET */
  77. #define MODE_SWAP_BGR BIT(7)
  78. #define MODE_SM BIT(6)
  79. #define MODE_RD BIT(5)
  80. #define MODE_CD BIT(4)
  81. /**
  82. * struct seps525_priv - Private structure
  83. * @reset_gpio: Reset gpio pin
  84. * @dc_gpio: Data/command control gpio pin
  85. * @dev: Device uclass for video_ops
  86. */
  87. struct seps525_priv {
  88. struct gpio_desc reset_gpio;
  89. struct gpio_desc dc_gpio;
  90. struct udevice *dev;
  91. };
  92. static int seps525_spi_write_cmd(struct udevice *dev, u32 reg)
  93. {
  94. struct seps525_priv *priv = dev_get_priv(dev);
  95. u8 buf8 = reg;
  96. int ret;
  97. ret = dm_gpio_set_value(&priv->dc_gpio, 0);
  98. if (ret) {
  99. dev_dbg(dev, "Failed to handle dc\n");
  100. return ret;
  101. }
  102. ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
  103. if (ret)
  104. dev_dbg(dev, "Failed to write command\n");
  105. return ret;
  106. }
  107. static int seps525_spi_write_data(struct udevice *dev, u32 val)
  108. {
  109. struct seps525_priv *priv = dev_get_priv(dev);
  110. u8 buf8 = val;
  111. int ret;
  112. ret = dm_gpio_set_value(&priv->dc_gpio, 1);
  113. if (ret) {
  114. dev_dbg(dev, "Failed to handle dc\n");
  115. return ret;
  116. }
  117. ret = dm_spi_xfer(dev, 8, &buf8, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
  118. if (ret)
  119. dev_dbg(dev, "Failed to write data\n");
  120. return ret;
  121. }
  122. static void seps525_spi_write(struct udevice *dev, u32 reg, u32 val)
  123. {
  124. (void)seps525_spi_write_cmd(dev, reg);
  125. (void)seps525_spi_write_data(dev, val);
  126. }
  127. static int seps525_display_init(struct udevice *dev)
  128. {
  129. /* Disable Oscillator Power Down */
  130. seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x03);
  131. mdelay(5);
  132. /* Set Normal Driving Current */
  133. seps525_spi_write(dev, SEPS525_REDUCE_CURRENT, 0x00);
  134. mdelay(5);
  135. seps525_spi_write(dev, SEPS525_SCREEN_SAVER_CONTEROL, 0x00);
  136. /* Set EXPORT1 Pin at Internal Clock */
  137. seps525_spi_write(dev, SEPS525_OSC_CTL, 0x01);
  138. /* Set Clock as 120 Frames/Sec */
  139. seps525_spi_write(dev, SEPS525_CLOCK_DIV, 0x90);
  140. /* Set Reference Voltage Controlled by External Resister */
  141. seps525_spi_write(dev, SEPS525_IREF, 0x01);
  142. /* precharge time R G B */
  143. seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_R, 0x04);
  144. seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_G, 0x05);
  145. seps525_spi_write(dev, SEPS525_PRECHARGE_TIME_B, 0x05);
  146. /* precharge current R G B (uA) */
  147. seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_R, 0x9D);
  148. seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_G, 0x8C);
  149. seps525_spi_write(dev, SEPS525_PRECHARGE_CURRENT_B, 0x57);
  150. /* driving current R G B (uA) */
  151. seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_R, 0x56);
  152. seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_G, 0x4D);
  153. seps525_spi_write(dev, SEPS525_DRIVING_CURRENT_B, 0x46);
  154. /* Set Color Sequence */
  155. seps525_spi_write(dev, SEPS525_DISPLAYMODE_SET, 0x00);
  156. /* Set MCU Interface Mode */
  157. seps525_spi_write(dev, SEPS525_RGBIF, 0x01);
  158. /* Set Memory Write Mode */
  159. seps525_spi_write(dev, SEPS525_MEMORY_WRITEMODE, 0x66);
  160. /* 1/128 Duty (0x0F~0x7F) */
  161. seps525_spi_write(dev, SEPS525_DUTY, 0x7F);
  162. /* Set Mapping RAM Display Start Line (0x00~0x7F) */
  163. seps525_spi_write(dev, SEPS525_DSL, 0x00);
  164. /* Display On (0x00/0x01) */
  165. seps525_spi_write(dev, SEPS525_DISP_ONOFF, 0x01);
  166. /* Set All Internal Register Value as Normal Mode */
  167. seps525_spi_write(dev, SEPS525_SOFT_RST, 0x00);
  168. /* Set RGB Interface Polarity as Active Low */
  169. seps525_spi_write(dev, SEPS525_RGB_POL, 0x00);
  170. /* Enable access for data */
  171. (void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT);
  172. return 0;
  173. }
  174. static int seps525_spi_startup(struct udevice *dev)
  175. {
  176. struct seps525_priv *priv = dev_get_priv(dev);
  177. int ret;
  178. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  179. if (ret)
  180. return ret;
  181. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  182. if (ret)
  183. return ret;
  184. ret = dm_spi_claim_bus(dev);
  185. if (ret) {
  186. dev_err(dev, "Failed to claim SPI bus: %d\n", ret);
  187. return ret;
  188. }
  189. ret = seps525_display_init(dev);
  190. if (ret)
  191. return ret;
  192. dm_spi_release_bus(dev);
  193. return 0;
  194. }
  195. static int seps525_sync(struct udevice *vid)
  196. {
  197. struct video_priv *uc_priv = dev_get_uclass_priv(vid);
  198. struct seps525_priv *priv = dev_get_priv(vid);
  199. struct udevice *dev = priv->dev;
  200. int i, ret;
  201. u8 data1, data2;
  202. u8 *start = uc_priv->fb;
  203. ret = dm_spi_claim_bus(dev);
  204. if (ret) {
  205. dev_err(dev, "Failed to claim SPI bus: %d\n", ret);
  206. return ret;
  207. }
  208. /* start position X,Y */
  209. seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_X, 0);
  210. seps525_spi_write(dev, SEPS525_MEMORY_ACCESS_POINTER_Y, 0);
  211. /* Enable access for data */
  212. (void)seps525_spi_write_cmd(dev, SEPS525_DDRAM_DATA_ACCESS_PORT);
  213. for (i = 0; i < (uc_priv->xsize * uc_priv->ysize); i++) {
  214. data2 = *start++;
  215. data1 = *start++;
  216. (void)seps525_spi_write_data(dev, data1);
  217. (void)seps525_spi_write_data(dev, data2);
  218. }
  219. dm_spi_release_bus(dev);
  220. return 0;
  221. }
  222. static int seps525_probe(struct udevice *dev)
  223. {
  224. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  225. struct seps525_priv *priv = dev_get_priv(dev);
  226. u32 buswidth;
  227. int ret;
  228. buswidth = dev_read_u32_default(dev, "buswidth", 0);
  229. if (buswidth != 8) {
  230. dev_err(dev, "Only 8bit buswidth is supported now");
  231. return -EINVAL;
  232. }
  233. ret = gpio_request_by_name(dev, "reset-gpios", 0,
  234. &priv->reset_gpio, GPIOD_IS_OUT);
  235. if (ret) {
  236. dev_err(dev, "missing reset GPIO\n");
  237. return ret;
  238. }
  239. ret = gpio_request_by_name(dev, "dc-gpios", 0,
  240. &priv->dc_gpio, GPIOD_IS_OUT);
  241. if (ret) {
  242. dev_err(dev, "missing dc GPIO\n");
  243. return ret;
  244. }
  245. uc_priv->bpix = VIDEO_BPP16;
  246. uc_priv->xsize = WIDTH;
  247. uc_priv->ysize = HEIGHT;
  248. uc_priv->rot = 0;
  249. priv->dev = dev;
  250. ret = seps525_spi_startup(dev);
  251. if (ret)
  252. return ret;
  253. return 0;
  254. }
  255. static int seps525_bind(struct udevice *dev)
  256. {
  257. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  258. plat->size = WIDTH * HEIGHT * 16;
  259. return 0;
  260. }
  261. static const struct video_ops seps525_ops = {
  262. .video_sync = seps525_sync,
  263. };
  264. static const struct udevice_id seps525_ids[] = {
  265. { .compatible = "syncoam,seps525" },
  266. { }
  267. };
  268. U_BOOT_DRIVER(seps525_video) = {
  269. .name = "seps525_video",
  270. .id = UCLASS_VIDEO,
  271. .of_match = seps525_ids,
  272. .ops = &seps525_ops,
  273. .platdata_auto_alloc_size = sizeof(struct video_uc_platdata),
  274. .bind = seps525_bind,
  275. .probe = seps525_probe,
  276. .priv_auto_alloc_size = sizeof(struct seps525_priv),
  277. };