starfive_evb.dts 9.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482
  1. // SPDX-License-Identifier: GPL-2.0 OR MIT
  2. /*
  3. * Copyright (C) 2022 StarFive Technology Co., Ltd.
  4. */
  5. /dts-v1/;
  6. #include "jh7110.dtsi"
  7. #include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
  8. / {
  9. #address-cells = <2>;
  10. #size-cells = <2>;
  11. model = "StarFive JH7110 EVB";
  12. compatible = "starfive,jh7110";
  13. aliases {
  14. spi0="/soc/spi@13010000";
  15. gpio0="/soc/gpio@13040000";
  16. ethernet0=&gmac0;
  17. ethernet1=&gmac1;
  18. mmc0=&sdio0;
  19. mmc1=&sdio1;
  20. };
  21. chosen {
  22. stdout-path = "/soc/serial@10000000:115200";
  23. starfive,boot-hart-id = <1>;
  24. };
  25. memory@80000000 {
  26. device_type = "memory";
  27. reg = <0x0 0x40000000 0x1 0x0>;
  28. };
  29. reserved-memory {
  30. #size-cells = <2>;
  31. #address-cells = <2>;
  32. ranges;
  33. opensbi {
  34. reg = <0x00 0x40000000 0x00 0x80000>;
  35. no-map;
  36. };
  37. };
  38. soc {
  39. };
  40. };
  41. &cpu0 {
  42. status = "okay";
  43. };
  44. &clkgen {
  45. clocks = <&osc>, <&gmac1_rmii_refin>,
  46. <&stg_apb>, <&gmac0_rmii_refin>;
  47. clock-names = "osc", "gmac1_rmii_refin",
  48. "stg_apb", "gmac0_rmii_refin";
  49. };
  50. &gpio {
  51. status = "okay";
  52. usb_pins: usb-pins {
  53. drive-vbus-pin {
  54. pinmux = <GPIOMUX(33, GPOUT_SYS_USB_DRIVE_VBUS,
  55. GPOEN_ENABLE, GPI_NONE)>;
  56. bias-pull-up;
  57. drive-strength = <2>;
  58. input-disable;
  59. input-schmitt-disable;
  60. slew-rate = <0>;
  61. };
  62. overcurrent-pin {
  63. pinmux = <GPIOMUX(34, GPOUT_LOW,
  64. GPOEN_DISABLE, GPI_SYS_USB_OVERCURRENT)>;
  65. bias-pull-up;
  66. drive-strength = <2>;
  67. input-disable;
  68. input-schmitt-disable;
  69. slew-rate = <0>;
  70. };
  71. };
  72. mmc0_pins: mmc0-pins {
  73. mmc0-pins-rest {
  74. pinmux = <GPIOMUX(22, GPOUT_SYS_SDIO0_RST,
  75. GPOEN_ENABLE, GPI_NONE)>;
  76. bias-pull-up;
  77. drive-strength = <12>;
  78. input-disable;
  79. input-schmitt-disable;
  80. slew-rate = <0>;
  81. };
  82. };
  83. mmc1_pins: mmc1-pins {
  84. mmc1-pins-rest {
  85. pinmux = <GPIOMUX(24, GPOUT_SYS_SDIO1_RST,
  86. GPOEN_ENABLE, GPI_NONE)>;
  87. bias-pull-up;
  88. drive-strength = <12>;
  89. input-disable;
  90. input-schmitt-disable;
  91. slew-rate = <0>;
  92. };
  93. };
  94. i2c2_pins: i2c2-0 {
  95. i2c-pins {
  96. pinmux = <GPIOMUX(11, GPOUT_LOW,
  97. GPOEN_SYS_I2C2_CLK,
  98. GPI_SYS_I2C2_CLK)>,
  99. <GPIOMUX(9, GPOUT_LOW,
  100. GPOEN_SYS_I2C2_DATA,
  101. GPI_SYS_I2C2_DATA)>;
  102. bias-disable; /* external pull-up */
  103. input-enable;
  104. input-schmitt-enable;
  105. };
  106. };
  107. i2c5_pins: i2c5-0 {
  108. i2c-pins {
  109. pinmux = <GPIOMUX(19, GPOUT_LOW,
  110. GPOEN_SYS_I2C5_CLK,
  111. GPI_SYS_I2C5_CLK)>,
  112. <GPIOMUX(20, GPOUT_LOW,
  113. GPOEN_SYS_I2C5_DATA,
  114. GPI_SYS_I2C5_DATA)>;
  115. bias-disable; /* external pull-up */
  116. input-enable;
  117. input-schmitt-enable;
  118. };
  119. };
  120. hdmi_pins: hdmi-0 {
  121. i2c-pins {
  122. pinmux = <GPIOMUX(7, GPOUT_SYS_HDMI_DDC_SCL,
  123. GPOEN_SYS_HDMI_DDC_SCL,
  124. GPI_SYS_HDMI_DDC_SCL)>,
  125. <GPIOMUX(8, GPOUT_SYS_HDMI_DDC_SDA,
  126. GPOEN_SYS_HDMI_DDC_SDA,
  127. GPI_SYS_HDMI_DDC_SDA)>;
  128. bias-pull-up;
  129. input-enable;
  130. };
  131. cec-pins {
  132. pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
  133. GPOEN_SYS_HDMI_CEC_SDA,
  134. GPI_SYS_HDMI_CEC_SDA)>;
  135. bias-pull-up;
  136. input-enable;
  137. };
  138. hpd-pins {
  139. pinmux = <GPIOMUX(15, GPOUT_LOW,
  140. GPOEN_DISABLE,
  141. GPI_SYS_HDMI_HPD)>;
  142. input-enable;
  143. };
  144. };
  145. pcie0_perst_default: pcie0_perst_default {
  146. perst-pins {
  147. pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  148. drive-strength = <2>;
  149. input-disable;
  150. input-schmitt-disable;
  151. slew-rate = <0>;
  152. };
  153. };
  154. pcie0_perst_active: pcie0_perst_active {
  155. perst-pins {
  156. pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
  157. drive-strength = <2>;
  158. input-disable;
  159. input-schmitt-disable;
  160. slew-rate = <0>;
  161. };
  162. };
  163. pcie0_power_default: pcie0_power_default {
  164. power-pins {
  165. pinmux = <GPIOMUX(32, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
  166. drive-strength = <2>;
  167. input-disable;
  168. input-schmitt-disable;
  169. slew-rate = <0>;
  170. };
  171. };
  172. pcie0_power_active: pcie0_power_active {
  173. power-pins {
  174. pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  175. drive-strength = <2>;
  176. input-disable;
  177. input-schmitt-disable;
  178. slew-rate = <0>;
  179. };
  180. };
  181. pcie1_perst_default: pcie1_perst_default {
  182. perst-pins {
  183. pinmux = <GPIOMUX(28, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  184. drive-strength = <2>;
  185. input-disable;
  186. input-schmitt-disable;
  187. slew-rate = <0>;
  188. };
  189. };
  190. pcie1_perst_active: pcie1_perst_active {
  191. perst-pins {
  192. pinmux = <GPIOMUX(28, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
  193. drive-strength = <2>;
  194. input-disable;
  195. input-schmitt-disable;
  196. slew-rate = <0>;
  197. };
  198. };
  199. pcie1_power_default: pcie1_power_default {
  200. power-pins {
  201. pinmux = <GPIOMUX(21, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
  202. drive-strength = <2>;
  203. input-disable;
  204. input-schmitt-disable;
  205. slew-rate = <0>;
  206. };
  207. };
  208. pcie1_power_active: pcie1_power_active {
  209. power-pins {
  210. pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
  211. drive-strength = <2>;
  212. input-disable;
  213. input-schmitt-disable;
  214. slew-rate = <0>;
  215. };
  216. };
  217. };
  218. &sdio0 {
  219. assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>;
  220. assigned-clock-rates = <50000000>;
  221. fifo-depth = <32>;
  222. bus-width = <4>;
  223. status = "okay";
  224. pinctrl-names = "default";
  225. pinctrl-0 = <&mmc0_pins>;
  226. };
  227. &sdio1 {
  228. status = "disabled";
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&mmc1_pins>;
  231. };
  232. &gmac0 {
  233. status = "okay";
  234. #address-cells = <1>;
  235. #size-cells = <0>;
  236. phy0: ethernet-phy@0 {
  237. rxc_dly_en = <1>;
  238. tx_delay_sel_fe = <5>;
  239. tx_delay_sel = <0xb>;
  240. tx_inverted_10 = <0x0>;
  241. tx_inverted_100 = <0x0>;
  242. tx_inverted_1000 = <0x0>;
  243. };
  244. };
  245. &gmac1 {
  246. status = "okay";
  247. #address-cells = <1>;
  248. #size-cells = <0>;
  249. phy1: ethernet-phy@1 {
  250. rxc-skew-ps = <1060>;
  251. txc-skew-ps = <1800>;
  252. reg = <0>;
  253. };
  254. };
  255. &uart0 {
  256. reg-offset = <0>;
  257. current-speed = <115200>;
  258. status = "okay";
  259. };
  260. &gpioa {
  261. status = "disabled";
  262. };
  263. &usbdrd30 {
  264. clocks = <&clkgen JH7110_USB_125M>,
  265. <&clkgen JH7110_USB0_CLK_APP_125>,
  266. <&clkgen JH7110_USB0_CLK_LPM>,
  267. <&clkgen JH7110_USB0_CLK_STB>,
  268. <&clkgen JH7110_USB0_CLK_USB_APB>,
  269. <&clkgen JH7110_USB0_CLK_AXI>,
  270. <&clkgen JH7110_USB0_CLK_UTMI_APB>,
  271. <&clkgen JH7110_PCIE0_CLK_APB>;
  272. clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
  273. resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
  274. <&rstgen RSTN_U0_CDN_USB_APB>,
  275. <&rstgen RSTN_U0_CDN_USB_AXI>,
  276. <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
  277. <&rstgen RSTN_U0_PLDA_PCIE_APB>;
  278. reset-names = "pwrup","apb","axi","utmi", "phy";
  279. starfive,usb2-only = <0>;
  280. status = "okay";
  281. };
  282. &usbdrd_cdns3 {
  283. dr_mode = "host";
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&usb_pins>;
  286. };
  287. &pcie0 {
  288. pinctrl-names = "perst-default", "perst-active", "power-default", "power-active";
  289. pinctrl-0 = <&pcie0_perst_default>;
  290. pinctrl-1 = <&pcie0_perst_active>;
  291. pinctrl-2 = <&pcie0_power_default>;
  292. pinctrl-3 = <&pcie0_power_active>;
  293. status = "disabled";
  294. };
  295. &pcie1 {
  296. pinctrl-names = "perst-default", "perst-active", "power-default", "power-active";
  297. pinctrl-0 = <&pcie1_perst_default>;
  298. pinctrl-1 = <&pcie1_perst_active>;
  299. pinctrl-2 = <&pcie1_power_default>;
  300. pinctrl-3 = <&pcie1_power_active>;
  301. status = "okay";
  302. };
  303. &timer {
  304. status = "disabled";
  305. };
  306. &wdog {
  307. status = "disabled";
  308. };
  309. &clkvout {
  310. status = "okay";
  311. };
  312. &pdm {
  313. status = "disabled";
  314. };
  315. &mipi_dsi0 {
  316. status = "okay";
  317. rockchip,panel = <&rm68200_panel>;
  318. data-lanes-num = <1>;
  319. display-timings {
  320. timing0 {
  321. bits-per-pixel = <24>;
  322. clock-frequency = <160000000>;
  323. hfront-porch = <120>;
  324. hsync-len = <20>;
  325. hback-porch = <21>;
  326. hactive = <1200>;
  327. vfront-porch = <21>;
  328. vsync-len = <3>;
  329. vback-porch = <18>;
  330. vactive = <1920>;
  331. hsync-active = <0>;
  332. vsync-active = <0>;
  333. de-active = <1>;
  334. pixelclk-active = <0>;
  335. };
  336. };
  337. };
  338. &hdmi{
  339. pinctrl-names = "default";
  340. pinctrl-0 = <&hdmi_pins>;
  341. status = "okay";
  342. };
  343. &i2c2 {
  344. clock-frequency = <100000>;
  345. i2c-sda-hold-time-ns = <300>;
  346. i2c-sda-falling-time-ns = <3000>;
  347. i2c-scl-falling-time-ns = <3000>;
  348. auto_calc_scl_lhcnt;
  349. pinctrl-names = "default";
  350. pinctrl-0 = <&i2c2_pins>;
  351. status = "okay";
  352. rm68200_panel: rm68200_panel@45 {
  353. compatible = "starfive,seeed";
  354. reg = <0x45>;
  355. };
  356. };
  357. &i2c5 {
  358. clock-frequency = <100000>;
  359. i2c-sda-hold-time-ns = <300>;
  360. i2c-sda-falling-time-ns = <3000>;
  361. i2c-scl-falling-time-ns = <3000>;
  362. auto_calc_scl_lhcnt;
  363. pinctrl-names = "default";
  364. pinctrl-0 = <&i2c5_pins>;
  365. status = "okay";
  366. pmic_axp15060: axp15060_reg@36 {
  367. compatible = "stf,axp15060-regulator";
  368. reg = <0x36>;
  369. };
  370. pmic: jh7110_evb_reg@50 {
  371. compatible = "starfive,jh7110-evb-regulator";
  372. reg = <0x50>;
  373. regulators {
  374. hdmi_1p8: ldo1 {
  375. regulator-name = "lp8733-ldo1";
  376. regulator-min-microvolt = <1800000>;
  377. regulator-max-microvolt = <1800000>;
  378. regulator-boot-on;
  379. regulator-always-on;
  380. };
  381. mipitx_1p8: ldo2 {
  382. regulator-name = "lp8733-ldo2";
  383. regulator-min-microvolt = <1800000>;
  384. regulator-max-microvolt = <1800000>;
  385. regulator-boot-on;
  386. regulator-always-on;
  387. };
  388. mipirx_1p8: ldo3 {
  389. regulator-name = "lp8733-ldo3";
  390. regulator-min-microvolt = <1800000>;
  391. regulator-max-microvolt = <1800000>;
  392. regulator-boot-on;
  393. regulator-always-on;
  394. };
  395. hdmi_0p9: ldo4 {
  396. regulator-name = "lp8733-ldo4";
  397. regulator-min-microvolt = <900000>;
  398. regulator-max-microvolt = <900000>;
  399. regulator-boot-on;
  400. regulator-always-on;
  401. };
  402. mipitx_0p9: ldo5 {
  403. regulator-name = "lp8733-ldo5";
  404. regulator-min-microvolt = <900000>;
  405. regulator-max-microvolt = <900000>;
  406. regulator-boot-on;
  407. regulator-always-on;
  408. };
  409. mipirx_0p9: ldo6 {
  410. regulator-name = "lp8733-ldo6";
  411. regulator-min-microvolt = <900000>;
  412. regulator-max-microvolt = <900000>;
  413. regulator-boot-on;
  414. regulator-always-on;
  415. };
  416. sdio_vdd: ldo7 {
  417. regulator-name = "lp8733-ldo7";
  418. regulator-min-microvolt = <1800000>;
  419. regulator-max-microvolt = <3300000>;
  420. regulator-boot-on;
  421. regulator-always-on;
  422. };
  423. };
  424. };
  425. };