Kconfig 33 KB

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  1. menu "x86 architecture"
  2. depends on X86
  3. config SYS_ARCH
  4. default "x86"
  5. choice
  6. prompt "Run U-Boot in 32/64-bit mode"
  7. default X86_RUN_32BIT
  8. help
  9. U-Boot can be built as a 32-bit binary which runs in 32-bit mode
  10. even on 64-bit machines. In this case SPL is not used, and U-Boot
  11. runs directly from the reset vector (via 16-bit start-up).
  12. Alternatively it can be run as a 64-bit binary, thus requiring a
  13. 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
  14. start-up) then jumps to U-Boot in 64-bit mode.
  15. For now, 32-bit mode is recommended, as 64-bit is still
  16. experimental and is missing a lot of features.
  17. config X86_RUN_32BIT
  18. bool "32-bit"
  19. help
  20. Build U-Boot as a 32-bit binary with no SPL. This is the currently
  21. supported normal setup. U-Boot will stay in 32-bit mode even on
  22. 64-bit machines. When booting a 64-bit kernel, U-Boot will switch
  23. to 64-bit just before starting the kernel. Only the bottom 4GB of
  24. memory can be accessed through normal means, although
  25. arch_phys_memset() can be used for basic access to other memory.
  26. config X86_RUN_64BIT
  27. bool "64-bit"
  28. select X86_64
  29. select SPL
  30. select SPL_SEPARATE_BSS
  31. help
  32. Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
  33. experimental and many features are missing. U-Boot SPL starts up,
  34. runs through the 16-bit and 32-bit init, then switches to 64-bit
  35. mode and jumps to U-Boot proper.
  36. endchoice
  37. config X86_64
  38. bool
  39. config SPL_X86_64
  40. bool
  41. depends on SPL
  42. choice
  43. prompt "Mainboard vendor"
  44. default VENDOR_EMULATION
  45. config VENDOR_ADVANTECH
  46. bool "advantech"
  47. config VENDOR_CONGATEC
  48. bool "congatec"
  49. config VENDOR_COREBOOT
  50. bool "coreboot"
  51. config VENDOR_DFI
  52. bool "dfi"
  53. config VENDOR_EFI
  54. bool "efi"
  55. config VENDOR_EMULATION
  56. bool "emulation"
  57. config VENDOR_GOOGLE
  58. bool "Google"
  59. config VENDOR_INTEL
  60. bool "Intel"
  61. endchoice
  62. # subarchitectures-specific options below
  63. config INTEL_MID
  64. bool "Intel MID platform support"
  65. select REGMAP
  66. select SYSCON
  67. help
  68. Select to build a U-Boot capable of supporting Intel MID
  69. (Mobile Internet Device) platform systems which do not have
  70. the PCI legacy interfaces.
  71. If you are building for a PC class system say N here.
  72. Intel MID platforms are based on an Intel processor and
  73. chipset which consume less power than most of the x86
  74. derivatives.
  75. # board-specific options below
  76. source "board/advantech/Kconfig"
  77. source "board/congatec/Kconfig"
  78. source "board/coreboot/Kconfig"
  79. source "board/dfi/Kconfig"
  80. source "board/efi/Kconfig"
  81. source "board/emulation/Kconfig"
  82. source "board/google/Kconfig"
  83. source "board/intel/Kconfig"
  84. # platform-specific options below
  85. source "arch/x86/cpu/apollolake/Kconfig"
  86. source "arch/x86/cpu/baytrail/Kconfig"
  87. source "arch/x86/cpu/braswell/Kconfig"
  88. source "arch/x86/cpu/broadwell/Kconfig"
  89. source "arch/x86/cpu/coreboot/Kconfig"
  90. source "arch/x86/cpu/ivybridge/Kconfig"
  91. source "arch/x86/cpu/efi/Kconfig"
  92. source "arch/x86/cpu/qemu/Kconfig"
  93. source "arch/x86/cpu/quark/Kconfig"
  94. source "arch/x86/cpu/queensbay/Kconfig"
  95. source "arch/x86/cpu/slimbootloader/Kconfig"
  96. source "arch/x86/cpu/tangier/Kconfig"
  97. # architecture-specific options below
  98. config AHCI
  99. default y
  100. config SYS_MALLOC_F_LEN
  101. default 0x800
  102. config RAMBASE
  103. hex
  104. default 0x100000
  105. config XIP_ROM_SIZE
  106. hex
  107. depends on X86_RESET_VECTOR
  108. default ROM_SIZE
  109. config CPU_ADDR_BITS
  110. int
  111. default 36
  112. config HPET_ADDRESS
  113. hex
  114. default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
  115. config SMM_TSEG
  116. bool
  117. config SMM_TSEG_SIZE
  118. hex
  119. config X86_RESET_VECTOR
  120. bool
  121. select BINMAN
  122. # The following options control where the 16-bit and 32-bit init lies
  123. # If SPL is enabled then it normally holds this init code, and U-Boot proper
  124. # is normally a 64-bit build.
  125. #
  126. # The 16-bit init refers to the reset vector and the small amount of code to
  127. # get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
  128. # or missing altogether if U-Boot is started from EFI or coreboot.
  129. #
  130. # The 32-bit init refers to processor init, running binary blobs including
  131. # FSP, setting up interrupts and anything else that needs to be done in
  132. # 32-bit code. It is normally in the same place as 16-bit init if that is
  133. # enabled (i.e. they are both in SPL, or both in U-Boot proper).
  134. config X86_16BIT_INIT
  135. bool
  136. depends on X86_RESET_VECTOR
  137. default y if X86_RESET_VECTOR && !SPL
  138. help
  139. This is enabled when 16-bit init is in U-Boot proper
  140. config SPL_X86_16BIT_INIT
  141. bool
  142. depends on X86_RESET_VECTOR
  143. default y if X86_RESET_VECTOR && SPL && !TPL
  144. help
  145. This is enabled when 16-bit init is in SPL
  146. config TPL_X86_16BIT_INIT
  147. bool
  148. depends on X86_RESET_VECTOR
  149. default y if X86_RESET_VECTOR && TPL
  150. help
  151. This is enabled when 16-bit init is in TPL
  152. config X86_32BIT_INIT
  153. bool
  154. depends on X86_RESET_VECTOR
  155. default y if X86_RESET_VECTOR && !SPL
  156. help
  157. This is enabled when 32-bit init is in U-Boot proper
  158. config SPL_X86_32BIT_INIT
  159. bool
  160. depends on X86_RESET_VECTOR
  161. default y if X86_RESET_VECTOR && SPL
  162. help
  163. This is enabled when 32-bit init is in SPL
  164. config USE_EARLY_BOARD_INIT
  165. bool
  166. config RESET_SEG_START
  167. hex
  168. depends on X86_RESET_VECTOR
  169. default 0xffff0000
  170. config RESET_VEC_LOC
  171. hex
  172. depends on X86_RESET_VECTOR
  173. default 0xfffffff0
  174. config SYS_X86_START16
  175. hex
  176. depends on X86_RESET_VECTOR
  177. default 0xfffff800
  178. config HAVE_X86_FIT
  179. bool
  180. help
  181. Enable inclusion of an Intel Firmware Interface Table (FIT) into the
  182. image. This table is supposed to point to microcode and the like. So
  183. far it is just a fixed table with the minimum set of headers, so that
  184. it is actually present.
  185. config X86_LOAD_FROM_32_BIT
  186. bool "Boot from a 32-bit program"
  187. help
  188. Define this to boot U-Boot from a 32-bit program which sets
  189. the GDT differently. This can be used to boot directly from
  190. any stage of coreboot, for example, bypassing the normal
  191. payload-loading feature.
  192. config BOARD_ROMSIZE_KB_512
  193. bool
  194. config BOARD_ROMSIZE_KB_1024
  195. bool
  196. config BOARD_ROMSIZE_KB_2048
  197. bool
  198. config BOARD_ROMSIZE_KB_4096
  199. bool
  200. config BOARD_ROMSIZE_KB_8192
  201. bool
  202. config BOARD_ROMSIZE_KB_16384
  203. bool
  204. choice
  205. prompt "ROM chip size"
  206. depends on X86_RESET_VECTOR
  207. default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
  208. default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
  209. default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
  210. default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
  211. default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
  212. default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
  213. help
  214. Select the size of the ROM chip you intend to flash U-Boot on.
  215. The build system will take care of creating a u-boot.rom file
  216. of the matching size.
  217. config UBOOT_ROMSIZE_KB_512
  218. bool "512 KB"
  219. help
  220. Choose this option if you have a 512 KB ROM chip.
  221. config UBOOT_ROMSIZE_KB_1024
  222. bool "1024 KB (1 MB)"
  223. help
  224. Choose this option if you have a 1024 KB (1 MB) ROM chip.
  225. config UBOOT_ROMSIZE_KB_2048
  226. bool "2048 KB (2 MB)"
  227. help
  228. Choose this option if you have a 2048 KB (2 MB) ROM chip.
  229. config UBOOT_ROMSIZE_KB_4096
  230. bool "4096 KB (4 MB)"
  231. help
  232. Choose this option if you have a 4096 KB (4 MB) ROM chip.
  233. config UBOOT_ROMSIZE_KB_8192
  234. bool "8192 KB (8 MB)"
  235. help
  236. Choose this option if you have a 8192 KB (8 MB) ROM chip.
  237. config UBOOT_ROMSIZE_KB_16384
  238. bool "16384 KB (16 MB)"
  239. help
  240. Choose this option if you have a 16384 KB (16 MB) ROM chip.
  241. endchoice
  242. # Map the config names to an integer (KB).
  243. config UBOOT_ROMSIZE_KB
  244. int
  245. default 512 if UBOOT_ROMSIZE_KB_512
  246. default 1024 if UBOOT_ROMSIZE_KB_1024
  247. default 2048 if UBOOT_ROMSIZE_KB_2048
  248. default 4096 if UBOOT_ROMSIZE_KB_4096
  249. default 8192 if UBOOT_ROMSIZE_KB_8192
  250. default 16384 if UBOOT_ROMSIZE_KB_16384
  251. # Map the config names to a hex value (bytes).
  252. config ROM_SIZE
  253. hex
  254. default 0x80000 if UBOOT_ROMSIZE_KB_512
  255. default 0x100000 if UBOOT_ROMSIZE_KB_1024
  256. default 0x200000 if UBOOT_ROMSIZE_KB_2048
  257. default 0x400000 if UBOOT_ROMSIZE_KB_4096
  258. default 0x800000 if UBOOT_ROMSIZE_KB_8192
  259. default 0xc00000 if UBOOT_ROMSIZE_KB_12288
  260. default 0x1000000 if UBOOT_ROMSIZE_KB_16384
  261. config HAVE_INTEL_ME
  262. bool "Platform requires Intel Management Engine"
  263. help
  264. Newer higher-end devices have an Intel Management Engine (ME)
  265. which is a very large binary blob (typically 1.5MB) which is
  266. required for the platform to work. This enforces a particular
  267. SPI flash format. You will need to supply the me.bin file in
  268. your board directory.
  269. config X86_RAMTEST
  270. bool "Perform a simple RAM test after SDRAM initialisation"
  271. help
  272. If there is something wrong with SDRAM then the platform will
  273. often crash within U-Boot or the kernel. This option enables a
  274. very simple RAM test that quickly checks whether the SDRAM seems
  275. to work correctly. It is not exhaustive but can save time by
  276. detecting obvious failures.
  277. config FLASH_DESCRIPTOR_FILE
  278. string "Flash descriptor binary filename"
  279. depends on HAVE_INTEL_ME || FSP_VERSION2
  280. default "descriptor.bin"
  281. help
  282. The filename of the file to use as flash descriptor in the
  283. board directory.
  284. config INTEL_ME_FILE
  285. string "Intel Management Engine binary filename"
  286. depends on HAVE_INTEL_ME
  287. default "me.bin"
  288. help
  289. The filename of the file to use as Intel Management Engine in the
  290. board directory.
  291. config USE_HOB
  292. bool "Use HOB (Hand-Off Block)"
  293. help
  294. Select this option to access HOB (Hand-Off Block) data structures
  295. and parse HOBs. This HOB infra structure can be reused with
  296. different solutions across different platforms.
  297. config HAVE_FSP
  298. bool "Add an Firmware Support Package binary"
  299. depends on !EFI
  300. select USE_HOB
  301. select HAS_ROM
  302. help
  303. Select this option to add an Firmware Support Package binary to
  304. the resulting U-Boot image. It is a binary blob which U-Boot uses
  305. to set up SDRAM and other chipset specific initialization.
  306. Note: Without this binary U-Boot will not be able to set up its
  307. SDRAM so will not boot.
  308. config USE_CAR
  309. bool "Use Cache-As-RAM (CAR) to get temporary RAM at start-up"
  310. default y if !HAVE_FSP
  311. help
  312. Select this option if your board uses CAR init code, typically in a
  313. car.S file, to get some initial memory for code execution. This is
  314. common with Intel CPUs which don't use FSP.
  315. choice
  316. prompt "FSP version"
  317. depends on HAVE_FSP
  318. default FSP_VERSION1
  319. help
  320. Selects the FSP version to use. Intel has published several versions
  321. of the FSP External Architecture Specification and this allows
  322. selection of the version number used by a particular SoC.
  323. config FSP_VERSION1
  324. bool "FSP version 1.x"
  325. help
  326. This covers versions 1.0 and 1.1a. See here for details:
  327. https://github.com/IntelFsp/fsp/wiki
  328. config FSP_VERSION2
  329. bool "FSP version 2.x"
  330. help
  331. This covers versions 2.0 and 2.1. See here for details:
  332. https://github.com/IntelFsp/fsp/wiki
  333. endchoice
  334. config FSP_FILE
  335. string "Firmware Support Package binary filename"
  336. depends on FSP_VERSION1
  337. default "fsp.bin"
  338. help
  339. The filename of the file to use as Firmware Support Package binary
  340. in the board directory.
  341. config FSP_ADDR
  342. hex "Firmware Support Package binary location"
  343. depends on FSP_VERSION1
  344. default 0xfffc0000
  345. help
  346. FSP is not Position Independent Code (PIC) and the whole FSP has to
  347. be rebased if it is placed at a location which is different from the
  348. perferred base address specified during the FSP build. Use Intel's
  349. Binary Configuration Tool (BCT) to do the rebase.
  350. The default base address of 0xfffc0000 indicates that the binary must
  351. be located at offset 0xc0000 from the beginning of a 1MB flash device.
  352. if FSP_VERSION2
  353. config FSP_FILE_T
  354. string "Firmware Support Package binary filename (Temp RAM)"
  355. default "fsp_t.bin"
  356. help
  357. The filename of the file to use for the temporary-RAM init phase from
  358. the Firmware Support Package binary. Put this in the board directory.
  359. It is used to set up an initial area of RAM which can be used for the
  360. stack and other purposes, while bringing up the main system DRAM.
  361. config FSP_ADDR_T
  362. hex "Firmware Support Package binary location (Temp RAM)"
  363. default 0xffff8000
  364. help
  365. FSP is not Position-Independent Code (PIC) and FSP components have to
  366. be rebased if placed at a location which is different from the
  367. perferred base address specified during the FSP build. Use Intel's
  368. Binary Configuration Tool (BCT) to do the rebase.
  369. config FSP_FILE_M
  370. string "Firmware Support Package binary filename (Memory Init)"
  371. default "fsp_m.bin"
  372. help
  373. The filename of the file to use for the RAM init phase from the
  374. Firmware Support Package binary. Put this in the board directory.
  375. It is used to set up the main system DRAM and runs in SPL, once
  376. temporary RAM (CAR) is working.
  377. config FSP_FILE_S
  378. string "Firmware Support Package binary filename (Silicon Init)"
  379. default "fsp_s.bin"
  380. help
  381. The filename of the file to use for the Silicon init phase from the
  382. Firmware Support Package binary. Put this in the board directory.
  383. It is used to set up the silicon to work correctly and must be
  384. executed after DRAM is running.
  385. config IFWI_INPUT_FILE
  386. string "Filename containing FIT (Firmware Interface Table) with IFWI"
  387. default "fitimage.bin"
  388. help
  389. The IFWI is obtained by running a tool on this file to extract the
  390. IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
  391. microcode and other internal items.
  392. endif
  393. config FSP_TEMP_RAM_ADDR
  394. hex
  395. depends on FSP_VERSION1
  396. default 0x2000000
  397. help
  398. Stack top address which is used in fsp_init() after DRAM is ready and
  399. CAR is disabled.
  400. config FSP_SYS_MALLOC_F_LEN
  401. hex
  402. depends on FSP_VERSION1
  403. default 0x100000
  404. help
  405. Additional size of malloc() pool before relocation.
  406. config FSP_USE_UPD
  407. bool
  408. depends on FSP_VERSION1
  409. default y if !NORTHBRIDGE_INTEL_IVYBRIDGE
  410. help
  411. Most FSPs use UPD data region for some FSP customization. But there
  412. are still some FSPs that might not even have UPD. For such FSPs,
  413. override this to n in their platform Kconfig files.
  414. config FSP_BROKEN_HOB
  415. bool
  416. depends on FSP_VERSION1
  417. help
  418. Indicate some buggy FSPs that does not report memory used by FSP
  419. itself as reserved in the resource descriptor HOB. Select this to
  420. tell U-Boot to do some additional work to ensure U-Boot relocation
  421. do not overwrite the important boot service data which is used by
  422. FSP, otherwise the subsequent call to fsp_notify() will fail.
  423. config ENABLE_MRC_CACHE
  424. bool "Enable MRC cache"
  425. depends on !EFI && !SYS_COREBOOT
  426. help
  427. Enable this feature to cause MRC data to be cached in NV storage
  428. to be used for speeding up boot time on future reboots and/or
  429. power cycles.
  430. For platforms that use Intel FSP for the memory initialization,
  431. please check FSP output HOB via U-Boot command 'fsp hob' to see
  432. if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp1/fsp_hob.h).
  433. If such GUID does not exist, MRC cache is not available on such
  434. platform (eg: Intel Queensbay), which means selecting this option
  435. here does not make any difference.
  436. config HAVE_MRC
  437. bool "Add a System Agent binary"
  438. select HAS_ROM
  439. depends on !HAVE_FSP
  440. help
  441. Select this option to add a System Agent binary to
  442. the resulting U-Boot image. MRC stands for Memory Reference Code.
  443. It is a binary blob which U-Boot uses to set up SDRAM.
  444. Note: Without this binary U-Boot will not be able to set up its
  445. SDRAM so will not boot.
  446. config CACHE_MRC_BIN
  447. bool
  448. depends on HAVE_MRC
  449. help
  450. Enable caching for the memory reference code binary. This uses an
  451. MTRR (memory type range register) to turn on caching for the section
  452. of SPI flash that contains the memory reference code. This makes
  453. SDRAM init run faster.
  454. config CACHE_MRC_SIZE_KB
  455. int
  456. depends on HAVE_MRC
  457. default 512
  458. help
  459. Sets the size of the cached area for the memory reference code.
  460. This ends at the end of SPI flash (address 0xffffffff) and is
  461. measured in KB. Typically this is set to 512, providing for 0.5MB
  462. of cached space.
  463. config DCACHE_RAM_BASE
  464. hex
  465. depends on HAVE_MRC
  466. help
  467. Sets the base of the data cache area in memory space. This is the
  468. start address of the cache-as-RAM (CAR) area and the address varies
  469. depending on the CPU. Once CAR is set up, read/write memory becomes
  470. available at this address and can be used temporarily until SDRAM
  471. is working.
  472. config DCACHE_RAM_SIZE
  473. hex
  474. depends on HAVE_MRC
  475. default 0x40000
  476. help
  477. Sets the total size of the data cache area in memory space. This
  478. sets the size of the cache-as-RAM (CAR) area. Note that much of the
  479. CAR space is required by the MRC. The CAR space available to U-Boot
  480. is normally at the start and typically extends to 1/4 or 1/2 of the
  481. available size.
  482. config DCACHE_RAM_MRC_VAR_SIZE
  483. hex
  484. depends on HAVE_MRC
  485. help
  486. This is the amount of CAR (Cache as RAM) reserved for use by the
  487. memory reference code. This depends on the implementation of the
  488. memory reference code and must be set correctly or the board will
  489. not boot.
  490. config HAVE_REFCODE
  491. bool "Add a Reference Code binary"
  492. help
  493. Select this option to add a Reference Code binary to the resulting
  494. U-Boot image. This is an Intel binary blob that handles system
  495. initialisation, in this case the PCH and System Agent.
  496. Note: Without this binary (on platforms that need it such as
  497. broadwell) U-Boot will be missing some critical setup steps.
  498. Various peripherals may fail to work.
  499. config HAVE_MICROCODE
  500. bool "Board requires a microcode binary"
  501. default y if !FSP_VERSION2
  502. help
  503. Enable this if the board requires microcode to be loaded on boot.
  504. Typically this is handed by the FSP for modern boards, but for
  505. some older boards, it must be programmed by U-Boot, and that form
  506. part of the image.
  507. config SMP
  508. bool "Enable Symmetric Multiprocessing"
  509. help
  510. Enable use of more than one CPU in U-Boot and the Operating System
  511. when loaded. Each CPU will be started up and information can be
  512. obtained using the 'cpu' command. If this option is disabled, then
  513. only one CPU will be enabled regardless of the number of CPUs
  514. available.
  515. config SMP_AP_WORK
  516. bool
  517. depends on SMP
  518. help
  519. Allow APs to do other work after initialisation instead of going
  520. to sleep.
  521. config MAX_CPUS
  522. int "Maximum number of CPUs permitted"
  523. depends on SMP
  524. default 4
  525. help
  526. When using multi-CPU chips it is possible for U-Boot to start up
  527. more than one CPU. The stack memory used by all of these CPUs is
  528. pre-allocated so at present U-Boot wants to know the maximum
  529. number of CPUs that may be present. Set this to at least as high
  530. as the number of CPUs in your system (it uses about 4KB of RAM for
  531. each CPU).
  532. config AP_STACK_SIZE
  533. hex
  534. depends on SMP
  535. default 0x1000
  536. help
  537. Each additional CPU started by U-Boot requires its own stack. This
  538. option sets the stack size used by each CPU and directly affects
  539. the memory used by this initialisation process. Typically 4KB is
  540. enough space.
  541. config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
  542. bool
  543. help
  544. This option indicates that the turbo mode setting is not package
  545. scoped. i.e. turbo_enable() needs to be called on not just the
  546. bootstrap processor (BSP).
  547. config HAVE_VGA_BIOS
  548. bool "Add a VGA BIOS image"
  549. help
  550. Select this option if you have a VGA BIOS image that you would
  551. like to add to your ROM.
  552. config VGA_BIOS_FILE
  553. string "VGA BIOS image filename"
  554. depends on HAVE_VGA_BIOS
  555. default "vga.bin"
  556. help
  557. The filename of the VGA BIOS image in the board directory.
  558. config VGA_BIOS_ADDR
  559. hex "VGA BIOS image location"
  560. depends on HAVE_VGA_BIOS
  561. default 0xfff90000
  562. help
  563. The location of VGA BIOS image in the SPI flash. For example, base
  564. address of 0xfff90000 indicates that the image will be put at offset
  565. 0x90000 from the beginning of a 1MB flash device.
  566. config HAVE_VBT
  567. bool "Add a Video BIOS Table (VBT) image"
  568. depends on HAVE_FSP
  569. help
  570. Select this option if you have a Video BIOS Table (VBT) image that
  571. you would like to add to your ROM. This is normally required if you
  572. are using an Intel FSP firmware that is complaint with spec 1.1 or
  573. later to initialize the integrated graphics device (IGD).
  574. Video BIOS Table, or VBT, provides platform and board specific
  575. configuration information to the driver that is not discoverable
  576. or available through other means. By other means the most used
  577. method here is to read EDID table from the attached monitor, over
  578. Display Data Channel (DDC) using two pin I2C serial interface. VBT
  579. configuration is related to display hardware and is available via
  580. the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
  581. config VBT_FILE
  582. string "Video BIOS Table (VBT) image filename"
  583. depends on HAVE_VBT
  584. default "vbt.bin"
  585. help
  586. The filename of the file to use as Video BIOS Table (VBT) image
  587. in the board directory.
  588. config VBT_ADDR
  589. hex "Video BIOS Table (VBT) image location"
  590. depends on HAVE_VBT
  591. default 0xfff90000
  592. help
  593. The location of Video BIOS Table (VBT) image in the SPI flash. For
  594. example, base address of 0xfff90000 indicates that the image will
  595. be put at offset 0x90000 from the beginning of a 1MB flash device.
  596. config VIDEO_FSP
  597. bool "Enable FSP framebuffer driver support"
  598. depends on HAVE_VBT && DM_VIDEO
  599. help
  600. Turn on this option to enable a framebuffer driver when U-Boot is
  601. using Video BIOS Table (VBT) image for FSP firmware to initialize
  602. the integrated graphics device.
  603. config ROM_TABLE_ADDR
  604. hex
  605. default 0xf0000
  606. help
  607. All x86 tables happen to like the address range from 0x0f0000
  608. to 0x100000. We use 0xf0000 as the starting address to store
  609. those tables, including PIRQ routing table, Multi-Processor
  610. table and ACPI table.
  611. config ROM_TABLE_SIZE
  612. hex
  613. default 0x10000
  614. config HAVE_ITSS
  615. bool "Enable ITSS"
  616. help
  617. Select this to include the driver for the Interrupt Timer
  618. Subsystem (ITSS) which is found on several Intel devices.
  619. config HAVE_P2SB
  620. bool "Enable P2SB"
  621. depends on P2SB
  622. help
  623. Select this to include the driver for the Primary to
  624. Sideband Bridge (P2SB) which is found on several Intel
  625. devices.
  626. menu "System tables"
  627. depends on !EFI && !SYS_COREBOOT
  628. config GENERATE_PIRQ_TABLE
  629. bool "Generate a PIRQ table"
  630. help
  631. Generate a PIRQ routing table for this board. The PIRQ routing table
  632. is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
  633. at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
  634. It specifies the interrupt router information as well how all the PCI
  635. devices' interrupt pins are wired to PIRQs.
  636. config GENERATE_SFI_TABLE
  637. bool "Generate a SFI (Simple Firmware Interface) table"
  638. help
  639. The Simple Firmware Interface (SFI) provides a lightweight method
  640. for platform firmware to pass information to the operating system
  641. via static tables in memory. Kernel SFI support is required to
  642. boot on SFI-only platforms. If you have ACPI tables then these are
  643. used instead.
  644. U-Boot writes this table in write_sfi_table() just before booting
  645. the OS.
  646. For more information, see http://simplefirmware.org
  647. config GENERATE_MP_TABLE
  648. bool "Generate an MP (Multi-Processor) table"
  649. help
  650. Generate an MP (Multi-Processor) table for this board. The MP table
  651. provides a way for the operating system to support for symmetric
  652. multiprocessing as well as symmetric I/O interrupt handling with
  653. the local APIC and I/O APIC.
  654. config GENERATE_ACPI_TABLE
  655. bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
  656. select QFW if QEMU
  657. help
  658. The Advanced Configuration and Power Interface (ACPI) specification
  659. provides an open standard for device configuration and management
  660. by the operating system. It defines platform-independent interfaces
  661. for configuration and power management monitoring.
  662. config ACPI_GNVS_EXTERNAL
  663. bool
  664. help
  665. Put the GNVS (Global Non-Volatile Sleeping) table separate from the
  666. DSDT and add a pointer to the table from the DSDT. This allows
  667. U-Boot to better control the address of the GNVS.
  668. endmenu
  669. config HAVE_ACPI_RESUME
  670. bool "Enable ACPI S3 resume"
  671. select ENABLE_MRC_CACHE
  672. help
  673. Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
  674. state where all system context is lost except system memory. U-Boot
  675. is responsible for restoring the machine state as it was before sleep.
  676. It needs restore the memory controller, without overwriting memory
  677. which is not marked as reserved. For the peripherals which lose their
  678. registers, U-Boot needs to write the original value. When everything
  679. is done, U-Boot needs to find out the wakeup vector provided by OSes
  680. and jump there.
  681. config S3_VGA_ROM_RUN
  682. bool "Re-run VGA option ROMs on S3 resume"
  683. depends on HAVE_ACPI_RESUME
  684. help
  685. Execute VGA option ROMs in U-Boot when resuming from S3. Normally
  686. this is needed when graphics console is being used in the kernel.
  687. Turning it off can reduce some resume time, but be aware that your
  688. graphics console won't work without VGA options ROMs. Set it to N
  689. if your kernel is only on a serial console.
  690. config STACK_SIZE_RESUME
  691. hex
  692. depends on HAVE_ACPI_RESUME
  693. default 0x1000
  694. help
  695. Estimated U-Boot's runtime stack size that needs to be reserved
  696. during an ACPI S3 resume.
  697. config MAX_PIRQ_LINKS
  698. int
  699. default 8
  700. help
  701. This variable specifies the number of PIRQ interrupt links which are
  702. routable. On most older chipsets, this is 4, PIRQA through PIRQD.
  703. Some newer chipsets offer more than four links, commonly up to PIRQH.
  704. config IRQ_SLOT_COUNT
  705. int
  706. default 128
  707. help
  708. U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
  709. which in turns forms a table of exact 4KiB. The default value 128
  710. should be enough for most boards. If this does not fit your board,
  711. change it according to your needs.
  712. config PCIE_ECAM_BASE
  713. hex
  714. default 0xe0000000
  715. help
  716. This is the memory-mapped address of PCI configuration space, which
  717. is only available through the Enhanced Configuration Access
  718. Mechanism (ECAM) with PCI Express. It can be set up almost
  719. anywhere. Before it is set up, it is possible to access PCI
  720. configuration space through I/O access, but memory access is more
  721. convenient. Using this, PCI can be scanned and configured. This
  722. should be set to a region that does not conflict with memory
  723. assigned to PCI devices - i.e. the memory and prefetch regions, as
  724. passed to pci_set_region().
  725. config PCIE_ECAM_SIZE
  726. hex
  727. default 0x10000000
  728. help
  729. This is the size of memory-mapped address of PCI configuration space,
  730. which is only available through the Enhanced Configuration Access
  731. Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
  732. so a default 0x10000000 size covers all of the 256 buses which is the
  733. maximum number of PCI buses as defined by the PCI specification.
  734. config I8259_PIC
  735. bool "Enable Intel 8259 compatible interrupt controller"
  736. default y
  737. help
  738. Intel 8259 ISA compatible chipset incorporates two 8259 (master and
  739. slave) interrupt controllers. Include this to have U-Boot set up
  740. the interrupt correctly.
  741. config APIC
  742. bool "Enable Intel Advanced Programmable Interrupt Controller"
  743. default y
  744. help
  745. The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
  746. for catching interrupts and distributing them to one or more CPU
  747. cores. In most cases there are some LAPICs (local) for each core and
  748. one I/O APIC. This conjunction is found on most modern x86 systems.
  749. config PINCTRL_ICH6
  750. bool
  751. help
  752. Intel ICH6 compatible chipset pinctrl driver. It needs to work
  753. together with the ICH6 compatible gpio driver.
  754. config I8254_TIMER
  755. bool
  756. default y
  757. help
  758. Intel 8254 timer contains three counters which have fixed uses.
  759. Include this to have U-Boot set up the timer correctly.
  760. config SEABIOS
  761. bool "Support booting SeaBIOS"
  762. help
  763. SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
  764. It can run in an emulator or natively on X86 hardware with the use
  765. of coreboot/U-Boot. By turning on this option, U-Boot prepares
  766. all the configuration tables that are necessary to boot SeaBIOS.
  767. Check http://www.seabios.org/SeaBIOS for details.
  768. config HIGH_TABLE_SIZE
  769. hex "Size of configuration tables which reside in high memory"
  770. default 0x10000
  771. depends on SEABIOS
  772. help
  773. SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
  774. configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
  775. puts a copy of configuration tables in high memory region which
  776. is reserved on the stack before relocation. The region size is
  777. determined by this option.
  778. Increse it if the default size does not fit the board's needs.
  779. This is most likely due to a large ACPI DSDT table is used.
  780. config INTEL_CAR_CQOS
  781. bool "Support Intel Cache Quality of Service"
  782. help
  783. Cache Quality of Service allows more fine-grained control of cache
  784. usage. As result, it is possible to set up a portion of L2 cache for
  785. CAR and use the remainder for actual caching.
  786. #
  787. # Each bit in QOS mask controls this many bytes. This is calculated as:
  788. # (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
  789. #
  790. config CACHE_QOS_SIZE_PER_BIT
  791. hex
  792. depends on INTEL_CAR_CQOS
  793. default 0x20000 # 128 KB
  794. config X86_OFFSET_U_BOOT
  795. hex "Offset of U-Boot in ROM image"
  796. depends on HAVE_SYS_TEXT_BASE
  797. default SYS_TEXT_BASE
  798. config X86_OFFSET_SPL
  799. hex "Offset of SPL in ROM image"
  800. depends on SPL && X86
  801. default SPL_TEXT_BASE
  802. config ACPI_GPE
  803. bool "Support ACPI general-purpose events"
  804. help
  805. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  806. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  807. needs access to these interrupts. This can happen when it uses a
  808. peripheral that is set up to use GPEs and so cannot use the normal
  809. GPIO mechanism for polling an input.
  810. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  811. config SPL_ACPI_GPE
  812. bool "Support ACPI general-purpose events in SPL"
  813. help
  814. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  815. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  816. needs access to these interrupts. This can happen when it uses a
  817. peripheral that is set up to use GPEs and so cannot use the normal
  818. GPIO mechanism for polling an input.
  819. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  820. config TPL_ACPI_GPE
  821. bool "Support ACPI general-purpose events in TPL"
  822. help
  823. Enable a driver for ACPI GPEs to allow peripherals to send interrupts
  824. via ACPI to the OS. In U-Boot this is only used when U-Boot itself
  825. needs access to these interrupts. This can happen when it uses a
  826. peripheral that is set up to use GPEs and so cannot use the normal
  827. GPIO mechanism for polling an input.
  828. See https://queue.acm.org/blogposting.cfm?id=18977 for more info
  829. config SA_PCIEX_LENGTH
  830. hex
  831. default 0x10000000 if (PCIEX_LENGTH_256MB)
  832. default 0x8000000 if (PCIEX_LENGTH_128MB)
  833. default 0x4000000 if (PCIEX_LENGTH_64MB)
  834. default 0x10000000
  835. help
  836. This option allows you to select length of PCIEX region.
  837. config PCIEX_LENGTH_256MB
  838. bool
  839. config PCIEX_LENGTH_128MB
  840. bool
  841. config PCIEX_LENGTH_64MB
  842. bool
  843. config INTEL_SOC
  844. bool
  845. help
  846. This is enabled on Intel SoCs that can support various advanced
  847. features such as power management (requiring asm/arch/pm.h), system
  848. agent (asm/arch/systemagent.h) and an I/O map for ACPI
  849. (asm/arch/iomap.h).
  850. This cannot be selected in a defconfig file. It must be enabled by a
  851. 'select' in the SoC's Kconfig.
  852. if INTEL_SOC
  853. config INTEL_ACPIGEN
  854. bool "Support ACPI table generation for Intel SoCs"
  855. depends on ACPIGEN
  856. help
  857. This option adds some functions used for programmatic generation of
  858. ACPI tables on Intel SoCs. This provides features for writing CPU
  859. information such as P states and T stages. Also included is a way
  860. to create a GNVS table and set it up.
  861. config INTEL_GMA_ACPI
  862. bool "Generate ACPI table for Intel GMA graphics"
  863. help
  864. The Intel GMA graphics driver in Linux expects an ACPI table
  865. which describes the layout of the registers and the display
  866. connected to the device. Enable this option to create this
  867. table so that graphics works correctly.
  868. config INTEL_GENERIC_WIFI
  869. bool "Enable generation of ACPI tables for Intel WiFi"
  870. help
  871. Select this option to provide code to a build generic WiFi ACPI table
  872. for Intel WiFi devices. This is not a WiFi driver and offers no
  873. network functionality. It is only here to generate the ACPI tables
  874. required by Linux.
  875. config INTEL_GMA_SWSMISCI
  876. bool
  877. help
  878. Select this option for Atom-based platforms which use the SWSMISCI
  879. register (0xe0) rather than the SWSCI register (0xe8).
  880. endif # INTEL_SOC
  881. config COREBOOT_SYSINFO
  882. bool "Support reading coreboot sysinfo"
  883. default y if SYS_COREBOOT
  884. help
  885. Select this option to read the coreboot sysinfo table on start-up,
  886. if present. This is written by coreboot before it exits and provides
  887. various pieces of information about the running system, including
  888. display, memory and build information. It is stored in
  889. struct sysinfo_t after parsing by get_coreboot_info().
  890. config SPL_COREBOOT_SYSINFO
  891. bool "Support reading coreboot sysinfo"
  892. depends on SPL
  893. default y if COREBOOT_SYSINFO
  894. help
  895. Select this option to read the coreboot sysinfo table in SPL,
  896. if present. This is written by coreboot before it exits and provides
  897. various pieces of information about the running system, including
  898. display, memory and build information. It is stored in
  899. struct sysinfo_t after parsing by get_coreboot_info().
  900. endmenu