Kconfig 30 KB

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  1. if ARCH_SUNXI
  2. config SPL_LDSCRIPT
  3. default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
  4. config IDENT_STRING
  5. default " Allwinner Technology"
  6. config DRAM_SUN4I
  7. bool
  8. help
  9. Select this dram controller driver for Sun4/5/7i platforms,
  10. like A10/A13/A20.
  11. config DRAM_SUN6I
  12. bool
  13. help
  14. Select this dram controller driver for Sun6i platforms,
  15. like A31/A31s.
  16. config DRAM_SUN8I_A23
  17. bool
  18. help
  19. Select this dram controller driver for Sun8i platforms,
  20. for A23 SOC.
  21. config DRAM_SUN8I_A33
  22. bool
  23. help
  24. Select this dram controller driver for Sun8i platforms,
  25. for A33 SOC.
  26. config DRAM_SUN8I_A83T
  27. bool
  28. help
  29. Select this dram controller driver for Sun8i platforms,
  30. for A83T SOC.
  31. config DRAM_SUN9I
  32. bool
  33. help
  34. Select this dram controller driver for Sun9i platforms,
  35. like A80.
  36. config DRAM_SUN50I_H6
  37. bool
  38. help
  39. Select this dram controller driver for some sun50i platforms,
  40. like H6.
  41. config DRAM_SUN50I_H616
  42. bool
  43. help
  44. Select this dram controller driver for some sun50i platforms,
  45. like H616.
  46. if DRAM_SUN50I_H616
  47. config DRAM_SUN50I_H616_WRITE_LEVELING
  48. bool "H616 DRAM write leveling"
  49. ---help---
  50. Select this when DRAM on your H616 board needs write leveling.
  51. config DRAM_SUN50I_H616_READ_CALIBRATION
  52. bool "H616 DRAM read calibration"
  53. ---help---
  54. Select this when DRAM on your H616 board needs read calibration.
  55. config DRAM_SUN50I_H616_READ_TRAINING
  56. bool "H616 DRAM read training"
  57. ---help---
  58. Select this when DRAM on your H616 board needs read training.
  59. config DRAM_SUN50I_H616_WRITE_TRAINING
  60. bool "H616 DRAM write training"
  61. ---help---
  62. Select this when DRAM on your H616 board needs write training.
  63. config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
  64. bool "H616 DRAM bit delay compensation"
  65. ---help---
  66. Select this when DRAM on your H616 board needs bit delay
  67. compensation.
  68. config DRAM_SUN50I_H616_UNKNOWN_FEATURE
  69. bool "H616 DRAM unknown feature"
  70. ---help---
  71. Select this when DRAM on your H616 board needs this unknown
  72. feature.
  73. endif
  74. config SUN6I_P2WI
  75. bool "Allwinner sun6i internal P2WI controller"
  76. help
  77. If you say yes to this option, support will be included for the
  78. P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
  79. SOCs.
  80. The P2WI looks like an SMBus controller (which supports only byte
  81. accesses), except that it only supports one slave device.
  82. This interface is used to connect to specific PMIC devices (like the
  83. AXP221).
  84. config SUN6I_PRCM
  85. bool
  86. help
  87. Support for the PRCM (Power/Reset/Clock Management) unit available
  88. in A31 SoC.
  89. config AXP_PMIC_BUS
  90. bool "Sunxi AXP PMIC bus access helpers"
  91. help
  92. Select this PMIC bus access helpers for Sunxi platform PRCM or other
  93. AXP family PMIC devices.
  94. config SUN8I_RSB
  95. bool "Allwinner sunXi Reduced Serial Bus Driver"
  96. help
  97. Say y here to enable support for Allwinner's Reduced Serial Bus
  98. (RSB) support. This controller is responsible for communicating
  99. with various RSB based devices, such as AXP223, AXP8XX PMICs,
  100. and AC100/AC200 ICs.
  101. config SUNXI_SRAM_ADDRESS
  102. hex
  103. default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
  104. default 0x20000 if SUN50I_GEN_H6
  105. default 0x0
  106. ---help---
  107. Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
  108. with the first SRAM region being located at address 0.
  109. Some newer SoCs map the boot ROM at address 0 instead and move the
  110. SRAM to a different address.
  111. config SUNXI_A64_TIMER_ERRATUM
  112. bool
  113. # Note only one of these may be selected at a time! But hidden choices are
  114. # not supported by Kconfig
  115. config SUNXI_GEN_SUN4I
  116. bool
  117. ---help---
  118. Select this for sunxi SoCs which have resets and clocks set up
  119. as the original A10 (mach-sun4i).
  120. config SUNXI_GEN_SUN6I
  121. bool
  122. ---help---
  123. Select this for sunxi SoCs which have sun6i like periphery, like
  124. separate ahb reset control registers, custom pmic bus, new style
  125. watchdog, etc.
  126. config SUN50I_GEN_H6
  127. bool
  128. select FIT
  129. select SPL_LOAD_FIT
  130. select MMC_SUNXI_HAS_NEW_MODE
  131. select SUPPORT_SPL
  132. ---help---
  133. Select this for sunxi SoCs which have H6 like peripherals, clocks
  134. and memory map.
  135. config SUNXI_DRAM_DW
  136. bool
  137. ---help---
  138. Select this for sunxi SoCs which uses a DRAM controller like the
  139. DesignWare controller used in H3, mainly SoCs after H3, which do
  140. not have official open-source DRAM initialization code, but can
  141. use modified H3 DRAM initialization code.
  142. if SUNXI_DRAM_DW
  143. config SUNXI_DRAM_DW_16BIT
  144. bool
  145. ---help---
  146. Select this for sunxi SoCs with DesignWare DRAM controller and
  147. have only 16-bit memory buswidth.
  148. config SUNXI_DRAM_DW_32BIT
  149. bool
  150. ---help---
  151. Select this for sunxi SoCs with DesignWare DRAM controller with
  152. 32-bit memory buswidth.
  153. endif
  154. config MACH_SUNXI_H3_H5
  155. bool
  156. select DM_I2C
  157. select PHY_SUN4I_USB
  158. select SUNXI_DE2
  159. select SUNXI_DRAM_DW
  160. select SUNXI_DRAM_DW_32BIT
  161. select SUNXI_GEN_SUN6I
  162. select SUPPORT_SPL
  163. # TODO: try out A80's 8GiB DRAM space
  164. config SUNXI_DRAM_MAX_SIZE
  165. hex
  166. default 0x100000000 if MACH_SUN50I_H616
  167. default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
  168. default 0x80000000
  169. choice
  170. prompt "Sunxi SoC Variant"
  171. optional
  172. config MACH_SUN4I
  173. bool "sun4i (Allwinner A10)"
  174. select CPU_V7A
  175. select ARM_CORTEX_CPU_IS_UP
  176. select PHY_SUN4I_USB
  177. select DRAM_SUN4I
  178. select SUNXI_GEN_SUN4I
  179. select SUPPORT_SPL
  180. imply SPL_SYS_I2C_LEGACY
  181. imply SYS_I2C_LEGACY
  182. config MACH_SUN5I
  183. bool "sun5i (Allwinner A13)"
  184. select CPU_V7A
  185. select ARM_CORTEX_CPU_IS_UP
  186. select DRAM_SUN4I
  187. select PHY_SUN4I_USB
  188. select SUNXI_GEN_SUN4I
  189. select SUPPORT_SPL
  190. imply CONS_INDEX_2 if !DM_SERIAL
  191. imply SPL_SYS_I2C_LEGACY
  192. imply SYS_I2C_LEGACY
  193. config MACH_SUN6I
  194. bool "sun6i (Allwinner A31)"
  195. select CPU_V7A
  196. select CPU_V7_HAS_NONSEC
  197. select CPU_V7_HAS_VIRT
  198. select ARCH_SUPPORT_PSCI
  199. select DRAM_SUN6I
  200. select PHY_SUN4I_USB
  201. select SUN6I_P2WI
  202. select SUN6I_PRCM
  203. select SUNXI_GEN_SUN6I
  204. select SUPPORT_SPL
  205. select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  206. config MACH_SUN7I
  207. bool "sun7i (Allwinner A20)"
  208. select CPU_V7A
  209. select CPU_V7_HAS_NONSEC
  210. select CPU_V7_HAS_VIRT
  211. select ARCH_SUPPORT_PSCI
  212. select DRAM_SUN4I
  213. select PHY_SUN4I_USB
  214. select SUNXI_GEN_SUN4I
  215. select SUPPORT_SPL
  216. select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  217. imply SPL_SYS_I2C_LEGACY
  218. imply SYS_I2C_LEGACY
  219. config MACH_SUN8I_A23
  220. bool "sun8i (Allwinner A23)"
  221. select CPU_V7A
  222. select CPU_V7_HAS_NONSEC
  223. select CPU_V7_HAS_VIRT
  224. select ARCH_SUPPORT_PSCI
  225. select DRAM_SUN8I_A23
  226. select PHY_SUN4I_USB
  227. select SUNXI_GEN_SUN6I
  228. select SUPPORT_SPL
  229. select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  230. imply CONS_INDEX_5 if !DM_SERIAL
  231. config MACH_SUN8I_A33
  232. bool "sun8i (Allwinner A33)"
  233. select CPU_V7A
  234. select CPU_V7_HAS_NONSEC
  235. select CPU_V7_HAS_VIRT
  236. select ARCH_SUPPORT_PSCI
  237. select DRAM_SUN8I_A33
  238. select PHY_SUN4I_USB
  239. select SUNXI_GEN_SUN6I
  240. select SUPPORT_SPL
  241. select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  242. imply CONS_INDEX_5 if !DM_SERIAL
  243. config MACH_SUN8I_A83T
  244. bool "sun8i (Allwinner A83T)"
  245. select CPU_V7A
  246. select DRAM_SUN8I_A83T
  247. select PHY_SUN4I_USB
  248. select SUNXI_GEN_SUN6I
  249. select MMC_SUNXI_HAS_NEW_MODE
  250. select MMC_SUNXI_HAS_MODE_SWITCH
  251. select SUPPORT_SPL
  252. config MACH_SUN8I_H3
  253. bool "sun8i (Allwinner H3)"
  254. select CPU_V7A
  255. select CPU_V7_HAS_NONSEC
  256. select CPU_V7_HAS_VIRT
  257. select ARCH_SUPPORT_PSCI
  258. select MACH_SUNXI_H3_H5
  259. select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  260. config MACH_SUN8I_R40
  261. bool "sun8i (Allwinner R40)"
  262. select CPU_V7A
  263. select CPU_V7_HAS_NONSEC
  264. select CPU_V7_HAS_VIRT
  265. select ARCH_SUPPORT_PSCI
  266. select SUNXI_GEN_SUN6I
  267. select MMC_SUNXI_HAS_NEW_MODE
  268. select SUPPORT_SPL
  269. select SUNXI_DRAM_DW
  270. select SUNXI_DRAM_DW_32BIT
  271. select PHY_SUN4I_USB
  272. imply SPL_SYS_I2C_LEGACY
  273. config MACH_SUN8I_V3S
  274. bool "sun8i (Allwinner V3/V3s/S3/S3L)"
  275. select CPU_V7A
  276. select CPU_V7_HAS_NONSEC
  277. select CPU_V7_HAS_VIRT
  278. select ARCH_SUPPORT_PSCI
  279. select SUNXI_GEN_SUN6I
  280. select SUNXI_DRAM_DW
  281. select SUNXI_DRAM_DW_16BIT
  282. select SUPPORT_SPL
  283. select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  284. config MACH_SUN9I
  285. bool "sun9i (Allwinner A80)"
  286. select CPU_V7A
  287. select DRAM_SUN9I
  288. select SUN6I_PRCM
  289. select SUNXI_GEN_SUN6I
  290. select SUN8I_RSB
  291. select SUPPORT_SPL
  292. config MACH_SUN50I
  293. bool "sun50i (Allwinner A64)"
  294. select ARM64
  295. select SPI
  296. select DM_I2C
  297. select DM_SPI if SPI
  298. select DM_SPI_FLASH
  299. select PHY_SUN4I_USB
  300. select SUN6I_PRCM
  301. select SUNXI_DE2
  302. select SUNXI_GEN_SUN6I
  303. select MMC_SUNXI_HAS_NEW_MODE
  304. select SUPPORT_SPL
  305. select SUNXI_DRAM_DW
  306. select SUNXI_DRAM_DW_32BIT
  307. select FIT
  308. select SPL_LOAD_FIT
  309. select SUNXI_A64_TIMER_ERRATUM
  310. config MACH_SUN50I_H5
  311. bool "sun50i (Allwinner H5)"
  312. select ARM64
  313. select MACH_SUNXI_H3_H5
  314. select MMC_SUNXI_HAS_NEW_MODE
  315. select FIT
  316. select SPL_LOAD_FIT
  317. config MACH_SUN50I_H6
  318. bool "sun50i (Allwinner H6)"
  319. select ARM64
  320. select PHY_SUN4I_USB
  321. select DRAM_SUN50I_H6
  322. select SUN50I_GEN_H6
  323. config MACH_SUN50I_H616
  324. bool "sun50i (Allwinner H616)"
  325. select ARM64
  326. select DRAM_SUN50I_H616
  327. select SUN50I_GEN_H6
  328. endchoice
  329. # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
  330. config MACH_SUN8I
  331. bool
  332. select SUN8I_RSB
  333. select SUN6I_PRCM
  334. default y if MACH_SUN8I_A23
  335. default y if MACH_SUN8I_A33
  336. default y if MACH_SUN8I_A83T
  337. default y if MACH_SUNXI_H3_H5
  338. default y if MACH_SUN8I_R40
  339. default y if MACH_SUN8I_V3S
  340. config RESERVE_ALLWINNER_BOOT0_HEADER
  341. bool "reserve space for Allwinner boot0 header"
  342. select ENABLE_ARM_SOC_BOOT0_HOOK
  343. ---help---
  344. Prepend a 1536 byte (empty) header to the U-Boot image file, to be
  345. filled with magic values post build. The Allwinner provided boot0
  346. blob relies on this information to load and execute U-Boot.
  347. Only needed on 64-bit Allwinner boards so far when using boot0.
  348. config ARM_BOOT_HOOK_RMR
  349. bool
  350. depends on ARM64
  351. default y
  352. select ENABLE_ARM_SOC_BOOT0_HOOK
  353. ---help---
  354. Insert some ARM32 code at the very beginning of the U-Boot binary
  355. which uses an RMR register write to bring the core into AArch64 mode.
  356. The very first instruction acts as a switch, since it's carefully
  357. chosen to be a NOP in one mode and a branch in the other, so the
  358. code would only be executed if not already in AArch64.
  359. This allows both the SPL and the U-Boot proper to be entered in
  360. either mode and switch to AArch64 if needed.
  361. if SUNXI_DRAM_DW || DRAM_SUN50I_H6
  362. config SUNXI_DRAM_DDR3
  363. bool
  364. config SUNXI_DRAM_DDR2
  365. bool
  366. config SUNXI_DRAM_LPDDR3
  367. bool
  368. choice
  369. prompt "DRAM Type and Timing"
  370. default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
  371. default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
  372. config SUNXI_DRAM_DDR3_1333
  373. bool "DDR3 1333"
  374. select SUNXI_DRAM_DDR3
  375. ---help---
  376. This option is the original only supported memory type, which suits
  377. many H3/H5/A64 boards available now.
  378. config SUNXI_DRAM_LPDDR3_STOCK
  379. bool "LPDDR3 with Allwinner stock configuration"
  380. select SUNXI_DRAM_LPDDR3
  381. ---help---
  382. This option is the LPDDR3 timing used by the stock boot0 by
  383. Allwinner.
  384. config SUNXI_DRAM_H6_LPDDR3
  385. bool "LPDDR3 DRAM chips on the H6 DRAM controller"
  386. select SUNXI_DRAM_LPDDR3
  387. depends on DRAM_SUN50I_H6
  388. ---help---
  389. This option is the LPDDR3 timing used by the stock boot0 by
  390. Allwinner.
  391. config SUNXI_DRAM_H6_DDR3_1333
  392. bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
  393. select SUNXI_DRAM_DDR3
  394. depends on DRAM_SUN50I_H6
  395. ---help---
  396. This option is the DDR3 timing used by the boot0 on H6 TV boxes
  397. which use a DDR3-1333 timing.
  398. config SUNXI_DRAM_DDR2_V3S
  399. bool "DDR2 found in V3s chip"
  400. select SUNXI_DRAM_DDR2
  401. depends on MACH_SUN8I_V3S
  402. ---help---
  403. This option is only for the DDR2 memory chip which is co-packaged in
  404. Allwinner V3s SoC.
  405. endchoice
  406. endif
  407. config DRAM_TYPE
  408. int "sunxi dram type"
  409. depends on MACH_SUN8I_A83T
  410. default 3
  411. ---help---
  412. Set the dram type, 3: DDR3, 7: LPDDR3
  413. config DRAM_CLK
  414. int "sunxi dram clock speed"
  415. default 792 if MACH_SUN9I
  416. default 648 if MACH_SUN8I_R40
  417. default 312 if MACH_SUN6I || MACH_SUN8I
  418. default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
  419. MACH_SUN8I_V3S
  420. default 672 if MACH_SUN50I
  421. default 744 if MACH_SUN50I_H6
  422. default 720 if MACH_SUN50I_H616
  423. ---help---
  424. Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
  425. must be a multiple of 24. For the sun9i (A80), the tested values
  426. (for DDR3-1600) are 312 to 792.
  427. if MACH_SUN5I || MACH_SUN7I
  428. config DRAM_MBUS_CLK
  429. int "sunxi mbus clock speed"
  430. default 300
  431. ---help---
  432. Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
  433. endif
  434. config DRAM_ZQ
  435. int "sunxi dram zq value"
  436. depends on !MACH_SUN50I_H616
  437. default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
  438. MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
  439. default 127 if MACH_SUN7I
  440. default 14779 if MACH_SUN8I_V3S
  441. default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
  442. default 4145117 if MACH_SUN9I
  443. default 3881915 if MACH_SUN50I
  444. ---help---
  445. Set the dram zq value.
  446. config DRAM_ODT_EN
  447. bool "sunxi dram odt enable"
  448. default y if MACH_SUN8I_A23
  449. default y if MACH_SUNXI_H3_H5
  450. default y if MACH_SUN8I_R40
  451. default y if MACH_SUN50I
  452. default y if MACH_SUN50I_H6
  453. default y if MACH_SUN50I_H616
  454. ---help---
  455. Select this to enable dram odt (on die termination).
  456. if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
  457. config DRAM_EMR1
  458. int "sunxi dram emr1 value"
  459. default 0 if MACH_SUN4I
  460. default 4 if MACH_SUN5I || MACH_SUN7I
  461. ---help---
  462. Set the dram controller emr1 value.
  463. config DRAM_TPR3
  464. hex "sunxi dram tpr3 value"
  465. default 0
  466. ---help---
  467. Set the dram controller tpr3 parameter. This parameter configures
  468. the delay on the command lane and also phase shifts, which are
  469. applied for sampling incoming read data. The default value 0
  470. means that no phase/delay adjustments are necessary. Properly
  471. configuring this parameter increases reliability at high DRAM
  472. clock speeds.
  473. config DRAM_DQS_GATING_DELAY
  474. hex "sunxi dram dqs_gating_delay value"
  475. default 0
  476. ---help---
  477. Set the dram controller dqs_gating_delay parmeter. Each byte
  478. encodes the DQS gating delay for each byte lane. The delay
  479. granularity is 1/4 cycle. For example, the value 0x05060606
  480. means that the delay is 5 quarter-cycles for one lane (1.25
  481. cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
  482. The default value 0 means autodetection. The results of hardware
  483. autodetection are not very reliable and depend on the chip
  484. temperature (sometimes producing different results on cold start
  485. and warm reboot). But the accuracy of hardware autodetection
  486. is usually good enough, unless running at really high DRAM
  487. clocks speeds (up to 600MHz). If unsure, keep as 0.
  488. choice
  489. prompt "sunxi dram timings"
  490. default DRAM_TIMINGS_VENDOR_MAGIC
  491. ---help---
  492. Select the timings of the DDR3 chips.
  493. config DRAM_TIMINGS_VENDOR_MAGIC
  494. bool "Magic vendor timings from Android"
  495. ---help---
  496. The same DRAM timings as in the Allwinner boot0 bootloader.
  497. config DRAM_TIMINGS_DDR3_1066F_1333H
  498. bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
  499. ---help---
  500. Use the timings of the standard JEDEC DDR3-1066F speed bin for
  501. DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
  502. for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
  503. used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
  504. or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
  505. that down binning to DDR3-1066F is supported (because DDR3-1066F
  506. uses a bit faster timings than DDR3-1333H).
  507. config DRAM_TIMINGS_DDR3_800E_1066G_1333J
  508. bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
  509. ---help---
  510. Use the timings of the slowest possible JEDEC speed bin for the
  511. selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
  512. DDR3-800E, DDR3-1066G or DDR3-1333J.
  513. endchoice
  514. endif
  515. if MACH_SUN8I_A23
  516. config DRAM_ODT_CORRECTION
  517. int "sunxi dram odt correction value"
  518. default 0
  519. ---help---
  520. Set the dram odt correction value (range -255 - 255). In allwinner
  521. fex files, this option is found in bits 8-15 of the u32 odt_en variable
  522. in the [dram] section. When bit 31 of the odt_en variable is set
  523. then the correction is negative. Usually the value for this is 0.
  524. endif
  525. config SYS_CLK_FREQ
  526. default 1008000000 if MACH_SUN4I
  527. default 1008000000 if MACH_SUN5I
  528. default 1008000000 if MACH_SUN6I
  529. default 912000000 if MACH_SUN7I
  530. default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
  531. default 1008000000 if MACH_SUN8I
  532. default 1008000000 if MACH_SUN9I
  533. default 888000000 if MACH_SUN50I_H6
  534. default 1008000000 if MACH_SUN50I_H616
  535. config SYS_CONFIG_NAME
  536. default "sun4i" if MACH_SUN4I
  537. default "sun5i" if MACH_SUN5I
  538. default "sun6i" if MACH_SUN6I
  539. default "sun7i" if MACH_SUN7I
  540. default "sun8i" if MACH_SUN8I
  541. default "sun9i" if MACH_SUN9I
  542. default "sun50i" if MACH_SUN50I
  543. default "sun50i" if MACH_SUN50I_H6
  544. default "sun50i" if MACH_SUN50I_H616
  545. config SYS_BOARD
  546. default "sunxi"
  547. config SYS_SOC
  548. default "sunxi"
  549. config UART0_PORT_F
  550. bool "UART0 on MicroSD breakout board"
  551. ---help---
  552. Repurpose the SD card slot for getting access to the UART0 serial
  553. console. Primarily useful only for low level u-boot debugging on
  554. tablets, where normal UART0 is difficult to access and requires
  555. device disassembly and/or soldering. As the SD card can't be used
  556. at the same time, the system can be only booted in the FEL mode.
  557. Only enable this if you really know what you are doing.
  558. config OLD_SUNXI_KERNEL_COMPAT
  559. bool "Enable workarounds for booting old kernels"
  560. ---help---
  561. Set this to enable various workarounds for old kernels, this results in
  562. sub-optimal settings for newer kernels, only enable if needed.
  563. config MACPWR
  564. string "MAC power pin"
  565. default ""
  566. help
  567. Set the pin used to power the MAC. This takes a string in the format
  568. understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  569. config MMC0_CD_PIN
  570. string "Card detect pin for mmc0"
  571. default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
  572. default ""
  573. ---help---
  574. Set the card detect pin for mmc0, leave empty to not use cd. This
  575. takes a string in the format understood by sunxi_name_to_gpio, e.g.
  576. PH1 for pin 1 of port H.
  577. config MMC1_CD_PIN
  578. string "Card detect pin for mmc1"
  579. default ""
  580. ---help---
  581. See MMC0_CD_PIN help text.
  582. config MMC2_CD_PIN
  583. string "Card detect pin for mmc2"
  584. default ""
  585. ---help---
  586. See MMC0_CD_PIN help text.
  587. config MMC3_CD_PIN
  588. string "Card detect pin for mmc3"
  589. default ""
  590. ---help---
  591. See MMC0_CD_PIN help text.
  592. config MMC1_PINS
  593. string "Pins for mmc1"
  594. default ""
  595. ---help---
  596. Set the pins used for mmc1, when applicable. This takes a string in the
  597. format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
  598. config MMC2_PINS
  599. string "Pins for mmc2"
  600. default ""
  601. ---help---
  602. See MMC1_PINS help text.
  603. config MMC3_PINS
  604. string "Pins for mmc3"
  605. default ""
  606. ---help---
  607. See MMC1_PINS help text.
  608. config MMC_SUNXI_SLOT_EXTRA
  609. int "mmc extra slot number"
  610. default -1
  611. ---help---
  612. sunxi builds always enable mmc0, some boards also have a second sdcard
  613. slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
  614. support for this.
  615. config INITIAL_USB_SCAN_DELAY
  616. int "delay initial usb scan by x ms to allow builtin devices to init"
  617. default 0
  618. ---help---
  619. Some boards have on board usb devices which need longer than the
  620. USB spec's 1 second to connect from board powerup. Set this config
  621. option to a non 0 value to add an extra delay before the first usb
  622. bus scan.
  623. config USB0_VBUS_PIN
  624. string "Vbus enable pin for usb0 (otg)"
  625. default ""
  626. ---help---
  627. Set the Vbus enable pin for usb0 (otg). This takes a string in the
  628. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  629. config USB0_VBUS_DET
  630. string "Vbus detect pin for usb0 (otg)"
  631. default ""
  632. ---help---
  633. Set the Vbus detect pin for usb0 (otg). This takes a string in the
  634. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  635. config USB0_ID_DET
  636. string "ID detect pin for usb0 (otg)"
  637. default ""
  638. ---help---
  639. Set the ID detect pin for usb0 (otg). This takes a string in the
  640. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  641. config USB1_VBUS_PIN
  642. string "Vbus enable pin for usb1 (ehci0)"
  643. default "PH6" if MACH_SUN4I || MACH_SUN7I
  644. default "PH27" if MACH_SUN6I
  645. ---help---
  646. Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
  647. a string in the format understood by sunxi_name_to_gpio, e.g.
  648. PH1 for pin 1 of port H.
  649. config USB2_VBUS_PIN
  650. string "Vbus enable pin for usb2 (ehci1)"
  651. default "PH3" if MACH_SUN4I || MACH_SUN7I
  652. default "PH24" if MACH_SUN6I
  653. ---help---
  654. See USB1_VBUS_PIN help text.
  655. config USB3_VBUS_PIN
  656. string "Vbus enable pin for usb3 (ehci2)"
  657. default ""
  658. ---help---
  659. See USB1_VBUS_PIN help text.
  660. config I2C0_ENABLE
  661. bool "Enable I2C/TWI controller 0"
  662. default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
  663. default n if MACH_SUN6I || MACH_SUN8I
  664. select CMD_I2C
  665. ---help---
  666. This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
  667. its clock and setting up the bus. This is especially useful on devices
  668. with slaves connected to the bus or with pins exposed through e.g. an
  669. expansion port/header.
  670. config I2C1_ENABLE
  671. bool "Enable I2C/TWI controller 1"
  672. select CMD_I2C
  673. ---help---
  674. See I2C0_ENABLE help text.
  675. config I2C2_ENABLE
  676. bool "Enable I2C/TWI controller 2"
  677. select CMD_I2C
  678. ---help---
  679. See I2C0_ENABLE help text.
  680. if MACH_SUN6I || MACH_SUN7I
  681. config I2C3_ENABLE
  682. bool "Enable I2C/TWI controller 3"
  683. select CMD_I2C
  684. ---help---
  685. See I2C0_ENABLE help text.
  686. endif
  687. if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
  688. config R_I2C_ENABLE
  689. bool "Enable the PRCM I2C/TWI controller"
  690. # This is used for the pmic on H3
  691. default y if SY8106A_POWER
  692. select CMD_I2C
  693. ---help---
  694. Set this to y to enable the I2C controller which is part of the PRCM.
  695. endif
  696. if MACH_SUN7I
  697. config I2C4_ENABLE
  698. bool "Enable I2C/TWI controller 4"
  699. select CMD_I2C
  700. ---help---
  701. See I2C0_ENABLE help text.
  702. endif
  703. config AXP_GPIO
  704. bool "Enable support for gpio-s on axp PMICs"
  705. ---help---
  706. Say Y here to enable support for the gpio pins of the axp PMIC ICs.
  707. config VIDEO_SUNXI
  708. bool "Enable graphical uboot console on HDMI, LCD or VGA"
  709. depends on !MACH_SUN8I_A83T
  710. depends on !MACH_SUNXI_H3_H5
  711. depends on !MACH_SUN8I_R40
  712. depends on !MACH_SUN8I_V3S
  713. depends on !MACH_SUN9I
  714. depends on !MACH_SUN50I
  715. depends on !SUN50I_GEN_H6
  716. select DM_VIDEO
  717. select DISPLAY
  718. imply VIDEO_DT_SIMPLEFB
  719. default y
  720. ---help---
  721. Say Y here to add support for using a graphical console on the HDMI,
  722. LCD or VGA output found on older sunxi devices. This will also provide
  723. a simple_framebuffer device for Linux.
  724. config VIDEO_HDMI
  725. bool "HDMI output support"
  726. depends on VIDEO_SUNXI && !MACH_SUN8I
  727. default y
  728. ---help---
  729. Say Y here to add support for outputting video over HDMI.
  730. config VIDEO_VGA
  731. bool "VGA output support"
  732. depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
  733. ---help---
  734. Say Y here to add support for outputting video over VGA.
  735. config VIDEO_VGA_VIA_LCD
  736. bool "VGA via LCD controller support"
  737. depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
  738. ---help---
  739. Say Y here to add support for external DACs connected to the parallel
  740. LCD interface driving a VGA connector, such as found on the
  741. Olimex A13 boards.
  742. config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
  743. bool "Force sync active high for VGA via LCD controller support"
  744. depends on VIDEO_VGA_VIA_LCD
  745. ---help---
  746. Say Y here if you've a board which uses opendrain drivers for the vga
  747. hsync and vsync signals. Opendrain drivers cannot generate steep enough
  748. positive edges for a stable video output, so on boards with opendrain
  749. drivers the sync signals must always be active high.
  750. config VIDEO_VGA_EXTERNAL_DAC_EN
  751. string "LCD panel power enable pin"
  752. depends on VIDEO_VGA_VIA_LCD
  753. default ""
  754. ---help---
  755. Set the enable pin for the external VGA DAC. This takes a string in the
  756. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  757. config VIDEO_COMPOSITE
  758. bool "Composite video output support"
  759. depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
  760. ---help---
  761. Say Y here to add support for outputting composite video.
  762. config VIDEO_LCD_MODE
  763. string "LCD panel timing details"
  764. depends on VIDEO_SUNXI
  765. default ""
  766. ---help---
  767. LCD panel timing details string, leave empty if there is no LCD panel.
  768. This is in drivers/video/videomodes.c: video_get_params() format, e.g.
  769. x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
  770. Also see: http://linux-sunxi.org/LCD
  771. config VIDEO_LCD_DCLK_PHASE
  772. int "LCD panel display clock phase"
  773. depends on VIDEO_SUNXI || DM_VIDEO
  774. default 1
  775. ---help---
  776. Select LCD panel display clock phase shift, range 0-3.
  777. config VIDEO_LCD_POWER
  778. string "LCD panel power enable pin"
  779. depends on VIDEO_SUNXI
  780. default ""
  781. ---help---
  782. Set the power enable pin for the LCD panel. This takes a string in the
  783. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  784. config VIDEO_LCD_RESET
  785. string "LCD panel reset pin"
  786. depends on VIDEO_SUNXI
  787. default ""
  788. ---help---
  789. Set the reset pin for the LCD panel. This takes a string in the format
  790. understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  791. config VIDEO_LCD_BL_EN
  792. string "LCD panel backlight enable pin"
  793. depends on VIDEO_SUNXI
  794. default ""
  795. ---help---
  796. Set the backlight enable pin for the LCD panel. This takes a string in the
  797. the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
  798. port H.
  799. config VIDEO_LCD_BL_PWM
  800. string "LCD panel backlight pwm pin"
  801. depends on VIDEO_SUNXI
  802. default ""
  803. ---help---
  804. Set the backlight pwm pin for the LCD panel. This takes a string in the
  805. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  806. config VIDEO_LCD_BL_PWM_ACTIVE_LOW
  807. bool "LCD panel backlight pwm is inverted"
  808. depends on VIDEO_SUNXI
  809. default y
  810. ---help---
  811. Set this if the backlight pwm output is active low.
  812. config VIDEO_LCD_PANEL_I2C
  813. bool "LCD panel needs to be configured via i2c"
  814. depends on VIDEO_SUNXI
  815. select CMD_I2C
  816. ---help---
  817. Say y here if the LCD panel needs to be configured via i2c. This
  818. will add a bitbang i2c controller using gpios to talk to the LCD.
  819. config VIDEO_LCD_PANEL_I2C_SDA
  820. string "LCD panel i2c interface SDA pin"
  821. depends on VIDEO_LCD_PANEL_I2C
  822. default "PG12"
  823. ---help---
  824. Set the SDA pin for the LCD i2c interface. This takes a string in the
  825. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  826. config VIDEO_LCD_PANEL_I2C_SCL
  827. string "LCD panel i2c interface SCL pin"
  828. depends on VIDEO_LCD_PANEL_I2C
  829. default "PG10"
  830. ---help---
  831. Set the SCL pin for the LCD i2c interface. This takes a string in the
  832. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
  833. # Note only one of these may be selected at a time! But hidden choices are
  834. # not supported by Kconfig
  835. config VIDEO_LCD_IF_PARALLEL
  836. bool
  837. config VIDEO_LCD_IF_LVDS
  838. bool
  839. config SUNXI_DE2
  840. bool
  841. config VIDEO_DE2
  842. bool "Display Engine 2 video driver"
  843. depends on SUNXI_DE2
  844. select DM_VIDEO
  845. select DISPLAY
  846. select VIDEO_DW_HDMI
  847. imply VIDEO_DT_SIMPLEFB
  848. default y
  849. ---help---
  850. Say y here if you want to build DE2 video driver which is present on
  851. newer SoCs. Currently only HDMI output is supported.
  852. choice
  853. prompt "LCD panel support"
  854. depends on VIDEO_SUNXI
  855. ---help---
  856. Select which type of LCD panel to support.
  857. config VIDEO_LCD_PANEL_PARALLEL
  858. bool "Generic parallel interface LCD panel"
  859. select VIDEO_LCD_IF_PARALLEL
  860. config VIDEO_LCD_PANEL_LVDS
  861. bool "Generic lvds interface LCD panel"
  862. select VIDEO_LCD_IF_LVDS
  863. config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
  864. bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
  865. select VIDEO_LCD_SSD2828
  866. select VIDEO_LCD_IF_PARALLEL
  867. ---help---
  868. 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
  869. config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
  870. bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
  871. select VIDEO_LCD_ANX9804
  872. select VIDEO_LCD_IF_PARALLEL
  873. select VIDEO_LCD_PANEL_I2C
  874. ---help---
  875. Select this for eDP LCD panels with 4 lanes running at 1.62G,
  876. connected via an ANX9804 bridge chip.
  877. config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
  878. bool "Hitachi tx18d42vm LCD panel"
  879. select VIDEO_LCD_HITACHI_TX18D42VM
  880. select VIDEO_LCD_IF_LVDS
  881. ---help---
  882. 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
  883. config VIDEO_LCD_TL059WV5C0
  884. bool "tl059wv5c0 LCD panel"
  885. select VIDEO_LCD_PANEL_I2C
  886. select VIDEO_LCD_IF_PARALLEL
  887. ---help---
  888. 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
  889. Aigo M60/M608/M606 tablets.
  890. endchoice
  891. config SATAPWR
  892. string "SATA power pin"
  893. default ""
  894. help
  895. Set the pins used to power the SATA. This takes a string in the
  896. format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
  897. port H.
  898. config GMAC_TX_DELAY
  899. int "GMAC Transmit Clock Delay Chain"
  900. default 0
  901. ---help---
  902. Set the GMAC Transmit Clock Delay Chain value.
  903. config SPL_STACK_R_ADDR
  904. default 0x4fe00000 if MACH_SUN4I
  905. default 0x4fe00000 if MACH_SUN5I
  906. default 0x4fe00000 if MACH_SUN6I
  907. default 0x4fe00000 if MACH_SUN7I
  908. default 0x4fe00000 if MACH_SUN8I
  909. default 0x2fe00000 if MACH_SUN9I
  910. default 0x4fe00000 if MACH_SUN50I
  911. default 0x4fe00000 if SUN50I_GEN_H6
  912. config SPL_SPI_SUNXI
  913. bool "Support for SPI Flash on Allwinner SoCs in SPL"
  914. depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
  915. help
  916. Enable support for SPI Flash. This option allows SPL to read from
  917. sunxi SPI Flash. It uses the same method as the boot ROM, so does
  918. not need any extra configuration.
  919. config PINE64_DT_SELECTION
  920. bool "Enable Pine64 device tree selection code"
  921. depends on MACH_SUN50I
  922. help
  923. The original Pine A64 and Pine A64+ are similar but different
  924. boards and can be differed by the DRAM size. Pine A64 has
  925. 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
  926. option, the device tree selection code specific to Pine64 which
  927. utilizes the DRAM size will be enabled.
  928. config PINEPHONE_DT_SELECTION
  929. bool "Enable PinePhone device tree selection code"
  930. depends on MACH_SUN50I
  931. help
  932. Enable this option to automatically select the device tree for the
  933. correct PinePhone hardware revision during boot.
  934. config BLUETOOTH_DT_DEVICE_FIXUP
  935. string "Fixup the Bluetooth controller address"
  936. default ""
  937. help
  938. This option specifies the DT compatible name of the Bluetooth
  939. controller for which to set the "local-bd-address" property.
  940. Set this option if your device ships with the Bluetooth controller
  941. default address.
  942. The used address is "bdaddr" if set, and "ethaddr" with the LSB
  943. flipped elsewise.
  944. endif
  945. config CHIP_DIP_SCAN
  946. bool "Enable DIPs detection for CHIP board"
  947. select SUPPORT_EXTENSION_SCAN
  948. select W1
  949. select W1_GPIO
  950. select W1_EEPROM
  951. select W1_EEPROM_DS24XXX
  952. select CMD_EXTENSION