lowlevel_init.S 4.3 KB

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  1. /*
  2. * Copyright (C) 2012-2014 Panasonic Corporation
  3. * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <config.h>
  8. #include <linux/linkage.h>
  9. #include <asm/system.h>
  10. #include <asm/arch/led.h>
  11. #include <asm/arch/arm-mpcore.h>
  12. #include <asm/arch/sbc-regs.h>
  13. ENTRY(lowlevel_init)
  14. mov r8, lr @ persevere link reg across call
  15. /*
  16. * The UniPhier Boot ROM loads SPL code to the L2 cache.
  17. * But CPUs can only do instruction fetch now because start.S has
  18. * cleared C and M bits.
  19. * First we need to turn on MMU and Dcache again to get back
  20. * data access to L2.
  21. */
  22. mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
  23. orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
  24. mcr p15, 0, r0, c1, c0, 0
  25. #ifdef CONFIG_DEBUG_LL
  26. bl setup_lowlevel_debug
  27. #endif
  28. /*
  29. * Now we are using the page table embedded in the Boot ROM.
  30. * It is not handy since it is not a straight mapped table for sLD3.
  31. * What we need to do next is to switch over to the page table in SPL.
  32. */
  33. ldr r3, =init_page_table @ page table must be 16KB aligned
  34. /* Disable MMU and Dcache before switching Page Table */
  35. mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
  36. bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
  37. mcr p15, 0, r0, c1, c0, 0
  38. bl enable_mmu
  39. #ifdef CONFIG_UNIPHIER_SMP
  40. /*
  41. * ACTLR (Auxiliary Control Register) for Cortex-A9
  42. * bit[9] Parity on
  43. * bit[8] Alloc in one way
  44. * bit[7] EXCL (Exclusive cache bit)
  45. * bit[6] SMP
  46. * bit[3] Write full line of zeros mode
  47. * bit[2] L1 Prefetch enable
  48. * bit[1] L2 prefetch enable
  49. * bit[0] FW (Cache and TLB maintenance broadcast)
  50. */
  51. mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
  52. orr r0, r0, #0x41 @ enable SMP, FW bit
  53. mcr p15, 0, r0, c1, c0, 1
  54. /* branch by CPU ID */
  55. mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
  56. and r0, r0, #0x3
  57. cmp r0, #0x0
  58. beq primary_cpu
  59. ldr r1, =ROM_BOOT_ROMRSV2
  60. mov r0, #0
  61. str r0, [r1]
  62. 0: wfe
  63. ldr r0, [r1]
  64. cmp r0, #0
  65. beq 0b
  66. bx r0 @ r0: entry point of U-Boot main for the secondary CPU
  67. primary_cpu:
  68. ldr r1, =ROM_BOOT_ROMRSV2
  69. ldr r0, =_start @ entry for the secondary CPU
  70. str r0, [r1]
  71. ldr r0, [r1] @ make sure str is complete before sev
  72. sev @ kick the sedoncary CPU
  73. mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
  74. bfc r1, #0, #13 @ clear bit 12-0
  75. mov r0, #-1
  76. str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
  77. mov r0, #1 @ SCU enable
  78. str r0, [r1, #SCU_CTRL] @ SCU Control Register
  79. #endif
  80. bl setup_init_ram @ RAM area for temporary stack pointer
  81. mov lr, r8 @ restore link
  82. mov pc, lr @ back to my caller
  83. ENDPROC(lowlevel_init)
  84. ENTRY(enable_mmu)
  85. mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
  86. bic r0, r0, #0x37
  87. orr r0, r0, #0x20 @ disable TTBR1
  88. mcr p15, 0, r0, c2, c0, 2
  89. orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
  90. mcr p15, 0, r0, c2, c0, 0 @ TTBR0
  91. mov r0, #0
  92. mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
  93. mov r0, #-1 @ manager for all domains (No permission check)
  94. mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
  95. dsb
  96. isb
  97. /*
  98. * MMU on:
  99. * TLBs was already invalidated in "../start.S"
  100. * So, we don't need to invalidate it here.
  101. */
  102. mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
  103. orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
  104. mcr p15, 0, r0, c1, c0, 0
  105. mov pc, lr
  106. ENDPROC(enable_mmu)
  107. #include <asm/arch/ssc-regs.h>
  108. #define BOOT_RAM_SIZE (SSC_WAY_SIZE)
  109. #define BOOT_WAY_BITS (0x00000100) /* way 8 */
  110. ENTRY(setup_init_ram)
  111. /*
  112. * Touch to zero for the boot way
  113. */
  114. 0:
  115. /*
  116. * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
  117. */
  118. ldr r0, = 0x00408006 @ touch to zero with address range
  119. ldr r1, = SSCOQM
  120. str r0, [r1]
  121. ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
  122. ldr r1, = SSCOQAD
  123. str r0, [r1]
  124. ldr r0, = BOOT_RAM_SIZE
  125. ldr r1, = SSCOQSZ
  126. str r0, [r1]
  127. ldr r0, = BOOT_WAY_BITS
  128. ldr r1, = SSCOQWN
  129. str r0, [r1]
  130. ldr r1, = SSCOPPQSEF
  131. ldr r0, [r1]
  132. cmp r0, #0 @ check if the command is successfully set
  133. bne 0b @ try again if an error occurres
  134. ldr r1, = SSCOLPQS
  135. 1:
  136. ldr r0, [r1]
  137. cmp r0, #0x4
  138. bne 1b @ wait until the operation is completed
  139. str r0, [r1] @ clear the complete notification flag
  140. mov pc, lr
  141. ENDPROC(setup_init_ram)