ci_udc.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #include <common.h>
  10. #include <command.h>
  11. #include <config.h>
  12. #include <cpu_func.h>
  13. #include <net.h>
  14. #include <malloc.h>
  15. #include <asm/byteorder.h>
  16. #include <asm/cache.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <asm/io.h>
  20. #include <asm/unaligned.h>
  21. #include <linux/types.h>
  22. #include <linux/usb/ch9.h>
  23. #include <linux/usb/gadget.h>
  24. #include <usb/ci_udc.h>
  25. #include "../host/ehci.h"
  26. #include "ci_udc.h"
  27. /*
  28. * Check if the system has too long cachelines. If the cachelines are
  29. * longer then 128b, the driver will not be able flush/invalidate data
  30. * cache over separate QH entries. We use 128b because one QH entry is
  31. * 64b long and there are always two QH list entries for each endpoint.
  32. */
  33. #if ARCH_DMA_MINALIGN > 128
  34. #error This driver can not work on systems with caches longer than 128b
  35. #endif
  36. /*
  37. * Every QTD must be individually aligned, since we can program any
  38. * QTD's address into HW. Cache flushing requires ARCH_DMA_MINALIGN,
  39. * and the USB HW requires 32-byte alignment. Align to both:
  40. */
  41. #define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32)
  42. /* Each QTD is this size */
  43. #define ILIST_ENT_RAW_SZ sizeof(struct ept_queue_item)
  44. /*
  45. * Align the size of the QTD too, so we can add this value to each
  46. * QTD's address to get another aligned address.
  47. */
  48. #define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ILIST_ALIGN)
  49. /* For each endpoint, we need 2 QTDs, one for each of IN and OUT */
  50. #define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ)
  51. #define EP_MAX_LENGTH_TRANSFER 0x4000
  52. #ifndef DEBUG
  53. #define DBG(x...) do {} while (0)
  54. #else
  55. #define DBG(x...) printf(x)
  56. static const char *reqname(unsigned r)
  57. {
  58. switch (r) {
  59. case USB_REQ_GET_STATUS: return "GET_STATUS";
  60. case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
  61. case USB_REQ_SET_FEATURE: return "SET_FEATURE";
  62. case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
  63. case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
  64. case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
  65. case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
  66. case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
  67. case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
  68. case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
  69. default: return "*UNKNOWN*";
  70. }
  71. }
  72. #endif
  73. static struct usb_endpoint_descriptor ep0_desc = {
  74. .bLength = sizeof(struct usb_endpoint_descriptor),
  75. .bDescriptorType = USB_DT_ENDPOINT,
  76. .bEndpointAddress = USB_DIR_IN,
  77. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  78. };
  79. static int ci_pullup(struct usb_gadget *gadget, int is_on);
  80. static int ci_ep_enable(struct usb_ep *ep,
  81. const struct usb_endpoint_descriptor *desc);
  82. static int ci_ep_disable(struct usb_ep *ep);
  83. static int ci_ep_queue(struct usb_ep *ep,
  84. struct usb_request *req, gfp_t gfp_flags);
  85. static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req);
  86. static struct usb_request *
  87. ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
  88. static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
  89. static struct usb_gadget_ops ci_udc_ops = {
  90. .pullup = ci_pullup,
  91. };
  92. static struct usb_ep_ops ci_ep_ops = {
  93. .enable = ci_ep_enable,
  94. .disable = ci_ep_disable,
  95. .queue = ci_ep_queue,
  96. .dequeue = ci_ep_dequeue,
  97. .alloc_request = ci_ep_alloc_request,
  98. .free_request = ci_ep_free_request,
  99. };
  100. __weak void ci_init_after_reset(struct ehci_ctrl *ctrl)
  101. {
  102. }
  103. /* Init values for USB endpoints. */
  104. static const struct usb_ep ci_ep_init[5] = {
  105. [0] = { /* EP 0 */
  106. .maxpacket = 64,
  107. .name = "ep0",
  108. .ops = &ci_ep_ops,
  109. },
  110. [1] = {
  111. .maxpacket = 512,
  112. .name = "ep1in-bulk",
  113. .ops = &ci_ep_ops,
  114. },
  115. [2] = {
  116. .maxpacket = 512,
  117. .name = "ep2out-bulk",
  118. .ops = &ci_ep_ops,
  119. },
  120. [3] = {
  121. .maxpacket = 512,
  122. .name = "ep3in-int",
  123. .ops = &ci_ep_ops,
  124. },
  125. [4] = {
  126. .maxpacket = 512,
  127. .name = "ep-",
  128. .ops = &ci_ep_ops,
  129. },
  130. };
  131. static struct ci_drv controller = {
  132. .gadget = {
  133. .name = "ci_udc",
  134. .ops = &ci_udc_ops,
  135. .is_dualspeed = 1,
  136. .max_speed = USB_SPEED_HIGH,
  137. },
  138. };
  139. /**
  140. * ci_get_qh() - return queue head for endpoint
  141. * @ep_num: Endpoint number
  142. * @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
  143. *
  144. * This function returns the QH associated with particular endpoint
  145. * and it's direction.
  146. */
  147. static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in)
  148. {
  149. return &controller.epts[(ep_num * 2) + dir_in];
  150. }
  151. /**
  152. * ci_get_qtd() - return queue item for endpoint
  153. * @ep_num: Endpoint number
  154. * @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
  155. *
  156. * This function returns the QH associated with particular endpoint
  157. * and it's direction.
  158. */
  159. static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in)
  160. {
  161. int index = (ep_num * 2) + dir_in;
  162. uint8_t *imem = controller.items_mem + (index * ILIST_ENT_SZ);
  163. return (struct ept_queue_item *)imem;
  164. }
  165. /**
  166. * ci_flush_qh - flush cache over queue head
  167. * @ep_num: Endpoint number
  168. *
  169. * This function flushes cache over QH for particular endpoint.
  170. */
  171. static void ci_flush_qh(int ep_num)
  172. {
  173. struct ept_queue_head *head = ci_get_qh(ep_num, 0);
  174. const unsigned long start = (unsigned long)head;
  175. const unsigned long end = start + 2 * sizeof(*head);
  176. flush_dcache_range(start, end);
  177. }
  178. /**
  179. * ci_invalidate_qh - invalidate cache over queue head
  180. * @ep_num: Endpoint number
  181. *
  182. * This function invalidates cache over QH for particular endpoint.
  183. */
  184. static void ci_invalidate_qh(int ep_num)
  185. {
  186. struct ept_queue_head *head = ci_get_qh(ep_num, 0);
  187. unsigned long start = (unsigned long)head;
  188. unsigned long end = start + 2 * sizeof(*head);
  189. invalidate_dcache_range(start, end);
  190. }
  191. /**
  192. * ci_flush_qtd - flush cache over queue item
  193. * @ep_num: Endpoint number
  194. *
  195. * This function flushes cache over qTD pair for particular endpoint.
  196. */
  197. static void ci_flush_qtd(int ep_num)
  198. {
  199. struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
  200. const unsigned long start = (unsigned long)item;
  201. const unsigned long end = start + 2 * ILIST_ENT_SZ;
  202. flush_dcache_range(start, end);
  203. }
  204. /**
  205. * ci_flush_td - flush cache over queue item
  206. * @td: td pointer
  207. *
  208. * This function flushes cache for particular transfer descriptor.
  209. */
  210. static void ci_flush_td(struct ept_queue_item *td)
  211. {
  212. const unsigned long start = (unsigned long)td;
  213. const unsigned long end = (unsigned long)td + ILIST_ENT_SZ;
  214. flush_dcache_range(start, end);
  215. }
  216. /**
  217. * ci_invalidate_qtd - invalidate cache over queue item
  218. * @ep_num: Endpoint number
  219. *
  220. * This function invalidates cache over qTD pair for particular endpoint.
  221. */
  222. static void ci_invalidate_qtd(int ep_num)
  223. {
  224. struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
  225. const unsigned long start = (unsigned long)item;
  226. const unsigned long end = start + 2 * ILIST_ENT_SZ;
  227. invalidate_dcache_range(start, end);
  228. }
  229. /**
  230. * ci_invalidate_td - invalidate cache over queue item
  231. * @td: td pointer
  232. *
  233. * This function invalidates cache for particular transfer descriptor.
  234. */
  235. static void ci_invalidate_td(struct ept_queue_item *td)
  236. {
  237. const unsigned long start = (unsigned long)td;
  238. const unsigned long end = start + ILIST_ENT_SZ;
  239. invalidate_dcache_range(start, end);
  240. }
  241. static struct usb_request *
  242. ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
  243. {
  244. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  245. int num = -1;
  246. struct ci_req *ci_req;
  247. if (ci_ep->desc)
  248. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  249. if (num == 0 && controller.ep0_req)
  250. return &controller.ep0_req->req;
  251. ci_req = calloc(1, sizeof(*ci_req));
  252. if (!ci_req)
  253. return NULL;
  254. INIT_LIST_HEAD(&ci_req->queue);
  255. if (num == 0)
  256. controller.ep0_req = ci_req;
  257. return &ci_req->req;
  258. }
  259. static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req)
  260. {
  261. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  262. struct ci_req *ci_req = container_of(req, struct ci_req, req);
  263. int num = -1;
  264. if (ci_ep->desc)
  265. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  266. if (num == 0) {
  267. if (!controller.ep0_req)
  268. return;
  269. controller.ep0_req = 0;
  270. }
  271. if (ci_req->b_buf)
  272. free(ci_req->b_buf);
  273. free(ci_req);
  274. }
  275. static void ep_enable(int num, int in, int maxpacket)
  276. {
  277. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  278. unsigned n;
  279. n = readl(&udc->epctrl[num]);
  280. if (in)
  281. n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
  282. else
  283. n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
  284. if (num != 0) {
  285. struct ept_queue_head *head = ci_get_qh(num, in);
  286. head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
  287. ci_flush_qh(num);
  288. }
  289. writel(n, &udc->epctrl[num]);
  290. }
  291. static int ci_ep_enable(struct usb_ep *ep,
  292. const struct usb_endpoint_descriptor *desc)
  293. {
  294. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  295. int num, in;
  296. num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  297. in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
  298. ci_ep->desc = desc;
  299. ep->desc = desc;
  300. if (num) {
  301. int max = get_unaligned_le16(&desc->wMaxPacketSize);
  302. if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL))
  303. max = 64;
  304. if (ep->maxpacket != max) {
  305. DBG("%s: from %d to %d\n", __func__,
  306. ep->maxpacket, max);
  307. ep->maxpacket = max;
  308. }
  309. }
  310. ep_enable(num, in, ep->maxpacket);
  311. DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket);
  312. return 0;
  313. }
  314. static int ci_ep_disable(struct usb_ep *ep)
  315. {
  316. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  317. ci_ep->desc = NULL;
  318. ep->desc = NULL;
  319. return 0;
  320. }
  321. static int ci_bounce(struct ci_req *ci_req, int in)
  322. {
  323. struct usb_request *req = &ci_req->req;
  324. unsigned long addr = (unsigned long)req->buf;
  325. unsigned long hwaddr;
  326. uint32_t aligned_used_len;
  327. /* Input buffer address is not aligned. */
  328. if (addr & (ARCH_DMA_MINALIGN - 1))
  329. goto align;
  330. /* Input buffer length is not aligned. */
  331. if (req->length & (ARCH_DMA_MINALIGN - 1))
  332. goto align;
  333. /* The buffer is well aligned, only flush cache. */
  334. ci_req->hw_len = req->length;
  335. ci_req->hw_buf = req->buf;
  336. goto flush;
  337. align:
  338. if (ci_req->b_buf && req->length > ci_req->b_len) {
  339. free(ci_req->b_buf);
  340. ci_req->b_buf = 0;
  341. }
  342. if (!ci_req->b_buf) {
  343. ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN);
  344. ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len);
  345. if (!ci_req->b_buf)
  346. return -ENOMEM;
  347. }
  348. ci_req->hw_len = ci_req->b_len;
  349. ci_req->hw_buf = ci_req->b_buf;
  350. if (in)
  351. memcpy(ci_req->hw_buf, req->buf, req->length);
  352. flush:
  353. hwaddr = (unsigned long)ci_req->hw_buf;
  354. aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN);
  355. flush_dcache_range(hwaddr, hwaddr + aligned_used_len);
  356. return 0;
  357. }
  358. static void ci_debounce(struct ci_req *ci_req, int in)
  359. {
  360. struct usb_request *req = &ci_req->req;
  361. unsigned long addr = (unsigned long)req->buf;
  362. unsigned long hwaddr = (unsigned long)ci_req->hw_buf;
  363. uint32_t aligned_used_len;
  364. if (in)
  365. return;
  366. aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN);
  367. invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len);
  368. if (addr == hwaddr)
  369. return; /* not a bounce */
  370. memcpy(req->buf, ci_req->hw_buf, req->actual);
  371. }
  372. static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
  373. {
  374. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  375. struct ept_queue_item *item;
  376. struct ept_queue_head *head;
  377. int bit, num, len, in;
  378. struct ci_req *ci_req;
  379. u8 *buf;
  380. uint32_t len_left, len_this_dtd;
  381. struct ept_queue_item *dtd, *qtd;
  382. ci_ep->req_primed = true;
  383. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  384. in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
  385. item = ci_get_qtd(num, in);
  386. head = ci_get_qh(num, in);
  387. ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
  388. len = ci_req->req.length;
  389. head->next = (unsigned long)item;
  390. head->info = 0;
  391. ci_req->dtd_count = 0;
  392. buf = ci_req->hw_buf;
  393. len_left = len;
  394. dtd = item;
  395. do {
  396. len_this_dtd = min(len_left, (unsigned)EP_MAX_LENGTH_TRANSFER);
  397. dtd->info = INFO_BYTES(len_this_dtd) | INFO_ACTIVE;
  398. dtd->page0 = (unsigned long)buf;
  399. dtd->page1 = ((unsigned long)buf & 0xfffff000) + 0x1000;
  400. dtd->page2 = ((unsigned long)buf & 0xfffff000) + 0x2000;
  401. dtd->page3 = ((unsigned long)buf & 0xfffff000) + 0x3000;
  402. dtd->page4 = ((unsigned long)buf & 0xfffff000) + 0x4000;
  403. len_left -= len_this_dtd;
  404. buf += len_this_dtd;
  405. if (len_left) {
  406. qtd = (struct ept_queue_item *)
  407. memalign(ILIST_ALIGN, ILIST_ENT_SZ);
  408. dtd->next = (unsigned long)qtd;
  409. dtd = qtd;
  410. memset(dtd, 0, ILIST_ENT_SZ);
  411. }
  412. ci_req->dtd_count++;
  413. } while (len_left);
  414. item = dtd;
  415. /*
  416. * When sending the data for an IN transaction, the attached host
  417. * knows that all data for the IN is sent when one of the following
  418. * occurs:
  419. * a) A zero-length packet is transmitted.
  420. * b) A packet with length that isn't an exact multiple of the ep's
  421. * maxpacket is transmitted.
  422. * c) Enough data is sent to exactly fill the host's maximum expected
  423. * IN transaction size.
  424. *
  425. * One of these conditions MUST apply at the end of an IN transaction,
  426. * or the transaction will not be considered complete by the host. If
  427. * none of (a)..(c) already applies, then we must force (a) to apply
  428. * by explicitly sending an extra zero-length packet.
  429. */
  430. /* IN !a !b !c */
  431. if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) {
  432. /*
  433. * Each endpoint has 2 items allocated, even though typically
  434. * only 1 is used at a time since either an IN or an OUT but
  435. * not both is queued. For an IN transaction, item currently
  436. * points at the second of these items, so we know that we
  437. * can use the other to transmit the extra zero-length packet.
  438. */
  439. struct ept_queue_item *other_item = ci_get_qtd(num, 0);
  440. item->next = (unsigned long)other_item;
  441. item = other_item;
  442. item->info = INFO_ACTIVE;
  443. }
  444. item->next = TERMINATE;
  445. item->info |= INFO_IOC;
  446. ci_flush_qtd(num);
  447. item = (struct ept_queue_item *)(unsigned long)head->next;
  448. while (item->next != TERMINATE) {
  449. ci_flush_td((struct ept_queue_item *)(unsigned long)item->next);
  450. item = (struct ept_queue_item *)(unsigned long)item->next;
  451. }
  452. DBG("ept%d %s queue len %x, req %p, buffer %p\n",
  453. num, in ? "in" : "out", len, ci_req, ci_req->hw_buf);
  454. ci_flush_qh(num);
  455. if (in)
  456. bit = EPT_TX(num);
  457. else
  458. bit = EPT_RX(num);
  459. writel(bit, &udc->epprime);
  460. }
  461. static int ci_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  462. {
  463. struct ci_ep *ci_ep = container_of(_ep, struct ci_ep, ep);
  464. struct ci_req *ci_req;
  465. list_for_each_entry(ci_req, &ci_ep->queue, queue) {
  466. if (&ci_req->req == _req)
  467. break;
  468. }
  469. if (&ci_req->req != _req)
  470. return -EINVAL;
  471. list_del_init(&ci_req->queue);
  472. if (ci_req->req.status == -EINPROGRESS) {
  473. ci_req->req.status = -ECONNRESET;
  474. if (ci_req->req.complete)
  475. ci_req->req.complete(_ep, _req);
  476. }
  477. return 0;
  478. }
  479. static int ci_ep_queue(struct usb_ep *ep,
  480. struct usb_request *req, gfp_t gfp_flags)
  481. {
  482. struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
  483. struct ci_req *ci_req = container_of(req, struct ci_req, req);
  484. int in, ret;
  485. int __maybe_unused num;
  486. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  487. in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
  488. if (!num && ci_ep->req_primed) {
  489. /*
  490. * The flipping of ep0 between IN and OUT relies on
  491. * ci_ep_queue consuming the current IN/OUT setting
  492. * immediately. If this is deferred to a later point when the
  493. * req is pulled out of ci_req->queue, then the IN/OUT setting
  494. * may have been changed since the req was queued, and state
  495. * will get out of sync. This condition doesn't occur today,
  496. * but could if bugs were introduced later, and this error
  497. * check will save a lot of debugging time.
  498. */
  499. printf("%s: ep0 transaction already in progress\n", __func__);
  500. return -EPROTO;
  501. }
  502. ret = ci_bounce(ci_req, in);
  503. if (ret)
  504. return ret;
  505. DBG("ept%d %s pre-queue req %p, buffer %p\n",
  506. num, in ? "in" : "out", ci_req, ci_req->hw_buf);
  507. list_add_tail(&ci_req->queue, &ci_ep->queue);
  508. if (!ci_ep->req_primed)
  509. ci_ep_submit_next_request(ci_ep);
  510. return 0;
  511. }
  512. static void flip_ep0_direction(void)
  513. {
  514. if (ep0_desc.bEndpointAddress == USB_DIR_IN) {
  515. DBG("%s: Flipping ep0 to OUT\n", __func__);
  516. ep0_desc.bEndpointAddress = 0;
  517. } else {
  518. DBG("%s: Flipping ep0 to IN\n", __func__);
  519. ep0_desc.bEndpointAddress = USB_DIR_IN;
  520. }
  521. }
  522. static void handle_ep_complete(struct ci_ep *ci_ep)
  523. {
  524. struct ept_queue_item *item, *next_td;
  525. int num, in, len, j;
  526. struct ci_req *ci_req;
  527. num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  528. in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
  529. item = ci_get_qtd(num, in);
  530. ci_invalidate_qtd(num);
  531. ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
  532. next_td = item;
  533. len = 0;
  534. for (j = 0; j < ci_req->dtd_count; j++) {
  535. ci_invalidate_td(next_td);
  536. item = next_td;
  537. len += (item->info >> 16) & 0x7fff;
  538. if (item->info & 0xff)
  539. printf("EP%d/%s FAIL info=%x pg0=%x\n",
  540. num, in ? "in" : "out", item->info, item->page0);
  541. if (j != ci_req->dtd_count - 1)
  542. next_td = (struct ept_queue_item *)(unsigned long)
  543. item->next;
  544. if (j != 0)
  545. free(item);
  546. }
  547. list_del_init(&ci_req->queue);
  548. ci_ep->req_primed = false;
  549. if (!list_empty(&ci_ep->queue))
  550. ci_ep_submit_next_request(ci_ep);
  551. ci_req->req.actual = ci_req->req.length - len;
  552. ci_debounce(ci_req, in);
  553. DBG("ept%d %s req %p, complete %x\n",
  554. num, in ? "in" : "out", ci_req, len);
  555. if (num != 0 || controller.ep0_data_phase)
  556. ci_req->req.complete(&ci_ep->ep, &ci_req->req);
  557. if (num == 0 && controller.ep0_data_phase) {
  558. /*
  559. * Data Stage is complete, so flip ep0 dir for Status Stage,
  560. * which always transfers a packet in the opposite direction.
  561. */
  562. DBG("%s: flip ep0 dir for Status Stage\n", __func__);
  563. flip_ep0_direction();
  564. controller.ep0_data_phase = false;
  565. ci_req->req.length = 0;
  566. usb_ep_queue(&ci_ep->ep, &ci_req->req, 0);
  567. }
  568. }
  569. #define SETUP(type, request) (((type) << 8) | (request))
  570. static void handle_setup(void)
  571. {
  572. struct ci_ep *ci_ep = &controller.ep[0];
  573. struct ci_req *ci_req;
  574. struct usb_request *req;
  575. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  576. struct ept_queue_head *head;
  577. struct usb_ctrlrequest r;
  578. int status = 0;
  579. int num, in, _num, _in, i;
  580. char *buf;
  581. ci_req = controller.ep0_req;
  582. req = &ci_req->req;
  583. head = ci_get_qh(0, 0); /* EP0 OUT */
  584. ci_invalidate_qh(0);
  585. memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
  586. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  587. writel(EPT_RX(0), &udc->epsetupstat);
  588. #else
  589. writel(EPT_RX(0), &udc->epstat);
  590. #endif
  591. DBG("handle setup %s, %x, %x index %x value %x length %x\n",
  592. reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex,
  593. r.wValue, r.wLength);
  594. /* Set EP0 dir for Data Stage based on Setup Stage data */
  595. if (r.bRequestType & USB_DIR_IN) {
  596. DBG("%s: Set ep0 to IN for Data Stage\n", __func__);
  597. ep0_desc.bEndpointAddress = USB_DIR_IN;
  598. } else {
  599. DBG("%s: Set ep0 to OUT for Data Stage\n", __func__);
  600. ep0_desc.bEndpointAddress = 0;
  601. }
  602. if (r.wLength) {
  603. controller.ep0_data_phase = true;
  604. } else {
  605. /* 0 length -> no Data Stage. Flip dir for Status Stage */
  606. DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__);
  607. flip_ep0_direction();
  608. controller.ep0_data_phase = false;
  609. }
  610. list_del_init(&ci_req->queue);
  611. ci_ep->req_primed = false;
  612. switch (SETUP(r.bRequestType, r.bRequest)) {
  613. case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
  614. _num = r.wIndex & 15;
  615. _in = !!(r.wIndex & 0x80);
  616. if ((r.wValue == 0) && (r.wLength == 0)) {
  617. req->length = 0;
  618. for (i = 0; i < NUM_ENDPOINTS; i++) {
  619. struct ci_ep *ep = &controller.ep[i];
  620. if (!ep->desc)
  621. continue;
  622. num = ep->desc->bEndpointAddress
  623. & USB_ENDPOINT_NUMBER_MASK;
  624. in = (ep->desc->bEndpointAddress
  625. & USB_DIR_IN) != 0;
  626. if ((num == _num) && (in == _in)) {
  627. ep_enable(num, in, ep->ep.maxpacket);
  628. usb_ep_queue(controller.gadget.ep0,
  629. req, 0);
  630. break;
  631. }
  632. }
  633. }
  634. return;
  635. case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
  636. /*
  637. * write address delayed (will take effect
  638. * after the next IN txn)
  639. */
  640. writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
  641. req->length = 0;
  642. usb_ep_queue(controller.gadget.ep0, req, 0);
  643. return;
  644. case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
  645. req->length = 2;
  646. buf = (char *)req->buf;
  647. buf[0] = 1 << USB_DEVICE_SELF_POWERED;
  648. buf[1] = 0;
  649. usb_ep_queue(controller.gadget.ep0, req, 0);
  650. return;
  651. }
  652. /* pass request up to the gadget driver */
  653. if (controller.driver)
  654. status = controller.driver->setup(&controller.gadget, &r);
  655. else
  656. status = -ENODEV;
  657. if (!status)
  658. return;
  659. DBG("STALL reqname %s type %x value %x, index %x\n",
  660. reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
  661. writel((1<<16) | (1 << 0), &udc->epctrl[0]);
  662. }
  663. static void stop_activity(void)
  664. {
  665. int i, num, in;
  666. struct ept_queue_head *head;
  667. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  668. writel(readl(&udc->epcomp), &udc->epcomp);
  669. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  670. writel(readl(&udc->epsetupstat), &udc->epsetupstat);
  671. #endif
  672. writel(readl(&udc->epstat), &udc->epstat);
  673. writel(0xffffffff, &udc->epflush);
  674. /* error out any pending reqs */
  675. for (i = 0; i < NUM_ENDPOINTS; i++) {
  676. if (i != 0)
  677. writel(0, &udc->epctrl[i]);
  678. if (controller.ep[i].desc) {
  679. num = controller.ep[i].desc->bEndpointAddress
  680. & USB_ENDPOINT_NUMBER_MASK;
  681. in = (controller.ep[i].desc->bEndpointAddress
  682. & USB_DIR_IN) != 0;
  683. head = ci_get_qh(num, in);
  684. head->info = INFO_ACTIVE;
  685. ci_flush_qh(num);
  686. }
  687. }
  688. }
  689. void udc_irq(void)
  690. {
  691. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  692. unsigned n = readl(&udc->usbsts);
  693. writel(n, &udc->usbsts);
  694. int bit, i, num, in;
  695. n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
  696. if (n == 0)
  697. return;
  698. if (n & STS_URI) {
  699. DBG("-- reset --\n");
  700. stop_activity();
  701. }
  702. if (n & STS_SLI)
  703. DBG("-- suspend --\n");
  704. if (n & STS_PCI) {
  705. int max = 64;
  706. int speed = USB_SPEED_FULL;
  707. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  708. bit = (readl(&udc->hostpc1_devlc) >> 25) & 3;
  709. #else
  710. bit = (readl(&udc->portsc) >> 26) & 3;
  711. #endif
  712. DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
  713. if (bit == 2) {
  714. speed = USB_SPEED_HIGH;
  715. max = 512;
  716. }
  717. controller.gadget.speed = speed;
  718. for (i = 1; i < NUM_ENDPOINTS; i++) {
  719. if (controller.ep[i].ep.maxpacket > max)
  720. controller.ep[i].ep.maxpacket = max;
  721. }
  722. }
  723. if (n & STS_UEI)
  724. printf("<UEI %x>\n", readl(&udc->epcomp));
  725. if ((n & STS_UI) || (n & STS_UEI)) {
  726. #ifdef CONFIG_CI_UDC_HAS_HOSTPC
  727. n = readl(&udc->epsetupstat);
  728. #else
  729. n = readl(&udc->epstat);
  730. #endif
  731. if (n & EPT_RX(0))
  732. handle_setup();
  733. n = readl(&udc->epcomp);
  734. if (n != 0)
  735. writel(n, &udc->epcomp);
  736. for (i = 0; i < NUM_ENDPOINTS && n; i++) {
  737. if (controller.ep[i].desc) {
  738. num = controller.ep[i].desc->bEndpointAddress
  739. & USB_ENDPOINT_NUMBER_MASK;
  740. in = (controller.ep[i].desc->bEndpointAddress
  741. & USB_DIR_IN) != 0;
  742. bit = (in) ? EPT_TX(num) : EPT_RX(num);
  743. if (n & bit)
  744. handle_ep_complete(&controller.ep[i]);
  745. }
  746. }
  747. }
  748. }
  749. int usb_gadget_handle_interrupts(int index)
  750. {
  751. u32 value;
  752. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  753. value = readl(&udc->usbsts);
  754. if (value)
  755. udc_irq();
  756. return value;
  757. }
  758. void udc_disconnect(void)
  759. {
  760. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  761. /* disable pullup */
  762. stop_activity();
  763. writel(USBCMD_FS2, &udc->usbcmd);
  764. udelay(800);
  765. if (controller.driver)
  766. controller.driver->disconnect(&controller.gadget);
  767. }
  768. static int ci_pullup(struct usb_gadget *gadget, int is_on)
  769. {
  770. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  771. if (is_on) {
  772. /* RESET */
  773. writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
  774. udelay(200);
  775. ci_init_after_reset(controller.ctrl);
  776. writel((unsigned long)controller.epts, &udc->epinitaddr);
  777. /* select DEVICE mode */
  778. writel(USBMODE_DEVICE, &udc->usbmode);
  779. #if !defined(CONFIG_USB_GADGET_DUALSPEED)
  780. /* Port force Full-Speed Connect */
  781. setbits_le32(&udc->portsc, PFSC);
  782. #endif
  783. writel(0xffffffff, &udc->epflush);
  784. /* Turn on the USB connection by enabling the pullup resistor */
  785. setbits_le32(&udc->usbcmd, USBCMD_ITC(MICRO_8FRAME) |
  786. USBCMD_RUN);
  787. } else {
  788. udc_disconnect();
  789. }
  790. return 0;
  791. }
  792. static int ci_udc_probe(void)
  793. {
  794. struct ept_queue_head *head;
  795. int i;
  796. const int num = 2 * NUM_ENDPOINTS;
  797. const int eplist_min_align = 4096;
  798. const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
  799. const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
  800. const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
  801. /* The QH list must be aligned to 4096 bytes. */
  802. controller.epts = memalign(eplist_align, eplist_sz);
  803. if (!controller.epts)
  804. return -ENOMEM;
  805. memset(controller.epts, 0, eplist_sz);
  806. controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ);
  807. if (!controller.items_mem) {
  808. free(controller.epts);
  809. return -ENOMEM;
  810. }
  811. memset(controller.items_mem, 0, ILIST_SZ);
  812. for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
  813. /*
  814. * Configure QH for each endpoint. The structure of the QH list
  815. * is such that each two subsequent fields, N and N+1 where N is
  816. * even, in the QH list represent QH for one endpoint. The Nth
  817. * entry represents OUT configuration and the N+1th entry does
  818. * represent IN configuration of the endpoint.
  819. */
  820. head = controller.epts + i;
  821. if (i < 2)
  822. head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
  823. | CONFIG_ZLT | CONFIG_IOS;
  824. else
  825. head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
  826. | CONFIG_ZLT;
  827. head->next = TERMINATE;
  828. head->info = 0;
  829. if (i & 1) {
  830. ci_flush_qh(i / 2);
  831. ci_flush_qtd(i / 2);
  832. }
  833. }
  834. INIT_LIST_HEAD(&controller.gadget.ep_list);
  835. /* Init EP 0 */
  836. memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
  837. controller.ep[0].desc = &ep0_desc;
  838. INIT_LIST_HEAD(&controller.ep[0].queue);
  839. controller.ep[0].req_primed = false;
  840. controller.gadget.ep0 = &controller.ep[0].ep;
  841. INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
  842. /* Init EP 1..3 */
  843. for (i = 1; i < 4; i++) {
  844. memcpy(&controller.ep[i].ep, &ci_ep_init[i],
  845. sizeof(*ci_ep_init));
  846. INIT_LIST_HEAD(&controller.ep[i].queue);
  847. controller.ep[i].req_primed = false;
  848. list_add_tail(&controller.ep[i].ep.ep_list,
  849. &controller.gadget.ep_list);
  850. }
  851. /* Init EP 4..n */
  852. for (i = 4; i < NUM_ENDPOINTS; i++) {
  853. memcpy(&controller.ep[i].ep, &ci_ep_init[4],
  854. sizeof(*ci_ep_init));
  855. INIT_LIST_HEAD(&controller.ep[i].queue);
  856. controller.ep[i].req_primed = false;
  857. list_add_tail(&controller.ep[i].ep.ep_list,
  858. &controller.gadget.ep_list);
  859. }
  860. ci_ep_alloc_request(&controller.ep[0].ep, 0);
  861. if (!controller.ep0_req) {
  862. free(controller.items_mem);
  863. free(controller.epts);
  864. return -ENOMEM;
  865. }
  866. return 0;
  867. }
  868. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  869. {
  870. int ret;
  871. if (!driver)
  872. return -EINVAL;
  873. if (!driver->bind || !driver->setup || !driver->disconnect)
  874. return -EINVAL;
  875. #if CONFIG_IS_ENABLED(DM_USB)
  876. ret = usb_setup_ehci_gadget(&controller.ctrl);
  877. #else
  878. ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl);
  879. #endif
  880. if (ret)
  881. return ret;
  882. ret = ci_udc_probe();
  883. if (ret) {
  884. DBG("udc probe failed, returned %d\n", ret);
  885. return ret;
  886. }
  887. ret = driver->bind(&controller.gadget);
  888. if (ret) {
  889. DBG("driver->bind() returned %d\n", ret);
  890. return ret;
  891. }
  892. controller.driver = driver;
  893. return 0;
  894. }
  895. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  896. {
  897. udc_disconnect();
  898. driver->unbind(&controller.gadget);
  899. controller.driver = NULL;
  900. ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req);
  901. free(controller.items_mem);
  902. free(controller.epts);
  903. #if CONFIG_IS_ENABLED(DM_USB)
  904. usb_remove_ehci_gadget(&controller.ctrl);
  905. #else
  906. usb_lowlevel_stop(0);
  907. controller.ctrl = NULL;
  908. #endif
  909. return 0;
  910. }
  911. bool dfu_usb_get_reset(void)
  912. {
  913. struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
  914. return !!(readl(&udc->usbsts) & STS_URI);
  915. }