designware_wdt.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Altera Corporation <www.altera.com>
  4. */
  5. #include <clk.h>
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <reset.h>
  9. #include <wdt.h>
  10. #include <asm/io.h>
  11. #include <linux/bitops.h>
  12. #define DW_WDT_CR 0x00
  13. #define DW_WDT_TORR 0x04
  14. #define DW_WDT_CRR 0x0C
  15. #define DW_WDT_CR_EN_OFFSET 0x00
  16. #define DW_WDT_CR_RMOD_OFFSET 0x01
  17. #define DW_WDT_CRR_RESTART_VAL 0x76
  18. struct designware_wdt_priv {
  19. void __iomem *base;
  20. unsigned int clk_khz;
  21. struct reset_ctl_bulk resets;
  22. };
  23. /*
  24. * Set the watchdog time interval.
  25. * Counter is 32 bit.
  26. */
  27. static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
  28. unsigned int timeout)
  29. {
  30. signed int i;
  31. /* calculate the timeout range value */
  32. i = fls(timeout * clk_khz - 1) - 16;
  33. i = clamp(i, 0, 15);
  34. writel(i | (i << 4), base + DW_WDT_TORR);
  35. return 0;
  36. }
  37. static void designware_wdt_enable(void __iomem *base)
  38. {
  39. writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
  40. }
  41. static unsigned int designware_wdt_is_enabled(void __iomem *base)
  42. {
  43. return readl(base + DW_WDT_CR) & BIT(0);
  44. }
  45. static void designware_wdt_reset_common(void __iomem *base)
  46. {
  47. if (designware_wdt_is_enabled(base))
  48. /* restart the watchdog counter */
  49. writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
  50. }
  51. #if !CONFIG_IS_ENABLED(WDT)
  52. void hw_watchdog_reset(void)
  53. {
  54. designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
  55. }
  56. void hw_watchdog_init(void)
  57. {
  58. /* reset to disable the watchdog */
  59. hw_watchdog_reset();
  60. /* set timer in miliseconds */
  61. designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
  62. CONFIG_DW_WDT_CLOCK_KHZ,
  63. CONFIG_WATCHDOG_TIMEOUT_MSECS);
  64. /* enable the watchdog */
  65. designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
  66. /* reset the watchdog */
  67. hw_watchdog_reset();
  68. }
  69. #else
  70. static int designware_wdt_reset(struct udevice *dev)
  71. {
  72. struct designware_wdt_priv *priv = dev_get_priv(dev);
  73. designware_wdt_reset_common(priv->base);
  74. return 0;
  75. }
  76. static int designware_wdt_stop(struct udevice *dev)
  77. {
  78. struct designware_wdt_priv *priv = dev_get_priv(dev);
  79. designware_wdt_reset(dev);
  80. writel(0, priv->base + DW_WDT_CR);
  81. if (CONFIG_IS_ENABLED(DM_RESET)) {
  82. int ret;
  83. ret = reset_assert_bulk(&priv->resets);
  84. if (ret)
  85. return ret;
  86. ret = reset_deassert_bulk(&priv->resets);
  87. if (ret)
  88. return ret;
  89. }
  90. return 0;
  91. }
  92. static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  93. {
  94. struct designware_wdt_priv *priv = dev_get_priv(dev);
  95. designware_wdt_stop(dev);
  96. /* set timer in miliseconds */
  97. designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
  98. designware_wdt_enable(priv->base);
  99. /* reset the watchdog */
  100. return designware_wdt_reset(dev);
  101. }
  102. static int designware_wdt_probe(struct udevice *dev)
  103. {
  104. struct designware_wdt_priv *priv = dev_get_priv(dev);
  105. __maybe_unused int ret;
  106. priv->base = dev_remap_addr(dev);
  107. if (!priv->base)
  108. return -EINVAL;
  109. #if CONFIG_IS_ENABLED(CLK)
  110. struct clk clk;
  111. ret = clk_get_by_index(dev, 0, &clk);
  112. if (ret)
  113. return ret;
  114. ret = clk_enable(&clk);
  115. if (ret)
  116. goto err;
  117. priv->clk_khz = clk_get_rate(&clk) / 1000;
  118. if (!priv->clk_khz) {
  119. ret = -EINVAL;
  120. goto err;
  121. }
  122. #else
  123. priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
  124. #endif
  125. if (CONFIG_IS_ENABLED(DM_RESET)) {
  126. ret = reset_get_bulk(dev, &priv->resets);
  127. if (ret)
  128. goto err;
  129. ret = reset_deassert_bulk(&priv->resets);
  130. if (ret)
  131. goto err;
  132. }
  133. /* reset to disable the watchdog */
  134. return designware_wdt_stop(dev);
  135. err:
  136. #if CONFIG_IS_ENABLED(CLK)
  137. clk_free(&clk);
  138. #endif
  139. return ret;
  140. }
  141. static const struct wdt_ops designware_wdt_ops = {
  142. .start = designware_wdt_start,
  143. .reset = designware_wdt_reset,
  144. .stop = designware_wdt_stop,
  145. };
  146. static const struct udevice_id designware_wdt_ids[] = {
  147. { .compatible = "snps,dw-wdt"},
  148. {}
  149. };
  150. U_BOOT_DRIVER(designware_wdt) = {
  151. .name = "designware_wdt",
  152. .id = UCLASS_WDT,
  153. .of_match = designware_wdt_ids,
  154. .priv_auto = sizeof(struct designware_wdt_priv),
  155. .probe = designware_wdt_probe,
  156. .ops = &designware_wdt_ops,
  157. .flags = DM_FLAG_PRE_RELOC,
  158. };
  159. #endif