altera_qspi.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
  4. */
  5. #include <common.h>
  6. #include <console.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <fdt_support.h>
  10. #include <flash.h>
  11. #include <log.h>
  12. #include <mtd.h>
  13. #include <asm/global_data.h>
  14. #include <asm/io.h>
  15. #include <linux/bitops.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /* The STATUS register */
  18. #define QUADSPI_SR_BP0 BIT(2)
  19. #define QUADSPI_SR_BP1 BIT(3)
  20. #define QUADSPI_SR_BP2 BIT(4)
  21. #define QUADSPI_SR_BP2_0 GENMASK(4, 2)
  22. #define QUADSPI_SR_BP3 BIT(6)
  23. #define QUADSPI_SR_TB BIT(5)
  24. /*
  25. * The QUADSPI_MEM_OP register is used to do memory protect and erase operations
  26. */
  27. #define QUADSPI_MEM_OP_BULK_ERASE 0x00000001
  28. #define QUADSPI_MEM_OP_SECTOR_ERASE 0x00000002
  29. #define QUADSPI_MEM_OP_SECTOR_PROTECT 0x00000003
  30. /*
  31. * The QUADSPI_ISR register is used to determine whether an invalid write or
  32. * erase operation trigerred an interrupt
  33. */
  34. #define QUADSPI_ISR_ILLEGAL_ERASE BIT(0)
  35. #define QUADSPI_ISR_ILLEGAL_WRITE BIT(1)
  36. struct altera_qspi_regs {
  37. u32 rd_status;
  38. u32 rd_sid;
  39. u32 rd_rdid;
  40. u32 mem_op;
  41. u32 isr;
  42. u32 imr;
  43. u32 chip_select;
  44. };
  45. struct altera_qspi_plat {
  46. struct altera_qspi_regs *regs;
  47. void *base;
  48. unsigned long size;
  49. };
  50. static uint flash_verbose;
  51. flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
  52. static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
  53. uint64_t *len);
  54. void flash_print_info(flash_info_t *info)
  55. {
  56. struct mtd_info *mtd = info->mtd;
  57. loff_t ofs;
  58. u64 len;
  59. printf("Altera QSPI flash Size: %ld MB in %d Sectors\n",
  60. info->size >> 20, info->sector_count);
  61. altera_qspi_get_locked_range(mtd, &ofs, &len);
  62. printf(" %08lX +%lX", info->start[0], info->size);
  63. if (len) {
  64. printf(", protected %08llX +%llX",
  65. info->start[0] + ofs, len);
  66. }
  67. putc('\n');
  68. }
  69. void flash_set_verbose(uint v)
  70. {
  71. flash_verbose = v;
  72. }
  73. int flash_erase(flash_info_t *info, int s_first, int s_last)
  74. {
  75. struct mtd_info *mtd = info->mtd;
  76. struct erase_info instr;
  77. int ret;
  78. memset(&instr, 0, sizeof(instr));
  79. instr.mtd = mtd;
  80. instr.addr = mtd->erasesize * s_first;
  81. instr.len = mtd->erasesize * (s_last + 1 - s_first);
  82. flash_set_verbose(1);
  83. ret = mtd_erase(mtd, &instr);
  84. flash_set_verbose(0);
  85. if (ret)
  86. return ERR_PROTECTED;
  87. puts(" done\n");
  88. return 0;
  89. }
  90. int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  91. {
  92. struct mtd_info *mtd = info->mtd;
  93. struct udevice *dev = mtd->dev;
  94. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  95. ulong base = (ulong)pdata->base;
  96. loff_t to = addr - base;
  97. size_t retlen;
  98. int ret;
  99. ret = mtd_write(mtd, to, cnt, &retlen, src);
  100. if (ret)
  101. return ERR_PROTECTED;
  102. return 0;
  103. }
  104. unsigned long flash_init(void)
  105. {
  106. struct udevice *dev;
  107. /* probe every MTD device */
  108. for (uclass_first_device(UCLASS_MTD, &dev);
  109. dev;
  110. uclass_next_device(&dev)) {
  111. }
  112. return flash_info[0].size;
  113. }
  114. static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr)
  115. {
  116. struct udevice *dev = mtd->dev;
  117. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  118. struct altera_qspi_regs *regs = pdata->regs;
  119. size_t addr = instr->addr;
  120. size_t len = instr->len;
  121. size_t end = addr + len;
  122. u32 sect;
  123. u32 stat;
  124. u32 *flash, *last;
  125. instr->state = MTD_ERASING;
  126. addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
  127. while (addr < end) {
  128. if (ctrlc()) {
  129. if (flash_verbose)
  130. putc('\n');
  131. instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
  132. instr->state = MTD_ERASE_FAILED;
  133. mtd_erase_callback(instr);
  134. return -EIO;
  135. }
  136. flash = pdata->base + addr;
  137. last = pdata->base + addr + mtd->erasesize;
  138. /* skip erase if sector is blank */
  139. while (flash < last) {
  140. if (readl(flash) != 0xffffffff)
  141. break;
  142. flash++;
  143. }
  144. if (flash < last) {
  145. sect = addr / mtd->erasesize;
  146. sect <<= 8;
  147. sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
  148. debug("erase %08x\n", sect);
  149. writel(sect, &regs->mem_op);
  150. stat = readl(&regs->isr);
  151. if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
  152. /* erase failed, sector might be protected */
  153. debug("erase %08x fail %x\n", sect, stat);
  154. writel(stat, &regs->isr); /* clear isr */
  155. instr->fail_addr = addr;
  156. instr->state = MTD_ERASE_FAILED;
  157. mtd_erase_callback(instr);
  158. return -EIO;
  159. }
  160. if (flash_verbose)
  161. putc('.');
  162. } else {
  163. if (flash_verbose)
  164. putc(',');
  165. }
  166. addr += mtd->erasesize;
  167. }
  168. instr->state = MTD_ERASE_DONE;
  169. mtd_erase_callback(instr);
  170. return 0;
  171. }
  172. static int altera_qspi_read(struct mtd_info *mtd, loff_t from, size_t len,
  173. size_t *retlen, u_char *buf)
  174. {
  175. struct udevice *dev = mtd->dev;
  176. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  177. memcpy_fromio(buf, pdata->base + from, len);
  178. *retlen = len;
  179. return 0;
  180. }
  181. static int altera_qspi_write(struct mtd_info *mtd, loff_t to, size_t len,
  182. size_t *retlen, const u_char *buf)
  183. {
  184. struct udevice *dev = mtd->dev;
  185. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  186. struct altera_qspi_regs *regs = pdata->regs;
  187. u32 stat;
  188. memcpy_toio(pdata->base + to, buf, len);
  189. /* check whether write triggered a illegal write interrupt */
  190. stat = readl(&regs->isr);
  191. if (stat & QUADSPI_ISR_ILLEGAL_WRITE) {
  192. /* write failed, sector might be protected */
  193. debug("write fail %x\n", stat);
  194. writel(stat, &regs->isr); /* clear isr */
  195. return -EIO;
  196. }
  197. *retlen = len;
  198. return 0;
  199. }
  200. static void altera_qspi_sync(struct mtd_info *mtd)
  201. {
  202. }
  203. static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
  204. uint64_t *len)
  205. {
  206. struct udevice *dev = mtd->dev;
  207. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  208. struct altera_qspi_regs *regs = pdata->regs;
  209. int shift0 = ffs(QUADSPI_SR_BP2_0) - 1;
  210. int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3;
  211. u32 stat = readl(&regs->rd_status);
  212. unsigned pow = ((stat & QUADSPI_SR_BP2_0) >> shift0) |
  213. ((stat & QUADSPI_SR_BP3) >> shift3);
  214. *ofs = 0;
  215. *len = 0;
  216. if (pow) {
  217. *len = mtd->erasesize << (pow - 1);
  218. if (*len > mtd->size)
  219. *len = mtd->size;
  220. if (!(stat & QUADSPI_SR_TB))
  221. *ofs = mtd->size - *len;
  222. }
  223. }
  224. static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  225. {
  226. struct udevice *dev = mtd->dev;
  227. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  228. struct altera_qspi_regs *regs = pdata->regs;
  229. u32 sector_start, sector_end;
  230. u32 num_sectors;
  231. u32 mem_op;
  232. u32 sr_bp;
  233. u32 sr_tb;
  234. num_sectors = mtd->size / mtd->erasesize;
  235. sector_start = ofs / mtd->erasesize;
  236. sector_end = (ofs + len) / mtd->erasesize;
  237. if (sector_start >= num_sectors / 2) {
  238. sr_bp = fls(num_sectors - 1 - sector_start) + 1;
  239. sr_tb = 0;
  240. } else if (sector_end < num_sectors / 2) {
  241. sr_bp = fls(sector_end) + 1;
  242. sr_tb = 1;
  243. } else {
  244. sr_bp = 15;
  245. sr_tb = 0;
  246. }
  247. mem_op = (sr_tb << 12) | (sr_bp << 8);
  248. mem_op |= QUADSPI_MEM_OP_SECTOR_PROTECT;
  249. debug("lock %08x\n", mem_op);
  250. writel(mem_op, &regs->mem_op);
  251. return 0;
  252. }
  253. static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  254. {
  255. struct udevice *dev = mtd->dev;
  256. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  257. struct altera_qspi_regs *regs = pdata->regs;
  258. u32 mem_op;
  259. mem_op = QUADSPI_MEM_OP_SECTOR_PROTECT;
  260. debug("unlock %08x\n", mem_op);
  261. writel(mem_op, &regs->mem_op);
  262. return 0;
  263. }
  264. static int altera_qspi_probe(struct udevice *dev)
  265. {
  266. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  267. struct altera_qspi_regs *regs = pdata->regs;
  268. unsigned long base = (unsigned long)pdata->base;
  269. struct mtd_info *mtd;
  270. flash_info_t *flash = &flash_info[0];
  271. u32 rdid;
  272. int i;
  273. rdid = readl(&regs->rd_rdid);
  274. debug("rdid %x\n", rdid);
  275. mtd = dev_get_uclass_priv(dev);
  276. mtd->dev = dev;
  277. mtd->name = "nor0";
  278. mtd->type = MTD_NORFLASH;
  279. mtd->flags = MTD_CAP_NORFLASH;
  280. mtd->size = 1 << ((rdid & 0xff) - 6);
  281. mtd->writesize = 1;
  282. mtd->writebufsize = mtd->writesize;
  283. mtd->_erase = altera_qspi_erase;
  284. mtd->_read = altera_qspi_read;
  285. mtd->_write = altera_qspi_write;
  286. mtd->_sync = altera_qspi_sync;
  287. mtd->_lock = altera_qspi_lock;
  288. mtd->_unlock = altera_qspi_unlock;
  289. mtd->numeraseregions = 0;
  290. mtd->erasesize = 0x10000;
  291. if (add_mtd_device(mtd))
  292. return -ENOMEM;
  293. flash->mtd = mtd;
  294. flash->size = mtd->size;
  295. flash->sector_count = mtd->size / mtd->erasesize;
  296. flash->flash_id = rdid;
  297. flash->start[0] = base;
  298. for (i = 1; i < flash->sector_count; i++)
  299. flash->start[i] = flash->start[i - 1] + mtd->erasesize;
  300. gd->bd->bi_flashstart = base;
  301. return 0;
  302. }
  303. static int altera_qspi_of_to_plat(struct udevice *dev)
  304. {
  305. struct altera_qspi_plat *pdata = dev_get_plat(dev);
  306. void *blob = (void *)gd->fdt_blob;
  307. int node = dev_of_offset(dev);
  308. const char *list, *end;
  309. const fdt32_t *cell;
  310. void *base;
  311. unsigned long addr, size;
  312. int parent, addrc, sizec;
  313. int len, idx;
  314. /*
  315. * decode regs. there are multiple reg tuples, and they need to
  316. * match with reg-names.
  317. */
  318. parent = fdt_parent_offset(blob, node);
  319. fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
  320. list = fdt_getprop(blob, node, "reg-names", &len);
  321. if (!list)
  322. return -ENOENT;
  323. end = list + len;
  324. cell = fdt_getprop(blob, node, "reg", &len);
  325. if (!cell)
  326. return -ENOENT;
  327. idx = 0;
  328. while (list < end) {
  329. addr = fdt_translate_address((void *)blob,
  330. node, cell + idx);
  331. size = fdt_addr_to_cpu(cell[idx + addrc]);
  332. base = map_physmem(addr, size, MAP_NOCACHE);
  333. len = strlen(list);
  334. if (strcmp(list, "avl_csr") == 0) {
  335. pdata->regs = base;
  336. } else if (strcmp(list, "avl_mem") == 0) {
  337. pdata->base = base;
  338. pdata->size = size;
  339. }
  340. idx += addrc + sizec;
  341. list += (len + 1);
  342. }
  343. return 0;
  344. }
  345. static const struct udevice_id altera_qspi_ids[] = {
  346. { .compatible = "altr,quadspi-1.0" },
  347. {}
  348. };
  349. U_BOOT_DRIVER(altera_qspi) = {
  350. .name = "altera_qspi",
  351. .id = UCLASS_MTD,
  352. .of_match = altera_qspi_ids,
  353. .of_to_plat = altera_qspi_of_to_plat,
  354. .plat_auto = sizeof(struct altera_qspi_plat),
  355. .probe = altera_qspi_probe,
  356. };