evm.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * Texas Instruments Incorporated, <www.ti.com>
  5. *
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. *
  8. * Based on previous work by:
  9. * Aneesh V <aneesh@ti.com>
  10. * Steve Sakoman <steve@sakoman.com>
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <palmas.h>
  15. #include <sata.h>
  16. #include <serial.h>
  17. #include <linux/string.h>
  18. #include <asm/gpio.h>
  19. #include <usb.h>
  20. #include <linux/usb/gadget.h>
  21. #include <asm/omap_common.h>
  22. #include <asm/omap_sec_common.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/dra7xx_iodelay.h>
  25. #include <asm/emif.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/arch/mmc_host_def.h>
  28. #include <asm/arch/sata.h>
  29. #include <dwc3-uboot.h>
  30. #include <dwc3-omap-uboot.h>
  31. #include <i2c.h>
  32. #include <ti-usb-phy-uboot.h>
  33. #include <miiphy.h>
  34. #include "mux_data.h"
  35. #include "../common/board_detect.h"
  36. #define board_is_dra76x_evm() board_ti_is("DRA76/7x")
  37. #define board_is_dra74x_evm() board_ti_is("5777xCPU")
  38. #define board_is_dra72x_evm() board_ti_is("DRA72x-T")
  39. #define board_is_dra71x_evm() board_ti_is("DRA79x,D")
  40. #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
  41. (strncmp("H", board_ti_get_rev(), 1) <= 0))
  42. #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
  43. (strncmp("C", board_ti_get_rev(), 1) <= 0))
  44. #define board_ti_get_emif_size() board_ti_get_emif1_size() + \
  45. board_ti_get_emif2_size()
  46. #ifdef CONFIG_DRIVER_TI_CPSW
  47. #include <cpsw.h>
  48. #endif
  49. DECLARE_GLOBAL_DATA_PTR;
  50. /* GPIO 7_11 */
  51. #define GPIO_DDR_VTT_EN 203
  52. #define SYSINFO_BOARD_NAME_MAX_LEN 37
  53. /* I2C I/O Expander */
  54. #define NAND_PCF8575_ADDR 0x21
  55. #define NAND_PCF8575_I2C_BUS_NUM 0
  56. const struct omap_sysinfo sysinfo = {
  57. "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
  58. };
  59. static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
  60. .sdram_config_init = 0x61851ab2,
  61. .sdram_config = 0x61851ab2,
  62. .sdram_config2 = 0x08000000,
  63. .ref_ctrl = 0x000040F1,
  64. .ref_ctrl_final = 0x00001035,
  65. .sdram_tim1 = 0xCCCF36B3,
  66. .sdram_tim2 = 0x308F7FDA,
  67. .sdram_tim3 = 0x427F88A8,
  68. .read_idle_ctrl = 0x00050000,
  69. .zq_config = 0x0007190B,
  70. .temp_alert_config = 0x00000000,
  71. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  72. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  73. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  74. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  75. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  76. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  77. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  78. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  79. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  80. .emif_rd_wr_lvl_ctl = 0x00000000,
  81. .emif_rd_wr_exec_thresh = 0x00000305
  82. };
  83. static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
  84. .sdram_config_init = 0x61851B32,
  85. .sdram_config = 0x61851B32,
  86. .sdram_config2 = 0x08000000,
  87. .ref_ctrl = 0x000040F1,
  88. .ref_ctrl_final = 0x00001035,
  89. .sdram_tim1 = 0xCCCF36B3,
  90. .sdram_tim2 = 0x308F7FDA,
  91. .sdram_tim3 = 0x427F88A8,
  92. .read_idle_ctrl = 0x00050000,
  93. .zq_config = 0x0007190B,
  94. .temp_alert_config = 0x00000000,
  95. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  96. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  97. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  98. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  99. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  100. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  101. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  102. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  103. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  104. .emif_rd_wr_lvl_ctl = 0x00000000,
  105. .emif_rd_wr_exec_thresh = 0x00000305
  106. };
  107. static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
  108. .sdram_config_init = 0x61862B32,
  109. .sdram_config = 0x61862B32,
  110. .sdram_config2 = 0x08000000,
  111. .ref_ctrl = 0x0000514C,
  112. .ref_ctrl_final = 0x0000144A,
  113. .sdram_tim1 = 0xD113781C,
  114. .sdram_tim2 = 0x30717FE3,
  115. .sdram_tim3 = 0x409F86A8,
  116. .read_idle_ctrl = 0x00050000,
  117. .zq_config = 0x5007190B,
  118. .temp_alert_config = 0x00000000,
  119. .emif_ddr_phy_ctlr_1_init = 0x0024400D,
  120. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  121. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  122. .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
  123. .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
  124. .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
  125. .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
  126. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  127. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  128. .emif_rd_wr_lvl_ctl = 0x00000000,
  129. .emif_rd_wr_exec_thresh = 0x00000305
  130. };
  131. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
  132. .sdram_config_init = 0x61862BB2,
  133. .sdram_config = 0x61862BB2,
  134. .sdram_config2 = 0x00000000,
  135. .ref_ctrl = 0x0000514D,
  136. .ref_ctrl_final = 0x0000144A,
  137. .sdram_tim1 = 0xD1137824,
  138. .sdram_tim2 = 0x30B37FE3,
  139. .sdram_tim3 = 0x409F8AD8,
  140. .read_idle_ctrl = 0x00050000,
  141. .zq_config = 0x5007190B,
  142. .temp_alert_config = 0x00000000,
  143. .emif_ddr_phy_ctlr_1_init = 0x0824400E,
  144. .emif_ddr_phy_ctlr_1 = 0x0E24400E,
  145. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  146. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  147. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  148. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  149. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  150. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  151. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  152. .emif_rd_wr_lvl_ctl = 0x00000000,
  153. .emif_rd_wr_exec_thresh = 0x00000305
  154. };
  155. const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
  156. .sdram_config_init = 0x61851ab2,
  157. .sdram_config = 0x61851ab2,
  158. .sdram_config2 = 0x08000000,
  159. .ref_ctrl = 0x000040F1,
  160. .ref_ctrl_final = 0x00001035,
  161. .sdram_tim1 = 0xCCCF36B3,
  162. .sdram_tim2 = 0x30BF7FDA,
  163. .sdram_tim3 = 0x427F8BA8,
  164. .read_idle_ctrl = 0x00050000,
  165. .zq_config = 0x0007190B,
  166. .temp_alert_config = 0x00000000,
  167. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  168. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  169. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  170. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  171. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  172. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  173. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  174. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  175. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  176. .emif_rd_wr_lvl_ctl = 0x00000000,
  177. .emif_rd_wr_exec_thresh = 0x00000305
  178. };
  179. const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
  180. .sdram_config_init = 0x61851B32,
  181. .sdram_config = 0x61851B32,
  182. .sdram_config2 = 0x08000000,
  183. .ref_ctrl = 0x000040F1,
  184. .ref_ctrl_final = 0x00001035,
  185. .sdram_tim1 = 0xCCCF36B3,
  186. .sdram_tim2 = 0x308F7FDA,
  187. .sdram_tim3 = 0x427F88A8,
  188. .read_idle_ctrl = 0x00050000,
  189. .zq_config = 0x0007190B,
  190. .temp_alert_config = 0x00000000,
  191. .emif_ddr_phy_ctlr_1_init = 0x0024400B,
  192. .emif_ddr_phy_ctlr_1 = 0x0E24400B,
  193. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  194. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  195. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  196. .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  197. .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
  198. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  199. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  200. .emif_rd_wr_lvl_ctl = 0x00000000,
  201. .emif_rd_wr_exec_thresh = 0x00000305
  202. };
  203. const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = {
  204. .sdram_config_init = 0x61862B32,
  205. .sdram_config = 0x61862B32,
  206. .sdram_config2 = 0x00000000,
  207. .ref_ctrl = 0x0000514C,
  208. .ref_ctrl_final = 0x0000144A,
  209. .sdram_tim1 = 0xD113783C,
  210. .sdram_tim2 = 0x30B47FE3,
  211. .sdram_tim3 = 0x409F8AD8,
  212. .read_idle_ctrl = 0x00050000,
  213. .zq_config = 0x5007190B,
  214. .temp_alert_config = 0x00000000,
  215. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  216. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  217. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  218. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  219. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  220. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  221. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  222. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  223. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  224. .emif_rd_wr_lvl_ctl = 0x00000000,
  225. .emif_rd_wr_exec_thresh = 0x00000305
  226. };
  227. const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = {
  228. .sdram_config_init = 0x61862B32,
  229. .sdram_config = 0x61862B32,
  230. .sdram_config2 = 0x00000000,
  231. .ref_ctrl = 0x0000514C,
  232. .ref_ctrl_final = 0x0000144A,
  233. .sdram_tim1 = 0xD113781C,
  234. .sdram_tim2 = 0x30B47FE3,
  235. .sdram_tim3 = 0x409F8AD8,
  236. .read_idle_ctrl = 0x00050000,
  237. .zq_config = 0x5007190B,
  238. .temp_alert_config = 0x00000000,
  239. .emif_ddr_phy_ctlr_1_init = 0x0824400D,
  240. .emif_ddr_phy_ctlr_1 = 0x0E24400D,
  241. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  242. .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
  243. .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
  244. .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
  245. .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
  246. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  247. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  248. .emif_rd_wr_lvl_ctl = 0x00000000,
  249. .emif_rd_wr_exec_thresh = 0x00000305
  250. };
  251. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  252. {
  253. u64 ram_size;
  254. ram_size = board_ti_get_emif_size();
  255. switch (omap_revision()) {
  256. case DRA752_ES1_0:
  257. case DRA752_ES1_1:
  258. case DRA752_ES2_0:
  259. switch (emif_nr) {
  260. case 1:
  261. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  262. *regs = &emif1_ddr3_532_mhz_1cs_2G;
  263. else
  264. *regs = &emif1_ddr3_532_mhz_1cs;
  265. break;
  266. case 2:
  267. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  268. *regs = &emif2_ddr3_532_mhz_1cs_2G;
  269. else
  270. *regs = &emif2_ddr3_532_mhz_1cs;
  271. break;
  272. }
  273. break;
  274. case DRA762_ABZ_ES1_0:
  275. case DRA762_ACD_ES1_0:
  276. case DRA762_ES1_0:
  277. if (emif_nr == 1)
  278. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76;
  279. else
  280. *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76;
  281. break;
  282. case DRA722_ES1_0:
  283. case DRA722_ES2_0:
  284. case DRA722_ES2_1:
  285. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  286. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
  287. else
  288. *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
  289. break;
  290. default:
  291. *regs = &emif1_ddr3_532_mhz_1cs;
  292. }
  293. }
  294. static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
  295. .dmm_lisa_map_0 = 0x0,
  296. .dmm_lisa_map_1 = 0x80640300,
  297. .dmm_lisa_map_2 = 0xC0500220,
  298. .dmm_lisa_map_3 = 0xFF020100,
  299. .is_ma_present = 0x1
  300. };
  301. static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
  302. .dmm_lisa_map_0 = 0x0,
  303. .dmm_lisa_map_1 = 0x0,
  304. .dmm_lisa_map_2 = 0x80600100,
  305. .dmm_lisa_map_3 = 0xFF020100,
  306. .is_ma_present = 0x1
  307. };
  308. const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
  309. .dmm_lisa_map_0 = 0x0,
  310. .dmm_lisa_map_1 = 0x0,
  311. .dmm_lisa_map_2 = 0x80740300,
  312. .dmm_lisa_map_3 = 0xFF020100,
  313. .is_ma_present = 0x1
  314. };
  315. /*
  316. * DRA722 EVM EMIF1 2GB CONFIGURATION
  317. * EMIF1 4 devices of 512Mb x 8 Micron
  318. */
  319. const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
  320. .dmm_lisa_map_0 = 0x0,
  321. .dmm_lisa_map_1 = 0x0,
  322. .dmm_lisa_map_2 = 0x80700100,
  323. .dmm_lisa_map_3 = 0xFF020100,
  324. .is_ma_present = 0x1
  325. };
  326. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  327. {
  328. u64 ram_size;
  329. ram_size = board_ti_get_emif_size();
  330. switch (omap_revision()) {
  331. case DRA762_ABZ_ES1_0:
  332. case DRA762_ACD_ES1_0:
  333. case DRA762_ES1_0:
  334. case DRA752_ES1_0:
  335. case DRA752_ES1_1:
  336. case DRA752_ES2_0:
  337. if (ram_size > CONFIG_MAX_MEM_MAPPED)
  338. *dmm_lisa_regs = &lisa_map_dra7_2GB;
  339. else
  340. *dmm_lisa_regs = &lisa_map_dra7_1536MB;
  341. break;
  342. case DRA722_ES1_0:
  343. case DRA722_ES2_0:
  344. case DRA722_ES2_1:
  345. default:
  346. if (ram_size < CONFIG_MAX_MEM_MAPPED)
  347. *dmm_lisa_regs = &lisa_map_2G_x_2;
  348. else
  349. *dmm_lisa_regs = &lisa_map_2G_x_4;
  350. break;
  351. }
  352. }
  353. struct vcores_data dra752_volts = {
  354. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  355. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  356. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  357. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  358. .mpu.pmic = &tps659038,
  359. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  360. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  361. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  362. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  363. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  364. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  365. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  366. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  367. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  368. .eve.pmic = &tps659038,
  369. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  370. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  371. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  372. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  373. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  374. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  375. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  376. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  377. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  378. .gpu.pmic = &tps659038,
  379. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  380. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  381. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  382. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  383. .core.addr = TPS659038_REG_ADDR_SMPS7,
  384. .core.pmic = &tps659038,
  385. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  386. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  387. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  388. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  389. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  390. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  391. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  392. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  393. .iva.pmic = &tps659038,
  394. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  395. };
  396. struct vcores_data dra76x_volts = {
  397. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  398. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  399. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  400. .mpu.addr = LP87565_REG_ADDR_BUCK01,
  401. .mpu.pmic = &lp87565,
  402. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  403. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  404. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  405. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  406. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  407. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  408. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  409. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  410. .eve.addr = TPS65917_REG_ADDR_SMPS1,
  411. .eve.pmic = &tps659038,
  412. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  413. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  414. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  415. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  416. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  417. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  418. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  419. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  420. .gpu.addr = LP87565_REG_ADDR_BUCK23,
  421. .gpu.pmic = &lp87565,
  422. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  423. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  424. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  425. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  426. .core.addr = TPS65917_REG_ADDR_SMPS3,
  427. .core.pmic = &tps659038,
  428. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  429. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  430. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  431. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  432. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  433. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  434. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  435. .iva.addr = TPS65917_REG_ADDR_SMPS4,
  436. .iva.pmic = &tps659038,
  437. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  438. };
  439. struct vcores_data dra722_volts = {
  440. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  441. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  442. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  443. .mpu.addr = TPS65917_REG_ADDR_SMPS1,
  444. .mpu.pmic = &tps659038,
  445. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  446. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  447. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  448. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  449. .core.addr = TPS65917_REG_ADDR_SMPS2,
  450. .core.pmic = &tps659038,
  451. /*
  452. * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
  453. * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
  454. */
  455. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  456. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  457. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  458. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  459. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  460. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  461. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  462. .gpu.addr = TPS65917_REG_ADDR_SMPS3,
  463. .gpu.pmic = &tps659038,
  464. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  465. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  466. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  467. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  468. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  469. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  470. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  471. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  472. .eve.addr = TPS65917_REG_ADDR_SMPS3,
  473. .eve.pmic = &tps659038,
  474. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  475. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  476. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  477. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  478. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  479. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  480. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  481. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  482. .iva.addr = TPS65917_REG_ADDR_SMPS3,
  483. .iva.pmic = &tps659038,
  484. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  485. };
  486. struct vcores_data dra718_volts = {
  487. /*
  488. * In the case of dra71x GPU MPU and CORE
  489. * are all powered up by BUCK0 of LP873X PMIC
  490. */
  491. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  492. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  493. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  494. .mpu.addr = LP873X_REG_ADDR_BUCK0,
  495. .mpu.pmic = &lp8733,
  496. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  497. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  498. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  499. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  500. .core.addr = LP873X_REG_ADDR_BUCK0,
  501. .core.pmic = &lp8733,
  502. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  503. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  504. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  505. .gpu.addr = LP873X_REG_ADDR_BUCK0,
  506. .gpu.pmic = &lp8733,
  507. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  508. /*
  509. * The DSPEVE and IVA rails are grouped on DRA71x-evm
  510. * and are powered by BUCK1 of LP873X PMIC
  511. */
  512. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  513. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  514. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  515. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  516. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  517. .eve.addr = LP873X_REG_ADDR_BUCK1,
  518. .eve.pmic = &lp8733,
  519. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  520. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  521. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  522. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  523. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  524. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  525. .iva.addr = LP873X_REG_ADDR_BUCK1,
  526. .iva.pmic = &lp8733,
  527. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  528. };
  529. int get_voltrail_opp(int rail_offset)
  530. {
  531. int opp;
  532. switch (rail_offset) {
  533. case VOLT_MPU:
  534. opp = DRA7_MPU_OPP;
  535. /* DRA71x supports only OPP_NOM for MPU */
  536. if (board_is_dra71x_evm())
  537. opp = OPP_NOM;
  538. break;
  539. case VOLT_CORE:
  540. opp = DRA7_CORE_OPP;
  541. /* DRA71x supports only OPP_NOM for CORE */
  542. if (board_is_dra71x_evm())
  543. opp = OPP_NOM;
  544. break;
  545. case VOLT_GPU:
  546. opp = DRA7_GPU_OPP;
  547. /* DRA71x supports only OPP_NOM for GPU */
  548. if (board_is_dra71x_evm())
  549. opp = OPP_NOM;
  550. break;
  551. case VOLT_EVE:
  552. opp = DRA7_DSPEVE_OPP;
  553. /*
  554. * DRA71x does not support OPP_OD for EVE.
  555. * If OPP_OD is selected by menuconfig, fallback
  556. * to OPP_NOM.
  557. */
  558. if (board_is_dra71x_evm() && opp == OPP_OD)
  559. opp = OPP_NOM;
  560. break;
  561. case VOLT_IVA:
  562. opp = DRA7_IVA_OPP;
  563. /*
  564. * DRA71x does not support OPP_OD for IVA.
  565. * If OPP_OD is selected by menuconfig, fallback
  566. * to OPP_NOM.
  567. */
  568. if (board_is_dra71x_evm() && opp == OPP_OD)
  569. opp = OPP_NOM;
  570. break;
  571. default:
  572. opp = OPP_NOM;
  573. }
  574. return opp;
  575. }
  576. /**
  577. * @brief board_init
  578. *
  579. * @return 0
  580. */
  581. int board_init(void)
  582. {
  583. gpmc_init();
  584. gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  585. return 0;
  586. }
  587. int dram_init_banksize(void)
  588. {
  589. u64 ram_size;
  590. ram_size = board_ti_get_emif_size();
  591. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  592. gd->bd->bi_dram[0].size = get_effective_memsize();
  593. if (ram_size > CONFIG_MAX_MEM_MAPPED) {
  594. gd->bd->bi_dram[1].start = 0x200000000;
  595. gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
  596. }
  597. return 0;
  598. }
  599. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  600. static int device_okay(const char *path)
  601. {
  602. int node;
  603. node = fdt_path_offset(gd->fdt_blob, path);
  604. if (node < 0)
  605. return 0;
  606. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  607. }
  608. #endif
  609. int board_late_init(void)
  610. {
  611. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  612. char *name = "unknown";
  613. if (is_dra72x()) {
  614. if (board_is_dra72x_revc_or_later())
  615. name = "dra72x-revc";
  616. else if (board_is_dra71x_evm())
  617. name = "dra71x";
  618. else
  619. name = "dra72x";
  620. } else if (is_dra76x_abz()) {
  621. name = "dra76x_abz";
  622. } else if (is_dra76x_acd()) {
  623. name = "dra76x_acd";
  624. } else {
  625. name = "dra7xx";
  626. }
  627. set_board_info_env(name);
  628. /*
  629. * Default FIT boot on HS devices. Non FIT images are not allowed
  630. * on HS devices.
  631. */
  632. if (get_device_type() == HS_DEVICE)
  633. env_set("boot_fit", "1");
  634. omap_die_id_serial();
  635. omap_set_fastboot_vars();
  636. /*
  637. * Hook the LDO1 regulator to EN pin. This applies only to LP8733
  638. * Rest all regulators are hooked to EN Pin at reset.
  639. */
  640. if (board_is_dra71x_evm())
  641. palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
  642. #endif
  643. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  644. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  645. enable_usb_clocks(0);
  646. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  647. enable_usb_clocks(1);
  648. #endif
  649. return 0;
  650. }
  651. #ifdef CONFIG_SPL_BUILD
  652. void do_board_detect(void)
  653. {
  654. int rc;
  655. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  656. CONFIG_EEPROM_CHIP_ADDRESS);
  657. if (rc)
  658. printf("ti_i2c_eeprom_init failed %d\n", rc);
  659. }
  660. #else
  661. void do_board_detect(void)
  662. {
  663. char *bname = NULL;
  664. int rc;
  665. rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
  666. CONFIG_EEPROM_CHIP_ADDRESS);
  667. if (rc)
  668. printf("ti_i2c_eeprom_init failed %d\n", rc);
  669. if (board_is_dra74x_evm()) {
  670. bname = "DRA74x EVM";
  671. } else if (board_is_dra72x_evm()) {
  672. bname = "DRA72x EVM";
  673. } else if (board_is_dra71x_evm()) {
  674. bname = "DRA71x EVM";
  675. } else if (board_is_dra76x_evm()) {
  676. bname = "DRA76x EVM";
  677. } else {
  678. /* If EEPROM is not populated */
  679. if (is_dra72x())
  680. bname = "DRA72x EVM";
  681. else
  682. bname = "DRA74x EVM";
  683. }
  684. if (bname)
  685. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  686. "Board: %s REV %s\n", bname, board_ti_get_rev());
  687. }
  688. #endif /* CONFIG_SPL_BUILD */
  689. void vcores_init(void)
  690. {
  691. if (board_is_dra74x_evm()) {
  692. *omap_vcores = &dra752_volts;
  693. } else if (board_is_dra72x_evm()) {
  694. *omap_vcores = &dra722_volts;
  695. } else if (board_is_dra71x_evm()) {
  696. *omap_vcores = &dra718_volts;
  697. } else if (board_is_dra76x_evm()) {
  698. *omap_vcores = &dra76x_volts;
  699. } else {
  700. /* If EEPROM is not populated */
  701. if (is_dra72x())
  702. *omap_vcores = &dra722_volts;
  703. else
  704. *omap_vcores = &dra752_volts;
  705. }
  706. }
  707. void set_muxconf_regs(void)
  708. {
  709. do_set_mux32((*ctrl)->control_padconf_core_base,
  710. early_padconf, ARRAY_SIZE(early_padconf));
  711. }
  712. #if defined(CONFIG_NAND)
  713. static int nand_sw_detect(void)
  714. {
  715. int rc;
  716. uchar data[2];
  717. struct udevice *dev;
  718. rc = i2c_get_chip_for_busnum(NAND_PCF8575_I2C_BUS_NUM,
  719. NAND_PCF8575_ADDR, 0, &dev);
  720. if (rc)
  721. return -1;
  722. rc = dm_i2c_read(dev, 0, (uint8_t *)&data, sizeof(data));
  723. if (rc)
  724. return -1;
  725. /* We are only interested in P10 and P11 on PCF8575 which is equal to
  726. * bits 8 and 9.
  727. */
  728. data[1] = data[1] & 0x3;
  729. /* Ensure only P11 is set and P10 is cleared. This ensures only
  730. * NAND (P10) is configured and not NOR (P11) which are both low
  731. * true signals. NAND and NOR settings should not be enabled at
  732. * the same time.
  733. */
  734. if (data[1] == 0x2)
  735. return 0;
  736. return -1;
  737. }
  738. #else
  739. int nand_sw_detect(void)
  740. {
  741. return -1;
  742. }
  743. #endif
  744. #ifdef CONFIG_IODELAY_RECALIBRATION
  745. void recalibrate_iodelay(void)
  746. {
  747. struct pad_conf_entry const *pads, *delta_pads = NULL;
  748. struct iodelay_cfg_entry const *iodelay;
  749. int npads, niodelays, delta_npads = 0;
  750. int ret;
  751. switch (omap_revision()) {
  752. case DRA722_ES1_0:
  753. case DRA722_ES2_0:
  754. case DRA722_ES2_1:
  755. pads = dra72x_core_padconf_array_common;
  756. npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
  757. if (board_is_dra71x_evm()) {
  758. pads = dra71x_core_padconf_array;
  759. npads = ARRAY_SIZE(dra71x_core_padconf_array);
  760. iodelay = dra71_iodelay_cfg_array;
  761. niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
  762. /* If SW8 on the EVM is set to enable NAND then
  763. * overwrite the pins used by VOUT3 with NAND.
  764. */
  765. if (!nand_sw_detect()) {
  766. delta_pads = dra71x_nand_padconf_array;
  767. delta_npads =
  768. ARRAY_SIZE(dra71x_nand_padconf_array);
  769. } else {
  770. delta_pads = dra71x_vout3_padconf_array;
  771. delta_npads =
  772. ARRAY_SIZE(dra71x_vout3_padconf_array);
  773. }
  774. } else if (board_is_dra72x_revc_or_later()) {
  775. delta_pads = dra72x_rgmii_padconf_array_revc;
  776. delta_npads =
  777. ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
  778. iodelay = dra72_iodelay_cfg_array_revc;
  779. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
  780. } else {
  781. delta_pads = dra72x_rgmii_padconf_array_revb;
  782. delta_npads =
  783. ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
  784. iodelay = dra72_iodelay_cfg_array_revb;
  785. niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
  786. }
  787. break;
  788. case DRA752_ES1_0:
  789. case DRA752_ES1_1:
  790. pads = dra74x_core_padconf_array;
  791. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  792. iodelay = dra742_es1_1_iodelay_cfg_array;
  793. niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
  794. break;
  795. case DRA762_ACD_ES1_0:
  796. case DRA762_ES1_0:
  797. pads = dra76x_core_padconf_array;
  798. npads = ARRAY_SIZE(dra76x_core_padconf_array);
  799. iodelay = dra76x_es1_0_iodelay_cfg_array;
  800. niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
  801. break;
  802. default:
  803. case DRA752_ES2_0:
  804. case DRA762_ABZ_ES1_0:
  805. pads = dra74x_core_padconf_array;
  806. npads = ARRAY_SIZE(dra74x_core_padconf_array);
  807. iodelay = dra742_es2_0_iodelay_cfg_array;
  808. niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
  809. /* Setup port1 and port2 for rgmii with 'no-id' mode */
  810. clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
  811. RGMII1_ID_MODE_N_MASK);
  812. break;
  813. }
  814. /* Setup I/O isolation */
  815. ret = __recalibrate_iodelay_start();
  816. if (ret)
  817. goto err;
  818. /* Do the muxing here */
  819. do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
  820. /* Now do the weird minor deltas that should be safe */
  821. if (delta_npads)
  822. do_set_mux32((*ctrl)->control_padconf_core_base,
  823. delta_pads, delta_npads);
  824. if (is_dra76x())
  825. /* Set mux for MCAN instead of DCAN1 */
  826. clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
  827. MCAN_SEL_ALT_MASK, MCAN_SEL);
  828. /* Setup IOdelay configuration */
  829. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
  830. err:
  831. /* Closeup.. remove isolation */
  832. __recalibrate_iodelay_end(ret);
  833. }
  834. #endif
  835. #if defined(CONFIG_MMC)
  836. int board_mmc_init(bd_t *bis)
  837. {
  838. omap_mmc_init(0, 0, 0, -1, -1);
  839. omap_mmc_init(1, 0, 0, -1, -1);
  840. return 0;
  841. }
  842. void board_mmc_poweron_ldo(uint voltage)
  843. {
  844. if (board_is_dra71x_evm()) {
  845. if (voltage == LDO_VOLT_3V0)
  846. voltage = 0x19;
  847. else if (voltage == LDO_VOLT_1V8)
  848. voltage = 0xa;
  849. lp873x_mmc1_poweron_ldo(voltage);
  850. } else if (board_is_dra76x_evm()) {
  851. palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage);
  852. } else {
  853. palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
  854. }
  855. }
  856. static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = {
  857. .hw_rev = "rev11",
  858. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  859. MMC_CAP(UHS_SDR104),
  860. .max_freq = 96000000,
  861. };
  862. static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = {
  863. .hw_rev = "rev11",
  864. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  865. MMC_CAP(UHS_SDR104) |
  866. MMC_CAP(UHS_SDR50),
  867. .max_freq = 48000000,
  868. };
  869. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  870. {
  871. switch (omap_revision()) {
  872. case DRA752_ES1_0:
  873. case DRA752_ES1_1:
  874. if (addr == OMAP_HSMMC1_BASE)
  875. return &dra7x_es1_1_mmc1_fixups;
  876. else
  877. return &dra7x_es1_1_mmc23_fixups;
  878. default:
  879. return NULL;
  880. }
  881. }
  882. #endif
  883. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  884. int spl_start_uboot(void)
  885. {
  886. /* break into full u-boot on 'c' */
  887. if (serial_tstc() && serial_getc() == 'c')
  888. return 1;
  889. #ifdef CONFIG_SPL_ENV_SUPPORT
  890. env_init();
  891. env_load();
  892. if (env_get_yesno("boot_os") != 1)
  893. return 1;
  894. #endif
  895. return 0;
  896. }
  897. #endif
  898. #ifdef CONFIG_DRIVER_TI_CPSW
  899. extern u32 *const omap_si_rev;
  900. static void cpsw_control(int enabled)
  901. {
  902. /* VTP can be added here */
  903. return;
  904. }
  905. static struct cpsw_slave_data cpsw_slaves[] = {
  906. {
  907. .slave_reg_ofs = 0x208,
  908. .sliver_reg_ofs = 0xd80,
  909. .phy_addr = 2,
  910. },
  911. {
  912. .slave_reg_ofs = 0x308,
  913. .sliver_reg_ofs = 0xdc0,
  914. .phy_addr = 3,
  915. },
  916. };
  917. static struct cpsw_platform_data cpsw_data = {
  918. .mdio_base = CPSW_MDIO_BASE,
  919. .cpsw_base = CPSW_BASE,
  920. .mdio_div = 0xff,
  921. .channels = 8,
  922. .cpdma_reg_ofs = 0x800,
  923. .slaves = 2,
  924. .slave_data = cpsw_slaves,
  925. .ale_reg_ofs = 0xd00,
  926. .ale_entries = 1024,
  927. .host_port_reg_ofs = 0x108,
  928. .hw_stats_reg_ofs = 0x900,
  929. .bd_ram_ofs = 0x2000,
  930. .mac_control = (1 << 5),
  931. .control = cpsw_control,
  932. .host_port_num = 0,
  933. .version = CPSW_CTRL_VERSION_2,
  934. };
  935. int board_eth_init(bd_t *bis)
  936. {
  937. int ret;
  938. uint8_t mac_addr[6];
  939. uint32_t mac_hi, mac_lo;
  940. uint32_t ctrl_val;
  941. /* try reading mac address from efuse */
  942. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  943. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  944. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  945. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  946. mac_addr[2] = mac_hi & 0xFF;
  947. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  948. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  949. mac_addr[5] = mac_lo & 0xFF;
  950. if (!env_get("ethaddr")) {
  951. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  952. if (is_valid_ethaddr(mac_addr))
  953. eth_env_set_enetaddr("ethaddr", mac_addr);
  954. }
  955. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  956. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  957. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  958. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  959. mac_addr[2] = mac_hi & 0xFF;
  960. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  961. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  962. mac_addr[5] = mac_lo & 0xFF;
  963. if (!env_get("eth1addr")) {
  964. if (is_valid_ethaddr(mac_addr))
  965. eth_env_set_enetaddr("eth1addr", mac_addr);
  966. }
  967. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  968. ctrl_val |= 0x22;
  969. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  970. if (*omap_si_rev == DRA722_ES1_0)
  971. cpsw_data.active_slave = 1;
  972. if (board_is_dra72x_revc_or_later()) {
  973. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  974. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
  975. }
  976. ret = cpsw_register(&cpsw_data);
  977. if (ret < 0)
  978. printf("Error %d registering CPSW switch\n", ret);
  979. return ret;
  980. }
  981. #endif
  982. #ifdef CONFIG_BOARD_EARLY_INIT_F
  983. /* VTT regulator enable */
  984. static inline void vtt_regulator_enable(void)
  985. {
  986. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  987. return;
  988. /* Do not enable VTT for DRA722 or DRA76x */
  989. if (is_dra72x() || is_dra76x())
  990. return;
  991. /*
  992. * EVM Rev G and later use gpio7_11 for DDR3 termination.
  993. * This is safe enough to do on older revs.
  994. */
  995. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  996. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  997. }
  998. int board_early_init_f(void)
  999. {
  1000. vtt_regulator_enable();
  1001. return 0;
  1002. }
  1003. #endif
  1004. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  1005. int ft_board_setup(void *blob, bd_t *bd)
  1006. {
  1007. ft_cpu_setup(blob, bd);
  1008. return 0;
  1009. }
  1010. #endif
  1011. #ifdef CONFIG_SPL_LOAD_FIT
  1012. int board_fit_config_name_match(const char *name)
  1013. {
  1014. if (is_dra72x()) {
  1015. if (board_is_dra71x_evm()) {
  1016. if (!strcmp(name, "dra71-evm"))
  1017. return 0;
  1018. }else if(board_is_dra72x_revc_or_later()) {
  1019. if (!strcmp(name, "dra72-evm-revc"))
  1020. return 0;
  1021. } else if (!strcmp(name, "dra72-evm")) {
  1022. return 0;
  1023. }
  1024. } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) {
  1025. return 0;
  1026. } else if (!is_dra72x() && !is_dra76x_acd() &&
  1027. !strcmp(name, "dra7-evm")) {
  1028. return 0;
  1029. }
  1030. return -1;
  1031. }
  1032. #endif
  1033. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  1034. int fastboot_set_reboot_flag(void)
  1035. {
  1036. printf("Setting reboot to fastboot flag ...\n");
  1037. env_set("dofastboot", "1");
  1038. env_save();
  1039. return 0;
  1040. }
  1041. #endif
  1042. #ifdef CONFIG_TI_SECURE_DEVICE
  1043. void board_fit_image_post_process(void **p_image, size_t *p_size)
  1044. {
  1045. secure_boot_verify_image(p_image, p_size);
  1046. }
  1047. void board_tee_image_process(ulong tee_image, size_t tee_size)
  1048. {
  1049. secure_tee_install((u32)tee_image);
  1050. }
  1051. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  1052. #endif