board.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
  4. *
  5. * Author: Felipe Balbi <balbi@ti.com>
  6. *
  7. * Based on board/ti/dra7xx/evm.c
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <palmas.h>
  12. #include <sata.h>
  13. #include <serial.h>
  14. #include <usb.h>
  15. #include <asm/omap_common.h>
  16. #include <asm/omap_sec_common.h>
  17. #include <asm/emif.h>
  18. #include <asm/gpio.h>
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/dra7xx_iodelay.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/sata.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/arch/omap.h>
  27. #include <usb.h>
  28. #include <linux/usb/gadget.h>
  29. #include <dwc3-uboot.h>
  30. #include <dwc3-omap-uboot.h>
  31. #include <ti-usb-phy-uboot.h>
  32. #include <mmc.h>
  33. #include <dm/uclass.h>
  34. #include "../common/board_detect.h"
  35. #include "mux_data.h"
  36. #define board_is_x15() board_ti_is("BBRDX15_")
  37. #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
  38. !strncmp("B.10", board_ti_get_rev(), 3))
  39. #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
  40. !strncmp("C.00", board_ti_get_rev(), 3))
  41. #define board_is_am572x_evm() board_ti_is("AM572PM_")
  42. #define board_is_am572x_evm_reva3() \
  43. (board_ti_is("AM572PM_") && \
  44. !strncmp("A.30", board_ti_get_rev(), 3))
  45. #define board_is_am574x_idk() board_ti_is("AM574IDK")
  46. #define board_is_am572x_idk() board_ti_is("AM572IDK")
  47. #define board_is_am571x_idk() board_ti_is("AM571IDK")
  48. #ifdef CONFIG_DRIVER_TI_CPSW
  49. #include <cpsw.h>
  50. #endif
  51. DECLARE_GLOBAL_DATA_PTR;
  52. #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
  53. /* GPIO 7_11 */
  54. #define GPIO_DDR_VTT_EN 203
  55. /* Touch screen controller to identify the LCD */
  56. #define OSD_TS_FT_BUS_ADDRESS 0
  57. #define OSD_TS_FT_CHIP_ADDRESS 0x38
  58. #define OSD_TS_FT_REG_ID 0xA3
  59. /*
  60. * Touchscreen IDs for various OSD panels
  61. * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
  62. */
  63. /* Used on newer osd101t2587 Panels */
  64. #define OSD_TS_FT_ID_5x46 0x54
  65. /* Used on older osd101t2045 Panels */
  66. #define OSD_TS_FT_ID_5606 0x08
  67. #define SYSINFO_BOARD_NAME_MAX_LEN 45
  68. #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
  69. #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
  70. const struct omap_sysinfo sysinfo = {
  71. "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
  72. };
  73. static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
  74. .dmm_lisa_map_3 = 0x80740300,
  75. .is_ma_present = 0x1
  76. };
  77. static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
  78. .dmm_lisa_map_3 = 0x80640100,
  79. .is_ma_present = 0x1
  80. };
  81. static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
  82. .dmm_lisa_map_2 = 0xc0600200,
  83. .dmm_lisa_map_3 = 0x80600100,
  84. .is_ma_present = 0x1
  85. };
  86. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  87. {
  88. if (board_is_am571x_idk())
  89. *dmm_lisa_regs = &am571x_idk_lisa_regs;
  90. else if (board_is_am574x_idk())
  91. *dmm_lisa_regs = &am574x_idk_lisa_regs;
  92. else
  93. *dmm_lisa_regs = &beagle_x15_lisa_regs;
  94. }
  95. static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
  96. .sdram_config_init = 0x61851b32,
  97. .sdram_config = 0x61851b32,
  98. .sdram_config2 = 0x08000000,
  99. .ref_ctrl = 0x000040F1,
  100. .ref_ctrl_final = 0x00001035,
  101. .sdram_tim1 = 0xcccf36ab,
  102. .sdram_tim2 = 0x308f7fda,
  103. .sdram_tim3 = 0x409f88a8,
  104. .read_idle_ctrl = 0x00050000,
  105. .zq_config = 0x5007190b,
  106. .temp_alert_config = 0x00000000,
  107. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  108. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  109. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  110. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  111. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  112. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  113. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  114. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  115. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  116. .emif_rd_wr_lvl_ctl = 0x00000000,
  117. .emif_rd_wr_exec_thresh = 0x00000305
  118. };
  119. /* Ext phy ctrl regs 1-35 */
  120. static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
  121. 0x10040100,
  122. 0x00910091,
  123. 0x00950095,
  124. 0x009B009B,
  125. 0x009E009E,
  126. 0x00980098,
  127. 0x00340034,
  128. 0x00350035,
  129. 0x00340034,
  130. 0x00310031,
  131. 0x00340034,
  132. 0x007F007F,
  133. 0x007F007F,
  134. 0x007F007F,
  135. 0x007F007F,
  136. 0x007F007F,
  137. 0x00480048,
  138. 0x004A004A,
  139. 0x00520052,
  140. 0x00550055,
  141. 0x00500050,
  142. 0x00000000,
  143. 0x00600020,
  144. 0x40011080,
  145. 0x08102040,
  146. 0x0,
  147. 0x0,
  148. 0x0,
  149. 0x0,
  150. 0x0,
  151. 0x0,
  152. 0x0,
  153. 0x0,
  154. 0x0,
  155. 0x0
  156. };
  157. static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
  158. .sdram_config_init = 0x61851b32,
  159. .sdram_config = 0x61851b32,
  160. .sdram_config2 = 0x08000000,
  161. .ref_ctrl = 0x000040F1,
  162. .ref_ctrl_final = 0x00001035,
  163. .sdram_tim1 = 0xcccf36b3,
  164. .sdram_tim2 = 0x308f7fda,
  165. .sdram_tim3 = 0x407f88a8,
  166. .read_idle_ctrl = 0x00050000,
  167. .zq_config = 0x5007190b,
  168. .temp_alert_config = 0x00000000,
  169. .emif_ddr_phy_ctlr_1_init = 0x0024400b,
  170. .emif_ddr_phy_ctlr_1 = 0x0e24400b,
  171. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  172. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  173. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  174. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  175. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  176. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  177. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  178. .emif_rd_wr_lvl_ctl = 0x00000000,
  179. .emif_rd_wr_exec_thresh = 0x00000305
  180. };
  181. static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
  182. 0x10040100,
  183. 0x00910091,
  184. 0x00950095,
  185. 0x009B009B,
  186. 0x009E009E,
  187. 0x00980098,
  188. 0x00340034,
  189. 0x00350035,
  190. 0x00340034,
  191. 0x00310031,
  192. 0x00340034,
  193. 0x007F007F,
  194. 0x007F007F,
  195. 0x007F007F,
  196. 0x007F007F,
  197. 0x007F007F,
  198. 0x00480048,
  199. 0x004A004A,
  200. 0x00520052,
  201. 0x00550055,
  202. 0x00500050,
  203. 0x00000000,
  204. 0x00600020,
  205. 0x40011080,
  206. 0x08102040,
  207. 0x0,
  208. 0x0,
  209. 0x0,
  210. 0x0,
  211. 0x0,
  212. 0x0,
  213. 0x0,
  214. 0x0,
  215. 0x0,
  216. 0x0
  217. };
  218. static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
  219. .sdram_config_init = 0x61863332,
  220. .sdram_config = 0x61863332,
  221. .sdram_config2 = 0x08000000,
  222. .ref_ctrl = 0x0000514d,
  223. .ref_ctrl_final = 0x0000144a,
  224. .sdram_tim1 = 0xd333887c,
  225. .sdram_tim2 = 0x30b37fe3,
  226. .sdram_tim3 = 0x409f8ad8,
  227. .read_idle_ctrl = 0x00050000,
  228. .zq_config = 0x5007190b,
  229. .temp_alert_config = 0x00000000,
  230. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  231. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  232. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  233. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  234. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  235. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  236. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  237. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  238. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  239. .emif_rd_wr_lvl_ctl = 0x00000000,
  240. .emif_rd_wr_exec_thresh = 0x00000305
  241. };
  242. static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
  243. .sdram_config_init = 0x61863332,
  244. .sdram_config = 0x61863332,
  245. .sdram_config2 = 0x08000000,
  246. .ref_ctrl = 0x0000514d,
  247. .ref_ctrl_final = 0x0000144a,
  248. .sdram_tim1 = 0xd333887c,
  249. .sdram_tim2 = 0x30b37fe3,
  250. .sdram_tim3 = 0x409f8ad8,
  251. .read_idle_ctrl = 0x00050000,
  252. .zq_config = 0x5007190b,
  253. .temp_alert_config = 0x00000000,
  254. .emif_ddr_phy_ctlr_1_init = 0x0024400f,
  255. .emif_ddr_phy_ctlr_1 = 0x0e24400f,
  256. .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
  257. .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  258. .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  259. .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
  260. .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
  261. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  262. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  263. .emif_rd_wr_lvl_ctl = 0x00000000,
  264. .emif_rd_wr_exec_thresh = 0x00000305,
  265. .emif_ecc_ctrl_reg = 0xD0000001,
  266. .emif_ecc_address_range_1 = 0x3FFF0000,
  267. .emif_ecc_address_range_2 = 0x00000000
  268. };
  269. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  270. {
  271. switch (emif_nr) {
  272. case 1:
  273. if (board_is_am571x_idk())
  274. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  275. else if (board_is_am574x_idk())
  276. *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
  277. else
  278. *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
  279. break;
  280. case 2:
  281. if (board_is_am574x_idk())
  282. *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
  283. else
  284. *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
  285. break;
  286. }
  287. }
  288. void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
  289. {
  290. switch (emif_nr) {
  291. case 1:
  292. *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
  293. *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
  294. break;
  295. case 2:
  296. *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
  297. *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
  298. break;
  299. }
  300. }
  301. struct vcores_data beagle_x15_volts = {
  302. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  303. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  304. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  305. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  306. .mpu.pmic = &tps659038,
  307. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  308. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  309. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  310. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  311. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  312. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  313. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  314. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  315. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  316. .eve.pmic = &tps659038,
  317. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  318. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  319. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  320. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  321. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  322. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  323. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  324. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  325. .gpu.addr = TPS659038_REG_ADDR_SMPS45,
  326. .gpu.pmic = &tps659038,
  327. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  328. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  329. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  330. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  331. .core.addr = TPS659038_REG_ADDR_SMPS6,
  332. .core.pmic = &tps659038,
  333. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  334. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  335. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  336. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  337. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  338. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  339. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  340. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  341. .iva.pmic = &tps659038,
  342. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  343. };
  344. struct vcores_data am572x_idk_volts = {
  345. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  346. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  347. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  348. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  349. .mpu.pmic = &tps659038,
  350. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  351. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  352. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  353. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  354. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  355. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  356. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  357. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  358. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  359. .eve.pmic = &tps659038,
  360. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  361. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  362. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  363. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  364. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  365. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  366. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  367. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  368. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  369. .gpu.pmic = &tps659038,
  370. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  371. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  372. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  373. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  374. .core.addr = TPS659038_REG_ADDR_SMPS7,
  375. .core.pmic = &tps659038,
  376. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  377. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  378. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  379. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  380. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  381. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  382. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  383. .iva.addr = TPS659038_REG_ADDR_SMPS8,
  384. .iva.pmic = &tps659038,
  385. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  386. };
  387. struct vcores_data am571x_idk_volts = {
  388. .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
  389. .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
  390. .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  391. .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  392. .mpu.pmic = &tps659038,
  393. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  394. .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
  395. .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
  396. .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
  397. .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
  398. .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
  399. .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
  400. .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  401. .eve.addr = TPS659038_REG_ADDR_SMPS45,
  402. .eve.pmic = &tps659038,
  403. .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  404. .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
  405. .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
  406. .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
  407. .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
  408. .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
  409. .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
  410. .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  411. .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  412. .gpu.pmic = &tps659038,
  413. .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  414. .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
  415. .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
  416. .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  417. .core.addr = TPS659038_REG_ADDR_SMPS7,
  418. .core.pmic = &tps659038,
  419. .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
  420. .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
  421. .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
  422. .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
  423. .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
  424. .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
  425. .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  426. .iva.addr = TPS659038_REG_ADDR_SMPS45,
  427. .iva.pmic = &tps659038,
  428. .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  429. };
  430. int get_voltrail_opp(int rail_offset)
  431. {
  432. int opp;
  433. switch (rail_offset) {
  434. case VOLT_MPU:
  435. opp = DRA7_MPU_OPP;
  436. break;
  437. case VOLT_CORE:
  438. opp = DRA7_CORE_OPP;
  439. break;
  440. case VOLT_GPU:
  441. opp = DRA7_GPU_OPP;
  442. break;
  443. case VOLT_EVE:
  444. opp = DRA7_DSPEVE_OPP;
  445. break;
  446. case VOLT_IVA:
  447. opp = DRA7_IVA_OPP;
  448. break;
  449. default:
  450. opp = OPP_NOM;
  451. }
  452. return opp;
  453. }
  454. #ifdef CONFIG_SPL_BUILD
  455. /* No env to setup for SPL */
  456. static inline void setup_board_eeprom_env(void) { }
  457. /* Override function to read eeprom information */
  458. void do_board_detect(void)
  459. {
  460. int rc;
  461. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  462. CONFIG_EEPROM_CHIP_ADDRESS);
  463. if (rc)
  464. printf("ti_i2c_eeprom_init failed %d\n", rc);
  465. }
  466. #else /* CONFIG_SPL_BUILD */
  467. /* Override function to read eeprom information: actual i2c read done by SPL*/
  468. void do_board_detect(void)
  469. {
  470. char *bname = NULL;
  471. int rc;
  472. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  473. CONFIG_EEPROM_CHIP_ADDRESS);
  474. if (rc)
  475. printf("ti_i2c_eeprom_init failed %d\n", rc);
  476. if (board_is_x15())
  477. bname = "BeagleBoard X15";
  478. else if (board_is_am572x_evm())
  479. bname = "AM572x EVM";
  480. else if (board_is_am574x_idk())
  481. bname = "AM574x IDK";
  482. else if (board_is_am572x_idk())
  483. bname = "AM572x IDK";
  484. else if (board_is_am571x_idk())
  485. bname = "AM571x IDK";
  486. if (bname)
  487. snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
  488. "Board: %s REV %s\n", bname, board_ti_get_rev());
  489. }
  490. static void setup_board_eeprom_env(void)
  491. {
  492. char *name = "beagle_x15";
  493. int rc;
  494. rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  495. CONFIG_EEPROM_CHIP_ADDRESS);
  496. if (rc)
  497. goto invalid_eeprom;
  498. if (board_is_x15()) {
  499. if (board_is_x15_revb1())
  500. name = "beagle_x15_revb1";
  501. else if (board_is_x15_revc())
  502. name = "beagle_x15_revc";
  503. else
  504. name = "beagle_x15";
  505. } else if (board_is_am572x_evm()) {
  506. if (board_is_am572x_evm_reva3())
  507. name = "am57xx_evm_reva3";
  508. else
  509. name = "am57xx_evm";
  510. } else if (board_is_am574x_idk()) {
  511. name = "am574x_idk";
  512. } else if (board_is_am572x_idk()) {
  513. name = "am572x_idk";
  514. } else if (board_is_am571x_idk()) {
  515. name = "am571x_idk";
  516. } else {
  517. printf("Unidentified board claims %s in eeprom header\n",
  518. board_ti_get_name());
  519. }
  520. invalid_eeprom:
  521. set_board_info_env(name);
  522. }
  523. #endif /* CONFIG_SPL_BUILD */
  524. void vcores_init(void)
  525. {
  526. if (board_is_am572x_idk() || board_is_am574x_idk())
  527. *omap_vcores = &am572x_idk_volts;
  528. else if (board_is_am571x_idk())
  529. *omap_vcores = &am571x_idk_volts;
  530. else
  531. *omap_vcores = &beagle_x15_volts;
  532. }
  533. void hw_data_init(void)
  534. {
  535. *prcm = &dra7xx_prcm;
  536. if (is_dra72x())
  537. *dplls_data = &dra72x_dplls;
  538. else if (is_dra76x())
  539. *dplls_data = &dra76x_dplls;
  540. else
  541. *dplls_data = &dra7xx_dplls;
  542. *ctrl = &dra7xx_ctrl;
  543. }
  544. bool am571x_idk_needs_lcd(void)
  545. {
  546. bool needs_lcd;
  547. gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
  548. if (gpio_get_value(GPIO_ETH_LCD))
  549. needs_lcd = false;
  550. else
  551. needs_lcd = true;
  552. gpio_free(GPIO_ETH_LCD);
  553. return needs_lcd;
  554. }
  555. int board_init(void)
  556. {
  557. gpmc_init();
  558. gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
  559. return 0;
  560. }
  561. void am57x_idk_lcd_detect(void)
  562. {
  563. int r = -ENODEV;
  564. char *idk_lcd = "no";
  565. struct udevice *dev;
  566. /* Only valid for IDKs */
  567. if (board_is_x15() || board_is_am572x_evm())
  568. return;
  569. /* Only AM571x IDK has gpio control detect.. so check that */
  570. if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
  571. goto out;
  572. r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
  573. OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
  574. if (r) {
  575. printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
  576. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  577. r);
  578. /* AM572x IDK has no explicit settings for optional LCD kit */
  579. if (board_is_am571x_idk())
  580. printf("%s: Touch screen detect failed: %d!\n",
  581. __func__, r);
  582. goto out;
  583. }
  584. /* Read FT ID */
  585. r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
  586. if (r < 0) {
  587. printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
  588. __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
  589. OSD_TS_FT_REG_ID, r);
  590. goto out;
  591. }
  592. switch (r) {
  593. case OSD_TS_FT_ID_5606:
  594. idk_lcd = "osd101t2045";
  595. break;
  596. case OSD_TS_FT_ID_5x46:
  597. idk_lcd = "osd101t2587";
  598. break;
  599. default:
  600. printf("%s: Unidentifed Touch screen ID 0x%02x\n",
  601. __func__, r);
  602. /* we will let default be "no lcd" */
  603. }
  604. out:
  605. env_set("idk_lcd", idk_lcd);
  606. return;
  607. }
  608. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  609. static int device_okay(const char *path)
  610. {
  611. int node;
  612. node = fdt_path_offset(gd->fdt_blob, path);
  613. if (node < 0)
  614. return 0;
  615. return fdtdec_get_is_enabled(gd->fdt_blob, node);
  616. }
  617. #endif
  618. int board_late_init(void)
  619. {
  620. setup_board_eeprom_env();
  621. u8 val;
  622. struct udevice *dev;
  623. /*
  624. * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
  625. * This is the POWERHOLD-in-Low behavior.
  626. */
  627. palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
  628. /*
  629. * Default FIT boot on HS devices. Non FIT images are not allowed
  630. * on HS devices.
  631. */
  632. if (get_device_type() == HS_DEVICE)
  633. env_set("boot_fit", "1");
  634. /*
  635. * Set the GPIO7 Pad to POWERHOLD. This has higher priority
  636. * over DEV_CTRL.DEV_ON bit. This can be reset in case of
  637. * PMIC Power off. So to be on the safer side set it back
  638. * to POWERHOLD mode irrespective of the current state.
  639. */
  640. palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  641. &val);
  642. val = val | TPS65903X_PAD2_POWERHOLD_MASK;
  643. palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
  644. val);
  645. omap_die_id_serial();
  646. omap_set_fastboot_vars();
  647. am57x_idk_lcd_detect();
  648. /* Just probe the potentially supported cdce913 device */
  649. uclass_get_device(UCLASS_CLK, 0, &dev);
  650. #if !defined(CONFIG_SPL_BUILD)
  651. board_ti_set_ethaddr(2);
  652. #endif
  653. #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
  654. if (device_okay("/ocp/omap_dwc3_1@48880000"))
  655. enable_usb_clocks(0);
  656. if (device_okay("/ocp/omap_dwc3_2@488c0000"))
  657. enable_usb_clocks(1);
  658. #endif
  659. return 0;
  660. }
  661. void set_muxconf_regs(void)
  662. {
  663. do_set_mux32((*ctrl)->control_padconf_core_base,
  664. early_padconf, ARRAY_SIZE(early_padconf));
  665. }
  666. #ifdef CONFIG_IODELAY_RECALIBRATION
  667. void recalibrate_iodelay(void)
  668. {
  669. const struct pad_conf_entry *pconf;
  670. const struct iodelay_cfg_entry *iod, *delta_iod;
  671. int pconf_sz, iod_sz, delta_iod_sz = 0;
  672. int ret;
  673. if (board_is_am572x_idk()) {
  674. pconf = core_padconf_array_essential_am572x_idk;
  675. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
  676. iod = iodelay_cfg_array_am572x_idk;
  677. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
  678. } else if (board_is_am574x_idk()) {
  679. pconf = core_padconf_array_essential_am574x_idk;
  680. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
  681. iod = iodelay_cfg_array_am574x_idk;
  682. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
  683. } else if (board_is_am571x_idk()) {
  684. pconf = core_padconf_array_essential_am571x_idk;
  685. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
  686. iod = iodelay_cfg_array_am571x_idk;
  687. iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
  688. } else {
  689. /* Common for X15/GPEVM */
  690. pconf = core_padconf_array_essential_x15;
  691. pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
  692. /* There never was an SR1.0 X15.. So.. */
  693. if (omap_revision() == DRA752_ES1_1) {
  694. iod = iodelay_cfg_array_x15_sr1_1;
  695. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
  696. } else {
  697. /* Since full production should switch to SR2.0 */
  698. iod = iodelay_cfg_array_x15_sr2_0;
  699. iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
  700. }
  701. }
  702. /* Setup I/O isolation */
  703. ret = __recalibrate_iodelay_start();
  704. if (ret)
  705. goto err;
  706. /* Do the muxing here */
  707. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  708. /* Now do the weird minor deltas that should be safe */
  709. if (board_is_x15() || board_is_am572x_evm()) {
  710. if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
  711. board_is_x15_revc()) {
  712. pconf = core_padconf_array_delta_x15_sr2_0;
  713. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
  714. } else {
  715. pconf = core_padconf_array_delta_x15_sr1_1;
  716. pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
  717. }
  718. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  719. }
  720. if (board_is_am571x_idk()) {
  721. if (am571x_idk_needs_lcd()) {
  722. pconf = core_padconf_array_vout_am571x_idk;
  723. pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
  724. delta_iod = iodelay_cfg_array_am571x_idk_4port;
  725. delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
  726. } else {
  727. pconf = core_padconf_array_icss1eth_am571x_idk;
  728. pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
  729. }
  730. do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
  731. }
  732. /* Setup IOdelay configuration */
  733. ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
  734. if (delta_iod_sz)
  735. ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
  736. delta_iod_sz);
  737. err:
  738. /* Closeup.. remove isolation */
  739. __recalibrate_iodelay_end(ret);
  740. }
  741. #endif
  742. #if defined(CONFIG_MMC)
  743. int board_mmc_init(bd_t *bis)
  744. {
  745. omap_mmc_init(0, 0, 0, -1, -1);
  746. omap_mmc_init(1, 0, 0, -1, -1);
  747. return 0;
  748. }
  749. static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
  750. .hw_rev = "rev11",
  751. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  752. MMC_CAP(UHS_SDR104),
  753. .max_freq = 96000000,
  754. };
  755. static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
  756. .hw_rev = "rev11",
  757. .unsupported_caps = MMC_CAP(MMC_HS_200) |
  758. MMC_CAP(UHS_SDR104) |
  759. MMC_CAP(UHS_SDR50),
  760. .max_freq = 48000000,
  761. };
  762. const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  763. {
  764. switch (omap_revision()) {
  765. case DRA752_ES1_0:
  766. case DRA752_ES1_1:
  767. if (addr == OMAP_HSMMC1_BASE)
  768. return &am57x_es1_1_mmc1_fixups;
  769. else
  770. return &am57x_es1_1_mmc23_fixups;
  771. default:
  772. return NULL;
  773. }
  774. }
  775. #endif
  776. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
  777. int spl_start_uboot(void)
  778. {
  779. /* break into full u-boot on 'c' */
  780. if (serial_tstc() && serial_getc() == 'c')
  781. return 1;
  782. #ifdef CONFIG_SPL_ENV_SUPPORT
  783. env_init();
  784. env_load();
  785. if (env_get_yesno("boot_os") != 1)
  786. return 1;
  787. #endif
  788. return 0;
  789. }
  790. #endif
  791. #ifdef CONFIG_DRIVER_TI_CPSW
  792. /* Delay value to add to calibrated value */
  793. #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
  794. #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
  795. #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
  796. #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
  797. #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
  798. #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
  799. #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
  800. #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
  801. #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
  802. #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
  803. static void cpsw_control(int enabled)
  804. {
  805. /* VTP can be added here */
  806. }
  807. static struct cpsw_slave_data cpsw_slaves[] = {
  808. {
  809. .slave_reg_ofs = 0x208,
  810. .sliver_reg_ofs = 0xd80,
  811. .phy_addr = 1,
  812. },
  813. {
  814. .slave_reg_ofs = 0x308,
  815. .sliver_reg_ofs = 0xdc0,
  816. .phy_addr = 2,
  817. },
  818. };
  819. static struct cpsw_platform_data cpsw_data = {
  820. .mdio_base = CPSW_MDIO_BASE,
  821. .cpsw_base = CPSW_BASE,
  822. .mdio_div = 0xff,
  823. .channels = 8,
  824. .cpdma_reg_ofs = 0x800,
  825. .slaves = 1,
  826. .slave_data = cpsw_slaves,
  827. .ale_reg_ofs = 0xd00,
  828. .ale_entries = 1024,
  829. .host_port_reg_ofs = 0x108,
  830. .hw_stats_reg_ofs = 0x900,
  831. .bd_ram_ofs = 0x2000,
  832. .mac_control = (1 << 5),
  833. .control = cpsw_control,
  834. .host_port_num = 0,
  835. .version = CPSW_CTRL_VERSION_2,
  836. };
  837. static u64 mac_to_u64(u8 mac[6])
  838. {
  839. int i;
  840. u64 addr = 0;
  841. for (i = 0; i < 6; i++) {
  842. addr <<= 8;
  843. addr |= mac[i];
  844. }
  845. return addr;
  846. }
  847. static void u64_to_mac(u64 addr, u8 mac[6])
  848. {
  849. mac[5] = addr;
  850. mac[4] = addr >> 8;
  851. mac[3] = addr >> 16;
  852. mac[2] = addr >> 24;
  853. mac[1] = addr >> 32;
  854. mac[0] = addr >> 40;
  855. }
  856. int board_eth_init(bd_t *bis)
  857. {
  858. int ret;
  859. uint8_t mac_addr[6];
  860. uint32_t mac_hi, mac_lo;
  861. uint32_t ctrl_val;
  862. int i;
  863. u64 mac1, mac2;
  864. u8 mac_addr1[6], mac_addr2[6];
  865. int num_macs;
  866. /* try reading mac address from efuse */
  867. mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
  868. mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
  869. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  870. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  871. mac_addr[2] = mac_hi & 0xFF;
  872. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  873. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  874. mac_addr[5] = mac_lo & 0xFF;
  875. if (!env_get("ethaddr")) {
  876. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  877. if (is_valid_ethaddr(mac_addr))
  878. eth_env_set_enetaddr("ethaddr", mac_addr);
  879. }
  880. mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
  881. mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
  882. mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
  883. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  884. mac_addr[2] = mac_hi & 0xFF;
  885. mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
  886. mac_addr[4] = (mac_lo & 0xFF00) >> 8;
  887. mac_addr[5] = mac_lo & 0xFF;
  888. if (!env_get("eth1addr")) {
  889. if (is_valid_ethaddr(mac_addr))
  890. eth_env_set_enetaddr("eth1addr", mac_addr);
  891. }
  892. ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
  893. ctrl_val |= 0x22;
  894. writel(ctrl_val, (*ctrl)->control_core_control_io1);
  895. /* The phy address for the AM57xx IDK are different than x15 */
  896. if (board_is_am572x_idk() || board_is_am571x_idk() ||
  897. board_is_am574x_idk()) {
  898. cpsw_data.slave_data[0].phy_addr = 0;
  899. cpsw_data.slave_data[1].phy_addr = 1;
  900. }
  901. ret = cpsw_register(&cpsw_data);
  902. if (ret < 0)
  903. printf("Error %d registering CPSW switch\n", ret);
  904. /*
  905. * Export any Ethernet MAC addresses from EEPROM.
  906. * On AM57xx the 2 MAC addresses define the address range
  907. */
  908. board_ti_get_eth_mac_addr(0, mac_addr1);
  909. board_ti_get_eth_mac_addr(1, mac_addr2);
  910. if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
  911. mac1 = mac_to_u64(mac_addr1);
  912. mac2 = mac_to_u64(mac_addr2);
  913. /* must contain an address range */
  914. num_macs = mac2 - mac1 + 1;
  915. /* <= 50 to protect against user programming error */
  916. if (num_macs > 0 && num_macs <= 50) {
  917. for (i = 0; i < num_macs; i++) {
  918. u64_to_mac(mac1 + i, mac_addr);
  919. if (is_valid_ethaddr(mac_addr)) {
  920. eth_env_set_enetaddr_by_index("eth",
  921. i + 2,
  922. mac_addr);
  923. }
  924. }
  925. }
  926. }
  927. return ret;
  928. }
  929. #endif
  930. #ifdef CONFIG_BOARD_EARLY_INIT_F
  931. /* VTT regulator enable */
  932. static inline void vtt_regulator_enable(void)
  933. {
  934. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  935. return;
  936. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  937. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  938. }
  939. int board_early_init_f(void)
  940. {
  941. vtt_regulator_enable();
  942. return 0;
  943. }
  944. #endif
  945. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  946. int ft_board_setup(void *blob, bd_t *bd)
  947. {
  948. ft_cpu_setup(blob, bd);
  949. return 0;
  950. }
  951. #endif
  952. #ifdef CONFIG_SPL_LOAD_FIT
  953. int board_fit_config_name_match(const char *name)
  954. {
  955. if (board_is_x15()) {
  956. if (board_is_x15_revb1()) {
  957. if (!strcmp(name, "am57xx-beagle-x15-revb1"))
  958. return 0;
  959. } else if (board_is_x15_revc()) {
  960. if (!strcmp(name, "am57xx-beagle-x15-revc"))
  961. return 0;
  962. } else if (!strcmp(name, "am57xx-beagle-x15")) {
  963. return 0;
  964. }
  965. } else if (board_is_am572x_evm() &&
  966. !strcmp(name, "am57xx-beagle-x15")) {
  967. return 0;
  968. } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
  969. return 0;
  970. } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
  971. return 0;
  972. } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
  973. return 0;
  974. }
  975. return -1;
  976. }
  977. #endif
  978. #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
  979. int fastboot_set_reboot_flag(void)
  980. {
  981. printf("Setting reboot to fastboot flag ...\n");
  982. env_set("dofastboot", "1");
  983. env_save();
  984. return 0;
  985. }
  986. #endif
  987. #ifdef CONFIG_TI_SECURE_DEVICE
  988. void board_fit_image_post_process(void **p_image, size_t *p_size)
  989. {
  990. secure_boot_verify_image(p_image, p_size);
  991. }
  992. void board_tee_image_process(ulong tee_image, size_t tee_size)
  993. {
  994. secure_tee_install((u32)tee_image);
  995. }
  996. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
  997. #endif