board.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <env.h>
  9. #include <serial.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/ddr_defs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <i2c.h>
  16. #include <phy.h>
  17. #include <cpsw.h>
  18. #include "board.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  21. #if defined(CONFIG_SPL_BUILD)
  22. /* DDR3 RAM timings */
  23. static const struct ddr_data ddr3_data = {
  24. .datardsratio0 = MT41K128MJT187E_RD_DQS,
  25. .datawdsratio0 = MT41K128MJT187E_WR_DQS,
  26. .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
  27. .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
  28. };
  29. static const struct cmd_control ddr3_cmd_ctrl_data = {
  30. .cmd0csratio = MT41K128MJT187E_RATIO,
  31. .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  32. .cmd1csratio = MT41K128MJT187E_RATIO,
  33. .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  34. .cmd2csratio = MT41K128MJT187E_RATIO,
  35. .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
  36. };
  37. static struct emif_regs ddr3_emif_reg_data = {
  38. .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
  39. .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
  40. .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
  41. .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
  42. .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
  43. .zq_config = MT41K128MJT187E_ZQ_CFG,
  44. .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
  45. PHY_EN_DYN_PWRDN,
  46. };
  47. const struct ctrl_ioregs ddr3_ioregs = {
  48. .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
  49. .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
  50. .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
  51. .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
  52. .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
  53. };
  54. #ifdef CONFIG_SPL_OS_BOOT
  55. int spl_start_uboot(void)
  56. {
  57. /* break into full u-boot on 'c' */
  58. return serial_tstc() && serial_getc() == 'c';
  59. }
  60. #endif
  61. #define OSC (V_OSCK/1000000)
  62. const struct dpll_params dpll_ddr_266 = {
  63. 266, OSC-1, 1, -1, -1, -1, -1};
  64. const struct dpll_params dpll_ddr_303 = {
  65. 303, OSC-1, 1, -1, -1, -1, -1};
  66. const struct dpll_params dpll_ddr_400 = {
  67. 400, OSC-1, 1, -1, -1, -1, -1};
  68. void am33xx_spl_board_init(void)
  69. {
  70. /*
  71. * The pengwyn board uses the TPS650250 PMIC without I2C
  72. * interface and will output the following fixed voltages:
  73. * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
  74. * VLDO1=1V8 (IO) VLDO2=1V8(IO)
  75. * Vcore=1V1 is fixed, generated by TPS62231
  76. */
  77. /* Get the frequency */
  78. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  79. /* Set CORE Frequencies to OPP100 */
  80. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  81. /* 720MHz cpu, this might change on newer board revisions */
  82. dpll_mpu_opp100.m = MPUPLL_M_720;
  83. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  84. }
  85. const struct dpll_params *get_dpll_ddr_params(void)
  86. {
  87. /* future configs can return other clock settings */
  88. return &dpll_ddr_303;
  89. }
  90. void set_uart_mux_conf(void)
  91. {
  92. enable_uart0_pin_mux();
  93. }
  94. void set_mux_conf_regs(void)
  95. {
  96. enable_board_pin_mux();
  97. }
  98. void sdram_init(void)
  99. {
  100. config_ddr(303, &ddr3_ioregs, &ddr3_data,
  101. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  102. }
  103. #endif /* if CONFIG_SPL_BUILD */
  104. /*
  105. * Basic board specific setup. Pinmux has been handled already.
  106. */
  107. int board_init(void)
  108. {
  109. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  110. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  111. gpmc_init();
  112. return 0;
  113. }
  114. #ifdef CONFIG_DRIVER_TI_CPSW
  115. static void cpsw_control(int enabled)
  116. {
  117. /* VTP can be added here */
  118. return;
  119. }
  120. static struct cpsw_slave_data cpsw_slaves[] = {
  121. {
  122. .slave_reg_ofs = 0x208,
  123. .sliver_reg_ofs = 0xd80,
  124. .phy_addr = 1,
  125. .phy_if = PHY_INTERFACE_MODE_MII,
  126. },
  127. };
  128. static struct cpsw_platform_data cpsw_data = {
  129. .mdio_base = CPSW_MDIO_BASE,
  130. .cpsw_base = CPSW_BASE,
  131. .mdio_div = 0xff,
  132. .channels = 8,
  133. .cpdma_reg_ofs = 0x800,
  134. .slaves = 1,
  135. .slave_data = cpsw_slaves,
  136. .ale_reg_ofs = 0xd00,
  137. .ale_entries = 1024,
  138. .host_port_reg_ofs = 0x108,
  139. .hw_stats_reg_ofs = 0x900,
  140. .bd_ram_ofs = 0x2000,
  141. .mac_control = (1 << 5),
  142. .control = cpsw_control,
  143. .host_port_num = 0,
  144. .version = CPSW_CTRL_VERSION_2,
  145. };
  146. int board_eth_init(bd_t *bis)
  147. {
  148. int rv, n = 0;
  149. uint8_t mac_addr[6];
  150. uint32_t mac_hi, mac_lo;
  151. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  152. printf("<ethaddr> not set. Reading from E-fuse\n");
  153. /* try reading mac address from efuse */
  154. mac_lo = readl(&cdev->macid0l);
  155. mac_hi = readl(&cdev->macid0h);
  156. mac_addr[0] = mac_hi & 0xFF;
  157. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  158. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  159. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  160. mac_addr[4] = mac_lo & 0xFF;
  161. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  162. if (is_valid_ethaddr(mac_addr))
  163. eth_env_set_enetaddr("ethaddr", mac_addr);
  164. else
  165. return n;
  166. }
  167. writel(MII_MODE_ENABLE, &cdev->miisel);
  168. rv = cpsw_register(&cpsw_data);
  169. if (rv < 0)
  170. printf("Error %d registering CPSW switch\n", rv);
  171. else
  172. n += rv;
  173. return n;
  174. }
  175. #endif /* if CONFIG_DRIVER_TI_CPSW */