omap3logic.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011
  4. * Logic Product Development <www.logicpd.com>
  5. *
  6. * Author :
  7. * Peter Barada <peter.barada@logicpd.com>
  8. *
  9. * Derived from Beagle Board and 3430 SDP code by
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <ns16550.h>
  16. #include <netdev.h>
  17. #include <flash.h>
  18. #include <nand.h>
  19. #include <i2c.h>
  20. #include <serial.h>
  21. #include <twl4030.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/mux.h>
  25. #include <asm/arch/mem.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/gpio.h>
  28. #include <asm/omap_mmc.h>
  29. #include <asm/mach-types.h>
  30. #include <linux/mtd/rawnand.h>
  31. #include <asm/omap_musb.h>
  32. #include <linux/errno.h>
  33. #include <linux/usb/ch9.h>
  34. #include <linux/usb/gadget.h>
  35. #include <linux/usb/musb.h>
  36. #include "omap3logic.h"
  37. #ifdef CONFIG_USB_EHCI_HCD
  38. #include <usb.h>
  39. #include <asm/ehci-omap.h>
  40. #endif
  41. DECLARE_GLOBAL_DATA_PTR;
  42. #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
  43. #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
  44. #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
  45. #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
  46. #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
  47. #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
  48. #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
  49. #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
  50. #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
  51. #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
  52. #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
  53. #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
  54. #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
  55. #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
  56. #ifdef CONFIG_SPL_OS_BOOT
  57. int spl_start_uboot(void)
  58. {
  59. /* break into full u-boot on 'c' */
  60. return serial_tstc() && serial_getc() == 'c';
  61. }
  62. #endif
  63. #if defined(CONFIG_SPL_BUILD)
  64. /*
  65. * Routine: get_board_mem_timings
  66. * Description: If we use SPL then there is no x-loader nor config header
  67. * so we have to setup the DDR timings ourself on the first bank. This
  68. * provides the timing values back to the function that configures
  69. * the memory.
  70. */
  71. void get_board_mem_timings(struct board_sdrc_timings *timings)
  72. {
  73. timings->mr = MICRON_V_MR_165;
  74. if (get_cpu_family() == CPU_OMAP36XX) {
  75. /* 200 MHz works for OMAP36/DM37 */
  76. /* 256MB DDR */
  77. timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  78. timings->ctrla = MICRON_V_ACTIMA_200;
  79. timings->ctrlb = MICRON_V_ACTIMB_200;
  80. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  81. } else {
  82. /* 165 MHz works for OMAP35 */
  83. timings->mcfg = MICRON_V_MCFG_165(256 << 20);
  84. timings->ctrla = MICRON_V_ACTIMA_165;
  85. timings->ctrlb = MICRON_V_ACTIMB_165;
  86. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  87. }
  88. }
  89. #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
  90. #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
  91. #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
  92. void spl_board_prepare_for_linux(void)
  93. {
  94. /* The Micron NAND starts locked which
  95. * prohibits mounting the NAND as RW
  96. * The following commands are what unlocks
  97. * the NAND to become RW Falcon Mode does not
  98. * have as many smarts as U-Boot, but Logic PD
  99. * only makes NAND with 512MB so these hard coded
  100. * values should work for all current models
  101. */
  102. writeb(0x70, GPMC_NAND_COMMAND_0);
  103. writeb(-1, GPMC_NAND_DATA_0);
  104. writeb(0x7a, GPMC_NAND_COMMAND_0);
  105. writeb(0x00, GPMC_NAND_ADDRESS_0);
  106. writeb(0x00, GPMC_NAND_ADDRESS_0);
  107. writeb(0x00, GPMC_NAND_ADDRESS_0);
  108. writeb(-1, GPMC_NAND_COMMAND_0);
  109. /* Begin address 0 */
  110. writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
  111. writeb(0x00, GPMC_NAND_ADDRESS_0);
  112. writeb(0x00, GPMC_NAND_ADDRESS_0);
  113. writeb(0x00, GPMC_NAND_ADDRESS_0);
  114. writeb(-1, GPMC_NAND_DATA_0);
  115. /* Ending address at the end of Flash */
  116. writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
  117. writeb(0xc0, GPMC_NAND_ADDRESS_0);
  118. writeb(0xff, GPMC_NAND_ADDRESS_0);
  119. writeb(0x03, GPMC_NAND_ADDRESS_0);
  120. writeb(-1, GPMC_NAND_DATA_0);
  121. writeb(0x79, GPMC_NAND_COMMAND_0);
  122. writeb(-1, GPMC_NAND_DATA_0);
  123. writeb(-1, GPMC_NAND_DATA_0);
  124. }
  125. #endif
  126. /*
  127. * Routine: misc_init_r
  128. * Description: Configure board specific parts
  129. */
  130. int misc_init_r(void)
  131. {
  132. twl4030_power_init();
  133. twl4030_power_mmc_init(0);
  134. omap_die_id_display();
  135. return 0;
  136. }
  137. #if defined(CONFIG_FLASH_CFI_DRIVER)
  138. static const u32 gpmc_dm37_c2nor_config[] = {
  139. LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
  140. LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
  141. LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
  142. LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
  143. LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
  144. LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
  145. LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
  146. };
  147. static const u32 gpmc_omap35_c2nor_config[] = {
  148. LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
  149. LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
  150. LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
  151. LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
  152. LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
  153. LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
  154. LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
  155. };
  156. #endif
  157. /*
  158. * Routine: board_init
  159. * Description: Early hardware init.
  160. */
  161. int board_init(void)
  162. {
  163. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  164. /* boot param addr */
  165. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  166. #if defined(CONFIG_FLASH_CFI_DRIVER)
  167. if (get_cpu_family() == CPU_OMAP36XX) {
  168. /* Enable CS2 for NOR Flash */
  169. enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
  170. 0x10000000, GPMC_SIZE_64M);
  171. } else {
  172. enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
  173. 0x10000000, GPMC_SIZE_64M);
  174. }
  175. #endif
  176. return 0;
  177. }
  178. #ifdef CONFIG_BOARD_LATE_INIT
  179. static void unlock_nand(void)
  180. {
  181. int dev = nand_curr_device;
  182. struct mtd_info *mtd;
  183. mtd = get_nand_dev_by_index(dev);
  184. nand_unlock(mtd, 0, mtd->size, 0);
  185. }
  186. int board_late_init(void)
  187. {
  188. #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
  189. unlock_nand();
  190. #endif
  191. return 0;
  192. }
  193. #endif
  194. #if defined(CONFIG_MMC)
  195. void board_mmc_power_init(void)
  196. {
  197. twl4030_power_mmc_init(0);
  198. }
  199. #endif
  200. #ifdef CONFIG_SMC911X
  201. /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
  202. static const u32 gpmc_lan92xx_config[] = {
  203. NET_LAN92XX_GPMC_CONFIG1,
  204. NET_LAN92XX_GPMC_CONFIG2,
  205. NET_LAN92XX_GPMC_CONFIG3,
  206. NET_LAN92XX_GPMC_CONFIG4,
  207. NET_LAN92XX_GPMC_CONFIG5,
  208. NET_LAN92XX_GPMC_CONFIG6,
  209. };
  210. int board_eth_init(bd_t *bis)
  211. {
  212. enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
  213. CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
  214. return smc911x_initialize(0, CONFIG_SMC911X_BASE);
  215. }
  216. #endif