spl.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <serial.h>
  9. #include <spl.h>
  10. #include <linux/libfdt.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/mx6-ddr.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include "asm/arch/crm_regs.h"
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include "asm/arch/iomux.h"
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/gpio.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <netdev.h>
  23. #include <bootcount.h>
  24. #include <watchdog.h>
  25. #include "common.h"
  26. DECLARE_GLOBAL_DATA_PTR;
  27. static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  28. .dram_sdclk_0 = 0x00000030,
  29. .dram_sdclk_1 = 0x00000030,
  30. .dram_cas = 0x00000030,
  31. .dram_ras = 0x00000030,
  32. .dram_reset = 0x00000030,
  33. .dram_sdcke0 = 0x00003000,
  34. .dram_sdcke1 = 0x00003000,
  35. .dram_sdba2 = 0x00000000,
  36. .dram_sdodt0 = 0x00000030,
  37. .dram_sdodt1 = 0x00000030,
  38. .dram_sdqs0 = 0x00000030,
  39. .dram_sdqs1 = 0x00000030,
  40. .dram_sdqs2 = 0x00000030,
  41. .dram_sdqs3 = 0x00000030,
  42. .dram_sdqs4 = 0x00000030,
  43. .dram_sdqs5 = 0x00000030,
  44. .dram_sdqs6 = 0x00000030,
  45. .dram_sdqs7 = 0x00000030,
  46. .dram_dqm0 = 0x00000030,
  47. .dram_dqm1 = 0x00000030,
  48. .dram_dqm2 = 0x00000030,
  49. .dram_dqm3 = 0x00000030,
  50. .dram_dqm4 = 0x00000030,
  51. .dram_dqm5 = 0x00000030,
  52. .dram_dqm6 = 0x00000030,
  53. .dram_dqm7 = 0x00000030,
  54. };
  55. static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  56. .grp_ddr_type = 0x000c0000,
  57. .grp_ddrmode_ctl = 0x00020000,
  58. .grp_ddrpke = 0x00000000,
  59. .grp_addds = 0x00000030,
  60. .grp_ctlds = 0x00000030,
  61. .grp_ddrmode = 0x00020000,
  62. .grp_b0ds = 0x00000030,
  63. .grp_b1ds = 0x00000030,
  64. .grp_b2ds = 0x00000030,
  65. .grp_b3ds = 0x00000030,
  66. .grp_b4ds = 0x00000030,
  67. .grp_b5ds = 0x00000030,
  68. .grp_b6ds = 0x00000030,
  69. .grp_b7ds = 0x00000030,
  70. };
  71. /* 4x128Mx16.cfg */
  72. static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  73. .p0_mpwldectrl0 = 0x002D0028,
  74. .p0_mpwldectrl1 = 0x0032002D,
  75. .p1_mpwldectrl0 = 0x00210036,
  76. .p1_mpwldectrl1 = 0x0019002E,
  77. .p0_mpdgctrl0 = 0x4349035C,
  78. .p0_mpdgctrl1 = 0x0348033D,
  79. .p1_mpdgctrl0 = 0x43550362,
  80. .p1_mpdgctrl1 = 0x03520316,
  81. .p0_mprddlctl = 0x41393940,
  82. .p1_mprddlctl = 0x3F3A3C47,
  83. .p0_mpwrdlctl = 0x413A423A,
  84. .p1_mpwrdlctl = 0x4042483E,
  85. };
  86. /* MT41K128M16JT-125 (2Gb density) */
  87. static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  88. .mem_speed = 1600,
  89. .density = 2,
  90. .width = 16,
  91. .banks = 8,
  92. .rowaddr = 14,
  93. .coladdr = 10,
  94. .pagesz = 2,
  95. .trcd = 1375,
  96. .trcmin = 4875,
  97. .trasmin = 3500,
  98. };
  99. iomux_v3_cfg_t const uart_console_pads[] = {
  100. /* UART5 */
  101. MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  102. MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  103. MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  104. MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  105. };
  106. void displ5_set_iomux_uart_spl(void)
  107. {
  108. SETUP_IOMUX_PADS(uart_console_pads);
  109. }
  110. iomux_v3_cfg_t const misc_pads_spl[] = {
  111. /* Emergency recovery pin */
  112. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  113. };
  114. void displ5_set_iomux_misc_spl(void)
  115. {
  116. SETUP_IOMUX_PADS(misc_pads_spl);
  117. }
  118. #ifdef CONFIG_MXC_SPI
  119. iomux_v3_cfg_t const ecspi2_pads[] = {
  120. /* SPI2, NOR Flash nWP, CS0 */
  121. MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  122. MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  123. MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  124. MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  125. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  126. };
  127. int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
  128. {
  129. if (bus != 1 || cs != 0)
  130. return -EINVAL;
  131. return IMX_GPIO_NR(5, 29);
  132. }
  133. void displ5_set_iomux_ecspi_spl(void)
  134. {
  135. SETUP_IOMUX_PADS(ecspi2_pads);
  136. }
  137. #else
  138. void displ5_set_iomux_ecspi_spl(void) {}
  139. #endif
  140. #ifdef CONFIG_FSL_ESDHC_IMX
  141. iomux_v3_cfg_t const usdhc4_pads[] = {
  142. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  143. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  144. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  145. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  146. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  147. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  148. MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  149. MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150. MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151. MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  152. MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153. };
  154. void displ5_set_iomux_usdhc_spl(void)
  155. {
  156. SETUP_IOMUX_PADS(usdhc4_pads);
  157. }
  158. #else
  159. void displ5_set_iomux_usdhc_spl(void) {}
  160. #endif
  161. static void ccgr_init(void)
  162. {
  163. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  164. writel(0x00C03F3F, &ccm->CCGR0);
  165. writel(0x0030FC3F, &ccm->CCGR1);
  166. writel(0x0FFFCFC0, &ccm->CCGR2);
  167. writel(0x3FF00000, &ccm->CCGR3);
  168. writel(0x00FFF300, &ccm->CCGR4);
  169. writel(0x0F0000C3, &ccm->CCGR5);
  170. writel(0x000003FF, &ccm->CCGR6);
  171. }
  172. #ifdef CONFIG_MX6_DDRCAL
  173. static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
  174. {
  175. struct mx6_mmdc_calibration calibration = {0};
  176. mmdc_read_calibration(sysinfo, &calibration);
  177. debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
  178. debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
  179. debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
  180. debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
  181. debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
  182. debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
  183. debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
  184. debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
  185. debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
  186. debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
  187. debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
  188. debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
  189. }
  190. static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
  191. {
  192. int ret;
  193. /* Perform DDR DRAM calibration */
  194. udelay(100);
  195. ret = mmdc_do_write_level_calibration(sysinfo);
  196. if (ret) {
  197. printf("DDR: Write level calibration error [%d]\n", ret);
  198. return;
  199. }
  200. ret = mmdc_do_dqs_calibration(sysinfo);
  201. if (ret) {
  202. printf("DDR: DQS calibration error [%d]\n", ret);
  203. return;
  204. }
  205. spl_dram_print_cal(sysinfo);
  206. }
  207. #endif /* CONFIG_MX6_DDRCAL */
  208. static void spl_dram_init(void)
  209. {
  210. struct mx6_ddr_sysinfo sysinfo = {
  211. /* width of data bus:0=16,1=32,2=64 */
  212. .dsize = 2,
  213. /* config for full 4GB range so that get_mem_size() works */
  214. .cs_density = 32, /* 32Gb per CS */
  215. /* single chip select */
  216. .ncs = 1,
  217. .cs1_mirror = 0,
  218. .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
  219. .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
  220. .walat = 1, /* Write additional latency */
  221. .ralat = 5, /* Read additional latency */
  222. .mif3_mode = 3, /* Command prediction working mode */
  223. .bi_on = 1, /* Bank interleaving enabled */
  224. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  225. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  226. .pd_fast_exit = 1, /* enable precharge power-down fast exit */
  227. .ddr_type = DDR_TYPE_DDR3,
  228. .refsel = 1, /* Refresh cycles at 32KHz */
  229. .refr = 7, /* 8 refresh commands per refresh cycle */
  230. };
  231. mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  232. mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
  233. #ifdef CONFIG_MX6_DDRCAL
  234. spl_dram_perform_cal(&sysinfo);
  235. #endif
  236. }
  237. #ifdef CONFIG_SPL_SPI_SUPPORT
  238. static void displ5_init_ecspi(void)
  239. {
  240. displ5_set_iomux_ecspi_spl();
  241. enable_spi_clk(1, 1);
  242. }
  243. #else
  244. static inline void displ5_init_ecspi(void) { }
  245. #endif
  246. #ifdef CONFIG_SPL_MMC_SUPPORT
  247. static struct fsl_esdhc_cfg usdhc_cfg = {
  248. .esdhc_base = USDHC4_BASE_ADDR,
  249. .max_bus_width = 8,
  250. };
  251. int board_mmc_init(bd_t *bd)
  252. {
  253. displ5_set_iomux_usdhc_spl();
  254. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  255. gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
  256. return fsl_esdhc_initialize(bd, &usdhc_cfg);
  257. }
  258. #endif
  259. void board_init_f(ulong dummy)
  260. {
  261. ccgr_init();
  262. arch_cpu_init();
  263. gpr_init();
  264. /* setup GP timer */
  265. timer_init();
  266. displ5_set_iomux_uart_spl();
  267. /* UART clocks enabled and gd valid - init serial console */
  268. preloader_console_init();
  269. displ5_init_ecspi();
  270. /* DDR initialization */
  271. spl_dram_init();
  272. /* Clear the BSS. */
  273. memset(__bss_start, 0, __bss_end - __bss_start);
  274. displ5_set_iomux_misc_spl();
  275. /* Initialize and reset WDT in SPL */
  276. hw_watchdog_init();
  277. WATCHDOG_RESET();
  278. /* load/boot image from boot device */
  279. board_init_r(NULL, 0);
  280. }
  281. #define EM_PAD IMX_GPIO_NR(3, 29)
  282. int board_check_emergency_pad(void)
  283. {
  284. int ret;
  285. ret = gpio_direction_input(EM_PAD);
  286. if (ret)
  287. return ret;
  288. return !gpio_get_value(EM_PAD);
  289. }
  290. void board_boot_order(u32 *spl_boot_list)
  291. {
  292. /* Default boot sequence SPI -> MMC */
  293. spl_boot_list[0] = spl_boot_device();
  294. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  295. spl_boot_list[2] = BOOT_DEVICE_UART;
  296. spl_boot_list[3] = BOOT_DEVICE_NONE;
  297. /*
  298. * In case of emergency PAD pressed, we always boot
  299. * to proper u-boot and perform recovery tasks there.
  300. */
  301. if (board_check_emergency_pad())
  302. return;
  303. #ifdef CONFIG_SPL_ENV_SUPPORT
  304. /* 'fastboot' */
  305. const char *s;
  306. if (env_init() || env_load())
  307. return;
  308. s = env_get("BOOT_FROM");
  309. if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
  310. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  311. spl_boot_list[1] = spl_boot_device();
  312. }
  313. #endif
  314. }
  315. void reset_cpu(ulong addr) {}
  316. #ifdef CONFIG_SPL_LOAD_FIT
  317. int board_fit_config_name_match(const char *name)
  318. {
  319. return 0;
  320. }
  321. #endif
  322. #ifdef CONFIG_SPL_OS_BOOT
  323. /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
  324. int spl_start_uboot(void)
  325. {
  326. /* break into full u-boot on 'c' */
  327. if (serial_tstc() && serial_getc() == 'c')
  328. return 1;
  329. #ifdef CONFIG_SPL_ENV_SUPPORT
  330. if (env_get_yesno("boot_os") != 1)
  331. return 1;
  332. #endif
  333. return 0;
  334. }
  335. #endif