spl.c 1.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <serial.h>
  3. #include <asm/io.h>
  4. #include <asm/arch/mem.h>
  5. #include <asm/arch/sys_proto.h>
  6. #include <jffs2/load_kernel.h>
  7. #include <linux/mtd/rawnand.h>
  8. #include "igep00x0.h"
  9. /*
  10. * Routine: get_board_mem_timings
  11. * Description: If we use SPL then there is no x-loader nor config header
  12. * so we have to setup the DDR timings ourself on both banks.
  13. */
  14. void get_board_mem_timings(struct board_sdrc_timings *timings)
  15. {
  16. int mfr, id, err = identify_nand_chip(&mfr, &id);
  17. timings->mr = MICRON_V_MR_165;
  18. if (!err) {
  19. switch (mfr) {
  20. case NAND_MFR_HYNIX:
  21. timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  22. timings->ctrla = HYNIX_V_ACTIMA_200;
  23. timings->ctrlb = HYNIX_V_ACTIMB_200;
  24. break;
  25. case NAND_MFR_MICRON:
  26. timings->mcfg = MICRON_V_MCFG_200(256 << 20);
  27. timings->ctrla = MICRON_V_ACTIMA_200;
  28. timings->ctrlb = MICRON_V_ACTIMB_200;
  29. break;
  30. default:
  31. /* Should not happen... */
  32. break;
  33. }
  34. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  35. gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  36. } else {
  37. if (get_cpu_family() == CPU_OMAP34XX) {
  38. timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
  39. timings->ctrla = NUMONYX_V_ACTIMA_165;
  40. timings->ctrlb = NUMONYX_V_ACTIMB_165;
  41. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  42. } else {
  43. timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
  44. timings->ctrla = NUMONYX_V_ACTIMA_200;
  45. timings->ctrlb = NUMONYX_V_ACTIMB_200;
  46. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
  47. }
  48. gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  49. }
  50. }
  51. #ifdef CONFIG_SPL_OS_BOOT
  52. int spl_start_uboot(void)
  53. {
  54. /* break into full u-boot on 'c' */
  55. if (serial_tstc() && serial_getc() == 'c')
  56. return 1;
  57. return 0;
  58. }
  59. #endif