meesc.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2009-2015
  8. * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  9. * esd electronic system design gmbh <www.esd.eu>
  10. */
  11. #include <common.h>
  12. #include <env.h>
  13. #include <serial.h>
  14. #include <vsprintf.h>
  15. #include <asm/io.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/setup.h>
  19. #include <asm/arch/at91sam9_smc.h>
  20. #include <asm/arch/at91_common.h>
  21. #include <asm/arch/at91_pmc.h>
  22. #include <asm/arch/at91_rstc.h>
  23. #include <asm/arch/at91_matrix.h>
  24. #include <asm/arch/at91_pio.h>
  25. #include <asm/arch/clk.h>
  26. #include <netdev.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /*
  29. * Miscelaneous platform dependent initialisations
  30. */
  31. #ifdef CONFIG_REVISION_TAG
  32. static int hw_rev = -1; /* hardware revision */
  33. int get_hw_rev(void)
  34. {
  35. if (hw_rev >= 0)
  36. return hw_rev;
  37. hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  38. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  39. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  40. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  41. if (hw_rev == 15)
  42. hw_rev = 0;
  43. return hw_rev;
  44. }
  45. #endif /* CONFIG_REVISION_TAG */
  46. #ifdef CONFIG_CMD_NAND
  47. static void meesc_nand_hw_init(void)
  48. {
  49. unsigned long csa;
  50. at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
  51. at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  52. /* Enable CS3 */
  53. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  54. writel(csa, &matrix->csa[0]);
  55. /* Configure SMC CS3 for NAND/SmartMedia */
  56. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  57. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  58. &smc->cs[3].setup);
  59. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  60. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  61. &smc->cs[3].pulse);
  62. writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  63. &smc->cs[3].cycle);
  64. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  65. AT91_SMC_MODE_EXNW_DISABLE |
  66. AT91_SMC_MODE_DBW_8 |
  67. AT91_SMC_MODE_TDF_CYCLE(12),
  68. &smc->cs[3].mode);
  69. /* Configure RDY/BSY */
  70. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  71. /* Enable NandFlash */
  72. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  73. }
  74. #endif /* CONFIG_CMD_NAND */
  75. #ifdef CONFIG_MACB
  76. static void meesc_macb_hw_init(void)
  77. {
  78. at91_periph_clk_enable(ATMEL_ID_EMAC);
  79. at91_macb_hw_init();
  80. }
  81. #endif
  82. /*
  83. * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
  84. * controller debugging
  85. * The ET1100 is located at physical address 0x70000000
  86. * Its process memory is located at physical address 0x70001000
  87. */
  88. static void meesc_ethercat_hw_init(void)
  89. {
  90. at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
  91. /* Configure SMC EBI1_CS0 for EtherCAT */
  92. writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
  93. AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
  94. &smc1->cs[0].setup);
  95. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
  96. AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
  97. &smc1->cs[0].pulse);
  98. writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
  99. &smc1->cs[0].cycle);
  100. /*
  101. * Configure behavior at external wait signal, byte-select mode, 16 bit
  102. * data bus width, none data float wait states and TDF optimization
  103. */
  104. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
  105. AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
  106. AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
  107. /* Configure RDY/BSY */
  108. at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
  109. }
  110. int dram_init(void)
  111. {
  112. /* dram_init must store complete ramsize in gd->ram_size */
  113. gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
  114. PHYS_SDRAM_SIZE);
  115. return 0;
  116. }
  117. int dram_init_banksize(void)
  118. {
  119. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  120. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  121. return 0;
  122. }
  123. int board_eth_init(bd_t *bis)
  124. {
  125. int rc = 0;
  126. #ifdef CONFIG_MACB
  127. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  128. #endif
  129. return rc;
  130. }
  131. #ifdef CONFIG_DISPLAY_BOARDINFO
  132. int checkboard(void)
  133. {
  134. char str[32];
  135. u_char hw_type; /* hardware type */
  136. /* read the "Type" register of the ET1100 controller */
  137. hw_type = readb(CONFIG_ET1100_BASE);
  138. switch (hw_type) {
  139. case 0x11:
  140. case 0x3F:
  141. /* ET1100 present, arch number of MEESC-Board */
  142. gd->bd->bi_arch_number = MACH_TYPE_MEESC;
  143. puts("Board: CAN-EtherCAT Gateway");
  144. break;
  145. case 0xFF:
  146. /* no ET1100 present, arch number of EtherCAN/2-Board */
  147. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  148. puts("Board: EtherCAN/2 Gateway");
  149. /* switch on LED1D */
  150. at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
  151. break;
  152. default:
  153. /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
  154. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  155. printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
  156. puts("Board: EtherCAN/2 Gateway");
  157. break;
  158. }
  159. if (env_get_f("serial#", str, sizeof(str)) > 0) {
  160. puts(", serial# ");
  161. puts(str);
  162. }
  163. #ifdef CONFIG_REVISION_TAG
  164. printf("\nHardware-revision: 1.%d\n", get_hw_rev());
  165. #endif
  166. printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
  167. return 0;
  168. }
  169. #endif /* CONFIG_DISPLAY_BOARDINFO */
  170. #ifdef CONFIG_SERIAL_TAG
  171. void get_board_serial(struct tag_serialnr *serialnr)
  172. {
  173. char *str;
  174. char *serial = env_get("serial#");
  175. if (serial) {
  176. str = strchr(serial, '_');
  177. if (str && (strlen(str) >= 4)) {
  178. serialnr->high = (*(str + 1) << 8) | *(str + 2);
  179. serialnr->low = simple_strtoul(str + 3, NULL, 16);
  180. }
  181. } else {
  182. serialnr->high = 0;
  183. serialnr->low = 0;
  184. }
  185. }
  186. #endif
  187. #ifdef CONFIG_REVISION_TAG
  188. u32 get_board_rev(void)
  189. {
  190. return hw_rev | 0x100;
  191. }
  192. #endif
  193. #ifdef CONFIG_MISC_INIT_R
  194. int misc_init_r(void)
  195. {
  196. char *str;
  197. char buf[32];
  198. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  199. /*
  200. * Normally the processor clock has a divisor of 2.
  201. * In some cases this this needs to be set to 4.
  202. * Check the user has set environment mdiv to 4 to change the divisor.
  203. */
  204. str = env_get("mdiv");
  205. if (str && (strcmp(str, "4") == 0)) {
  206. writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
  207. AT91SAM9_PMC_MDIV_4, &pmc->mckr);
  208. at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
  209. serial_setbrg();
  210. /* Notify the user that the clock is not default */
  211. printf("Setting master clock to %s MHz\n",
  212. strmhz(buf, get_mck_clk_rate()));
  213. }
  214. return 0;
  215. }
  216. #endif /* CONFIG_MISC_INIT_R */
  217. int board_early_init_f(void)
  218. {
  219. at91_periph_clk_enable(ATMEL_ID_UHP);
  220. return 0;
  221. }
  222. int board_init(void)
  223. {
  224. /* initialize ET1100 Controller */
  225. meesc_ethercat_hw_init();
  226. /* adress of boot parameters */
  227. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  228. #ifdef CONFIG_CMD_NAND
  229. meesc_nand_hw_init();
  230. #endif
  231. #ifdef CONFIG_MACB
  232. meesc_macb_hw_init();
  233. #endif
  234. #ifdef CONFIG_AT91_CAN
  235. at91_can_hw_init();
  236. #endif
  237. #ifdef CONFIG_USB_OHCI_NEW
  238. at91_uhp_hw_init();
  239. #endif
  240. return 0;
  241. }