spl.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
  4. * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
  5. * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
  6. */
  7. #include <common.h>
  8. #include <serial.h>
  9. #include <spl.h>
  10. #include <asm/io.h>
  11. #include <linux/sizes.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/mx6-ddr.h>
  16. #include <asm/arch/mx6-pins.h>
  17. #include <asm/arch/sys_proto.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define IMX6SDL_DRIVE_STRENGTH 0x28
  20. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  21. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  22. static iomux_v3_cfg_t const uart3_pads[] = {
  23. IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  24. IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  25. };
  26. #ifdef CONFIG_SPL_OS_BOOT
  27. int spl_start_uboot(void)
  28. {
  29. /* break into full u-boot on 'c' */
  30. if (serial_tstc() && serial_getc() == 'c')
  31. return 1;
  32. return 0;
  33. }
  34. #endif
  35. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  36. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  37. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  38. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  39. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  40. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  41. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  42. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  43. .dram_sdba2 = 0x00000000,
  44. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  45. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  46. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  47. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  48. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  49. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  50. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  51. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  52. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  53. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  54. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  55. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  56. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  57. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  58. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  59. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  60. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  61. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  62. };
  63. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  64. .grp_ddr_type = 0x000c0000,
  65. .grp_ddrmode_ctl = 0x00020000,
  66. .grp_ddrpke = 0x00000000,
  67. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  68. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  69. .grp_ddrmode = 0x00020000,
  70. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  71. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  72. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  73. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  74. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  75. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  76. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  77. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  78. };
  79. static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  80. .mem_speed = 1600,
  81. .density = 4,
  82. .width = 32,
  83. .banks = 8,
  84. .rowaddr = 14,
  85. .coladdr = 10,
  86. .pagesz = 2,
  87. .trcd = 1375,
  88. .trcmin = 4875,
  89. .trasmin = 3500,
  90. .SRT = 0,
  91. };
  92. static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
  93. .p0_mpwldectrl0 = 0x0042004b,
  94. .p0_mpwldectrl1 = 0x0038003c,
  95. .p0_mpdgctrl0 = 0x42340230,
  96. .p0_mpdgctrl1 = 0x0228022c,
  97. .p0_mprddlctl = 0x42444646,
  98. .p0_mpwrdlctl = 0x38382e2e,
  99. };
  100. static struct mx6_ddr_sysinfo mem_dl = {
  101. .dsize = 1,
  102. .cs1_mirror = 0,
  103. /* config for full 4GB range so that get_mem_size() works */
  104. .cs_density = 32,
  105. .ncs = 1,
  106. .bi_on = 1,
  107. .rtt_nom = 1,
  108. .rtt_wr = 1,
  109. .ralat = 5,
  110. .walat = 0,
  111. .mif3_mode = 3,
  112. .rst_to_cke = 0x23,
  113. .sde_to_rst = 0x10,
  114. .refsel = 1,
  115. .refr = 7,
  116. };
  117. static void spl_dram_init(void)
  118. {
  119. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  120. mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
  121. udelay(100);
  122. }
  123. static void ccgr_init(void)
  124. {
  125. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  126. writel(0x00003f3f, &ccm->CCGR0);
  127. writel(0x0030fc00, &ccm->CCGR1);
  128. writel(0x000fc000, &ccm->CCGR2);
  129. writel(0x3f300000, &ccm->CCGR3);
  130. writel(0xff00f300, &ccm->CCGR4);
  131. writel(0x0f0000c3, &ccm->CCGR5);
  132. writel(0x000003cc, &ccm->CCGR6);
  133. }
  134. void board_init_f(ulong dummy)
  135. {
  136. ccgr_init();
  137. /* setup AIPS and disable watchdog */
  138. arch_cpu_init();
  139. gpr_init();
  140. /* iomux */
  141. SETUP_IOMUX_PADS(uart3_pads);
  142. /* setup GP timer */
  143. timer_init();
  144. /* UART clocks enabled and gd valid - init serial console */
  145. preloader_console_init();
  146. /* DDR initialization */
  147. spl_dram_init();
  148. }