board.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Birdland Audio BAV335x Network Processor
  6. *
  7. * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <serial.h>
  13. #include <spl.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/hardware.h>
  16. #include <asm/arch/omap.h>
  17. #include <asm/arch/ddr_defs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/gpio.h>
  20. #include <asm/arch/mmc_host_def.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/arch/mem.h>
  23. #include <asm/io.h>
  24. #include <asm/emif.h>
  25. #include <asm/gpio.h>
  26. #include <i2c.h>
  27. #include <miiphy.h>
  28. #include <cpsw.h>
  29. #include <power/tps65217.h>
  30. #include <power/tps65910.h>
  31. #include <env_internal.h>
  32. #include <watchdog.h>
  33. #include "board.h"
  34. DECLARE_GLOBAL_DATA_PTR;
  35. /* GPIO that controls power to DDR on EVM-SK */
  36. #define GPIO_DDR_VTT_EN 7
  37. static __maybe_unused struct ctrl_dev *cdev =
  38. (struct ctrl_dev *)CTRL_DEVICE_BASE;
  39. /*
  40. * Read header information from EEPROM into global structure.
  41. */
  42. static int read_eeprom(struct board_eeconfig *header)
  43. {
  44. /* Check if baseboard eeprom is available */
  45. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
  46. return -ENODEV;
  47. /* read the eeprom using i2c */
  48. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  49. sizeof(struct board_eeconfig)))
  50. return -EIO;
  51. if (header->magic != BOARD_MAGIC) {
  52. /* read the i2c eeprom again using only a 1 byte address */
  53. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  54. sizeof(struct board_eeconfig)))
  55. return -EIO;
  56. if (header->magic != BOARD_MAGIC)
  57. return -EINVAL;
  58. }
  59. return 0;
  60. }
  61. enum board_type get_board_type(bool debug)
  62. {
  63. int ecode;
  64. struct board_eeconfig header;
  65. ecode = read_eeprom(&header);
  66. if (ecode == 0) {
  67. if (header.version[1] == 'A') {
  68. if (debug)
  69. puts("=== Detected Board model BAV335x Rev.A");
  70. return BAV335A;
  71. } else if (header.version[1] == 'B') {
  72. if (debug)
  73. puts("=== Detected Board model BAV335x Rev.B");
  74. return BAV335B;
  75. } else if (debug) {
  76. puts("### Un-known board model in serial-EE\n");
  77. }
  78. } else if (debug) {
  79. switch (ecode) {
  80. case -ENODEV:
  81. puts("### Board doesn't have a serial-EE\n");
  82. break;
  83. case -EINVAL:
  84. puts("### Board serial-EE signature is incorrect.\n");
  85. break;
  86. default:
  87. puts("### IO Error reading serial-EE.\n");
  88. break;
  89. }
  90. }
  91. #if (CONFIG_BAV_VERSION == 1)
  92. if (debug)
  93. puts("### Selecting BAV335A as per config\n");
  94. return BAV335A;
  95. #elif (CONFIG_BAV_VERSION == 2)
  96. if (debug)
  97. puts("### Selecting BAV335B as per config\n");
  98. return BAV335B;
  99. #endif
  100. #if (NOT_DEFINED == 2)
  101. #error "SHOULD NEVER DISPLAY THIS"
  102. #endif
  103. if (debug)
  104. puts("### Defaulting to model BAV335x Rev.B\n");
  105. return BAV335B;
  106. }
  107. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  108. static const struct ddr_data ddr3_bav335x_data = {
  109. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  110. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  111. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  112. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  113. };
  114. static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
  115. .cmd0csratio = MT41K256M16HA125E_RATIO,
  116. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  117. .cmd1csratio = MT41K256M16HA125E_RATIO,
  118. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  119. .cmd2csratio = MT41K256M16HA125E_RATIO,
  120. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  121. };
  122. static struct emif_regs ddr3_bav335x_emif_reg_data = {
  123. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  124. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  125. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  126. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  127. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  128. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  129. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  130. };
  131. #ifdef CONFIG_SPL_OS_BOOT
  132. int spl_start_uboot(void)
  133. {
  134. /* break into full u-boot on 'c' */
  135. if (serial_tstc() && serial_getc() == 'c')
  136. return 1;
  137. #ifdef CONFIG_SPL_ENV_SUPPORT
  138. env_init();
  139. env_load();
  140. if (env_get_yesno("boot_os") != 1)
  141. return 1;
  142. #endif
  143. return 0;
  144. }
  145. #endif
  146. #define OSC (V_OSCK/1000000)
  147. const struct dpll_params dpll_ddr = {
  148. 266, OSC-1, 1, -1, -1, -1, -1};
  149. const struct dpll_params dpll_ddr_evm_sk = {
  150. 303, OSC-1, 1, -1, -1, -1, -1};
  151. const struct dpll_params dpll_ddr_bone_black = {
  152. 400, OSC-1, 1, -1, -1, -1, -1};
  153. void am33xx_spl_board_init(void)
  154. {
  155. /* debug print detect status */
  156. (void)get_board_type(true);
  157. /* Get the frequency */
  158. /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
  159. dpll_mpu_opp100.m = MPUPLL_M_1000;
  160. if (i2c_probe(TPS65217_CHIP_PM))
  161. return;
  162. /* Set the USB Current Limit */
  163. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
  164. TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
  165. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  166. puts("! tps65217_reg_write: could not set USB limit\n");
  167. /* Set the Core Voltage (DCDC3) to 1.125V */
  168. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  169. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  170. puts("! tps65217_reg_write: could not set Core Voltage\n");
  171. return;
  172. }
  173. /* Set CORE Frequencies to OPP100 */
  174. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  175. /* Set the MPU Voltage (DCDC2) */
  176. if (tps65217_voltage_update(TPS65217_DEFDCDC2,
  177. TPS65217_DCDC_VOLT_SEL_1325MV)) {
  178. puts("! tps65217_reg_write: could not set MPU Voltage\n");
  179. return;
  180. }
  181. /*
  182. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  183. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  184. */
  185. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
  186. TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
  187. puts("! tps65217_reg_write: could not set LDO3\n");
  188. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
  189. TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
  190. puts("! tps65217_reg_write: could not set LDO4\n");
  191. /* Set MPU Frequency to what we detected now that voltages are set */
  192. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  193. }
  194. const struct dpll_params *get_dpll_ddr_params(void)
  195. {
  196. enable_i2c0_pin_mux();
  197. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  198. return &dpll_ddr_bone_black;
  199. }
  200. void set_uart_mux_conf(void)
  201. {
  202. #if CONFIG_CONS_INDEX == 1
  203. enable_uart0_pin_mux();
  204. #elif CONFIG_CONS_INDEX == 2
  205. enable_uart1_pin_mux();
  206. #elif CONFIG_CONS_INDEX == 3
  207. enable_uart2_pin_mux();
  208. #elif CONFIG_CONS_INDEX == 4
  209. enable_uart3_pin_mux();
  210. #elif CONFIG_CONS_INDEX == 5
  211. enable_uart4_pin_mux();
  212. #elif CONFIG_CONS_INDEX == 6
  213. enable_uart5_pin_mux();
  214. #endif
  215. }
  216. void set_mux_conf_regs(void)
  217. {
  218. enum board_type board;
  219. board = get_board_type(false);
  220. enable_board_pin_mux(board);
  221. }
  222. const struct ctrl_ioregs ioregs_bonelt = {
  223. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  224. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  225. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  226. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  227. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  228. };
  229. void sdram_init(void)
  230. {
  231. config_ddr(400, &ioregs_bonelt,
  232. &ddr3_bav335x_data,
  233. &ddr3_bav335x_cmd_ctrl_data,
  234. &ddr3_bav335x_emif_reg_data, 0);
  235. }
  236. #endif
  237. /*
  238. * Basic board specific setup. Pinmux has been handled already.
  239. */
  240. int board_init(void)
  241. {
  242. #if defined(CONFIG_HW_WATCHDOG)
  243. hw_watchdog_init();
  244. #endif
  245. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  246. #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
  247. gpmc_init();
  248. #endif
  249. return 0;
  250. }
  251. #ifdef CONFIG_BOARD_LATE_INIT
  252. int board_late_init(void)
  253. {
  254. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  255. env_set("board_name", "BAV335xB");
  256. env_set("board_rev", "B"); /* Fix me, but why bother.. */
  257. #endif
  258. return 0;
  259. }
  260. #endif
  261. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  262. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  263. static void cpsw_control(int enabled)
  264. {
  265. /* VTP can be added here */
  266. return;
  267. }
  268. static struct cpsw_slave_data cpsw_slaves[] = {
  269. {
  270. .slave_reg_ofs = 0x208,
  271. .sliver_reg_ofs = 0xd80,
  272. .phy_addr = 0,
  273. },
  274. {
  275. .slave_reg_ofs = 0x308,
  276. .sliver_reg_ofs = 0xdc0,
  277. .phy_addr = 1,
  278. },
  279. };
  280. static struct cpsw_platform_data cpsw_data = {
  281. .mdio_base = CPSW_MDIO_BASE,
  282. .cpsw_base = CPSW_BASE,
  283. .mdio_div = 0xff,
  284. .channels = 8,
  285. .cpdma_reg_ofs = 0x800,
  286. .slaves = 1,
  287. .slave_data = cpsw_slaves,
  288. .ale_reg_ofs = 0xd00,
  289. .ale_entries = 1024,
  290. .host_port_reg_ofs = 0x108,
  291. .hw_stats_reg_ofs = 0x900,
  292. .bd_ram_ofs = 0x2000,
  293. .mac_control = (1 << 5),
  294. .control = cpsw_control,
  295. .host_port_num = 0,
  296. .version = CPSW_CTRL_VERSION_2,
  297. };
  298. #endif
  299. /*
  300. * This function will:
  301. * Perform fixups to the PHY present on certain boards. We only need this
  302. * function in:
  303. * - SPL with either CPSW or USB ethernet support
  304. * - Full U-Boot, with either CPSW or USB ethernet
  305. * Build in only these cases to avoid warnings about unused variables
  306. * when we build an SPL that has neither option but full U-Boot will.
  307. */
  308. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
  309. defined(CONFIG_SPL_BUILD)) || \
  310. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  311. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  312. !defined(CONFIG_SPL_BUILD))
  313. int board_eth_init(bd_t *bis)
  314. {
  315. int ecode, rv, n;
  316. uint8_t mac_addr[6];
  317. struct board_eeconfig header;
  318. __maybe_unused enum board_type board;
  319. /* Default manufacturing address; used when no EE or invalid */
  320. n = 0;
  321. mac_addr[0] = 0;
  322. mac_addr[1] = 0x20;
  323. mac_addr[2] = 0x18;
  324. mac_addr[3] = 0x1C;
  325. mac_addr[4] = 0x00;
  326. mac_addr[5] = 0x01;
  327. ecode = read_eeprom(&header);
  328. /* if we have a valid EE, get mac address from there */
  329. if ((ecode == 0) &&
  330. is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
  331. memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
  332. }
  333. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  334. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  335. if (!env_get("ethaddr")) {
  336. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  337. if (is_valid_ethaddr(mac_addr))
  338. eth_env_set_enetaddr("ethaddr", mac_addr);
  339. }
  340. #ifdef CONFIG_DRIVER_TI_CPSW
  341. board = get_board_type(false);
  342. /* Rev.A uses 10/100 PHY in mii mode */
  343. if (board == BAV335A) {
  344. writel(MII_MODE_ENABLE, &cdev->miisel);
  345. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
  346. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
  347. }
  348. /* Rev.B (default) uses GB PHY in rmii mode */
  349. else {
  350. writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
  351. cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
  352. = PHY_INTERFACE_MODE_RGMII;
  353. }
  354. rv = cpsw_register(&cpsw_data);
  355. if (rv < 0)
  356. printf("Error %d registering CPSW switch\n", rv);
  357. else
  358. n += rv;
  359. #endif
  360. #endif
  361. return n;
  362. }
  363. #endif