ddr.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * DDR controller configuration for the i.MX7 architecture
  4. *
  5. * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
  6. *
  7. * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
  8. */
  9. #include <linux/types.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/mx7-ddr.h>
  14. #include <common.h>
  15. #include <linux/delay.h>
  16. /*
  17. * Routine: mx7_dram_cfg
  18. * Description: DDR controller configuration
  19. *
  20. * @ddrc_regs_val: DDRC registers value
  21. * @ddrc_mp_val: DDRC_MP registers value
  22. * @ddr_phy_regs_val: DDR_PHY registers value
  23. * @calib_param: calibration parameters
  24. *
  25. */
  26. void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
  27. struct ddr_phy *ddr_phy_regs_val,
  28. struct mx7_calibration *calib_param)
  29. {
  30. struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
  31. struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
  32. struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
  33. struct ddr_phy *const ddr_phy_regs =
  34. (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
  35. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
  36. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  37. int i;
  38. /*
  39. * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
  40. * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 ,
  41. * aresetn_n = 0, presetn = 0. That means reset everything.
  42. */
  43. writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK,
  44. &src_regs->ddrc_rcr);
  45. /*
  46. * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown).
  47. * If we assume this is 30 cycles at 100 MHz (about the rate of a
  48. * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty.
  49. */
  50. udelay(10);
  51. /* De-assert DDR Controller 'preset' and DDR PHY reset */
  52. clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK);
  53. /* DDR controller configuration */
  54. writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
  55. writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
  56. writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
  57. writel(ddrc_regs_val->init1, &ddrc_regs->init1);
  58. writel(ddrc_regs_val->init0, &ddrc_regs->init0);
  59. writel(ddrc_regs_val->init3, &ddrc_regs->init3);
  60. writel(ddrc_regs_val->init4, &ddrc_regs->init4);
  61. writel(ddrc_regs_val->init5, &ddrc_regs->init5);
  62. writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
  63. writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
  64. writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
  65. writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
  66. writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
  67. writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
  68. writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
  69. writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
  70. writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
  71. writel(ddrc_regs_val->zqctl1, &ddrc_regs->zqctl1);
  72. writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
  73. writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
  74. writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
  75. writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
  76. writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
  77. writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
  78. writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
  79. writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
  80. writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
  81. writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
  82. writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
  83. writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
  84. /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */
  85. clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
  86. /* PHY configuration */
  87. writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
  88. writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
  89. writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
  90. writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
  91. writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
  92. writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
  93. writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
  94. writel(ddr_phy_regs_val->cmd_sdll_con0 |
  95. DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
  96. &ddr_phy_regs->cmd_sdll_con0);
  97. writel(ddr_phy_regs_val->cmd_sdll_con0 &
  98. ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
  99. &ddr_phy_regs->cmd_sdll_con0);
  100. writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
  101. writel(ddr_phy_regs_val->cmd_deskew_con0,
  102. &ddr_phy_regs->cmd_deskew_con0);
  103. writel(ddr_phy_regs_val->cmd_deskew_con1,
  104. &ddr_phy_regs->cmd_deskew_con1);
  105. writel(ddr_phy_regs_val->cmd_deskew_con2,
  106. &ddr_phy_regs->cmd_deskew_con2);
  107. writel(ddr_phy_regs_val->cmd_deskew_con3,
  108. &ddr_phy_regs->cmd_deskew_con3);
  109. writel(ddr_phy_regs_val->cmd_lvl_con0, &ddr_phy_regs->cmd_lvl_con0);
  110. /* calibration */
  111. for (i = 0; i < calib_param->num_val; i++)
  112. writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
  113. /* Wake_up DDR PHY */
  114. HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
  115. writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
  116. IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
  117. &iomuxc_gpr_regs->gpr[8]);
  118. HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
  119. }
  120. /*
  121. * Routine: imx_ddr_size
  122. * Description: extract the current DRAM size from the DDRC registers
  123. *
  124. * @return: DRAM size
  125. */
  126. unsigned int imx_ddr_size(void)
  127. {
  128. struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
  129. u32 reg_val, field_val;
  130. int bits = 0;/* Number of address bits */
  131. /* Count data bus width bits */
  132. reg_val = readl(&ddrc_regs->mstr);
  133. field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
  134. bits += 2 - field_val;
  135. /* Count rank address bits */
  136. field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
  137. if (field_val > 1)
  138. bits += field_val - 1;
  139. /* Count column address bits */
  140. bits += 2;/* Column address 0 and 1 are fixed mapped */
  141. reg_val = readl(&ddrc_regs->addrmap2);
  142. field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
  143. if (field_val <= 7)
  144. bits++;
  145. field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
  146. if (field_val <= 7)
  147. bits++;
  148. field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
  149. if (field_val <= 7)
  150. bits++;
  151. field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
  152. if (field_val <= 7)
  153. bits++;
  154. reg_val = readl(&ddrc_regs->addrmap3);
  155. field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
  156. if (field_val <= 7)
  157. bits++;
  158. field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
  159. if (field_val <= 7)
  160. bits++;
  161. field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
  162. if (field_val <= 7)
  163. bits++;
  164. field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
  165. if (field_val <= 7)
  166. bits++;
  167. reg_val = readl(&ddrc_regs->addrmap4);
  168. field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
  169. if (field_val <= 7)
  170. bits++;
  171. field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
  172. if (field_val <= 7)
  173. bits++;
  174. /* Count row address bits */
  175. reg_val = readl(&ddrc_regs->addrmap5);
  176. field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
  177. if (field_val <= 11)
  178. bits++;
  179. field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
  180. if (field_val <= 11)
  181. bits++;
  182. field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
  183. if (field_val <= 11)
  184. bits += 9;
  185. field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
  186. if (field_val <= 11)
  187. bits++;
  188. reg_val = readl(&ddrc_regs->addrmap6);
  189. field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
  190. if (field_val <= 11)
  191. bits++;
  192. field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
  193. if (field_val <= 11)
  194. bits++;
  195. field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
  196. if (field_val <= 11)
  197. bits++;
  198. field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
  199. if (field_val <= 11)
  200. bits++;
  201. /* Count bank bits */
  202. reg_val = readl(&ddrc_regs->addrmap1);
  203. field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
  204. if (field_val <= 30)
  205. bits++;
  206. field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
  207. if (field_val <= 30)
  208. bits++;
  209. field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
  210. if (field_val <= 29)
  211. bits++;
  212. /* cap to max 2 GB */
  213. if (bits > 31)
  214. bits = 31;
  215. return 1 << bits;
  216. }