socfpga_sr1500.h 3.2 KB

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  1. /*
  2. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __CONFIG_SOCFPGA_SR1500_H__
  7. #define __CONFIG_SOCFPGA_SR1500_H__
  8. #include <asm/arch/base_addr_ac5.h>
  9. #define CONFIG_BOARD_EARLY_INIT_F
  10. #define CONFIG_SYS_NO_FLASH
  11. #define CONFIG_DOS_PARTITION
  12. #define CONFIG_FAT_WRITE
  13. #define CONFIG_HW_WATCHDOG
  14. /* U-Boot Commands */
  15. #define CONFIG_CMD_ASKENV
  16. #define CONFIG_CMD_BOOTZ
  17. #define CONFIG_CMD_CACHE
  18. #define CONFIG_CMD_DHCP
  19. #define CONFIG_CMD_EXT4
  20. #define CONFIG_CMD_EXT4_WRITE
  21. #define CONFIG_CMD_FAT
  22. #define CONFIG_CMD_FS_GENERIC
  23. #define CONFIG_CMD_GPIO
  24. #define CONFIG_CMD_GREPENV
  25. #define CONFIG_CMD_MEMTEST
  26. #define CONFIG_CMD_MII
  27. #define CONFIG_CMD_MMC
  28. #define CONFIG_CMD_PING
  29. #define CONFIG_CMD_SF
  30. #define CONFIG_CMD_SPI
  31. #define CONFIG_CMD_TIME
  32. /* Memory configurations */
  33. #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
  34. /* Booting Linux */
  35. #define CONFIG_BOOTDELAY 3
  36. #define CONFIG_BOOTFILE "uImage"
  37. #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
  38. #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
  39. #define CONFIG_LOADADDR 0x01000000
  40. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  41. #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
  42. /* Ethernet on SoC (EMAC) */
  43. #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
  44. /* The PHY is autodetected, so no MII PHY address is needed here */
  45. #define CONFIG_PHY_MARVELL
  46. #define PHY_ANEG_TIMEOUT 8000
  47. /* Extra Environment */
  48. #define CONFIG_HOSTNAME sr1500
  49. #define CONFIG_EXTRA_ENV_SETTINGS \
  50. "verify=n\0" \
  51. "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  52. "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  53. "bootm ${loadaddr} - ${fdt_addr}\0" \
  54. "bootimage=zImage\0" \
  55. "fdt_addr=100\0" \
  56. "fdtimage=socfpga.dtb\0" \
  57. "fsloadcmd=ext2load\0" \
  58. "bootm ${loadaddr} - ${fdt_addr}\0" \
  59. "mmcroot=/dev/mmcblk0p2\0" \
  60. "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  61. " root=${mmcroot} rw rootwait;" \
  62. "bootz ${loadaddr} - ${fdt_addr}\0" \
  63. "mmcload=mmc rescan;" \
  64. "load mmc 0:1 ${loadaddr} ${bootimage};" \
  65. "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  66. "qspiroot=/dev/mtdblock0\0" \
  67. "qspirootfstype=jffs2\0" \
  68. "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  69. " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
  70. "bootm ${loadaddr} - ${fdt_addr}\0"
  71. /* Environment */
  72. #define CONFIG_ENV_IS_IN_SPI_FLASH
  73. /* Enable SPI NOR flash reset, needed for SPI booting */
  74. #define CONFIG_SPI_N25Q256A_RESET
  75. /*
  76. * Bootcounter
  77. */
  78. #define CONFIG_BOOTCOUNT_LIMIT
  79. /* last 2 lwords in OCRAM */
  80. #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
  81. #define CONFIG_SYS_BOOTCOUNT_BE
  82. /* The rest of the configuration is shared */
  83. #include <configs/socfpga_common.h>
  84. /* U-Boot payload is stored at offset 0x60000 */
  85. #undef CONFIG_SYS_SPI_U_BOOT_OFFS
  86. #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
  87. /* Environment setting for SPI flash */
  88. #undef CONFIG_ENV_SIZE
  89. #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  90. #define CONFIG_ENV_SECT_SIZE (64 * 1024)
  91. #define CONFIG_ENV_SIZE (16 * 1024)
  92. #define CONFIG_ENV_OFFSET 0x00040000
  93. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
  94. #define CONFIG_ENV_SPI_BUS 0
  95. #define CONFIG_ENV_SPI_CS 0
  96. #define CONFIG_ENV_SPI_MODE SPI_MODE_3
  97. #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  98. #endif /* __CONFIG_SOCFPGA_SR1500_H__ */