Kconfig 8.1 KB

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  1. menu "MIPS architecture"
  2. depends on MIPS
  3. config SYS_ARCH
  4. default "mips"
  5. config SYS_CPU
  6. default "mips32" if CPU_MIPS32
  7. default "mips64" if CPU_MIPS64
  8. choice
  9. prompt "Target select"
  10. optional
  11. config TARGET_QEMU_MIPS
  12. bool "Support qemu-mips"
  13. select SUPPORTS_BIG_ENDIAN
  14. select SUPPORTS_LITTLE_ENDIAN
  15. select SUPPORTS_CPU_MIPS32_R1
  16. select SUPPORTS_CPU_MIPS32_R2
  17. select SUPPORTS_CPU_MIPS64_R1
  18. select SUPPORTS_CPU_MIPS64_R2
  19. config TARGET_MALTA
  20. bool "Support malta"
  21. select DM
  22. select DM_SERIAL
  23. select DYNAMIC_IO_PORT_BASE
  24. select MIPS_CM
  25. select MIPS_L2_CACHE
  26. select OF_CONTROL
  27. select OF_ISA_BUS
  28. select SUPPORTS_BIG_ENDIAN
  29. select SUPPORTS_LITTLE_ENDIAN
  30. select SUPPORTS_CPU_MIPS32_R1
  31. select SUPPORTS_CPU_MIPS32_R2
  32. select SUPPORTS_CPU_MIPS32_R6
  33. select SUPPORTS_CPU_MIPS64_R1
  34. select SUPPORTS_CPU_MIPS64_R2
  35. select SUPPORTS_CPU_MIPS64_R6
  36. select SWAP_IO_SPACE
  37. select MIPS_L1_CACHE_SHIFT_6
  38. config TARGET_VCT
  39. bool "Support vct"
  40. select SUPPORTS_BIG_ENDIAN
  41. select SUPPORTS_CPU_MIPS32_R1
  42. select SUPPORTS_CPU_MIPS32_R2
  43. select SYS_MIPS_CACHE_INIT_RAM_LOAD
  44. config TARGET_DBAU1X00
  45. bool "Support dbau1x00"
  46. select SUPPORTS_BIG_ENDIAN
  47. select SUPPORTS_LITTLE_ENDIAN
  48. select SUPPORTS_CPU_MIPS32_R1
  49. select SUPPORTS_CPU_MIPS32_R2
  50. select SYS_MIPS_CACHE_INIT_RAM_LOAD
  51. select MIPS_TUNE_4KC
  52. config TARGET_PB1X00
  53. bool "Support pb1x00"
  54. select SUPPORTS_LITTLE_ENDIAN
  55. select SUPPORTS_CPU_MIPS32_R1
  56. select SUPPORTS_CPU_MIPS32_R2
  57. select SYS_MIPS_CACHE_INIT_RAM_LOAD
  58. select MIPS_TUNE_4KC
  59. config ARCH_ATH79
  60. bool "Support QCA/Atheros ath79"
  61. select OF_CONTROL
  62. select DM
  63. config MACH_PIC32
  64. bool "Support Microchip PIC32"
  65. select OF_CONTROL
  66. select DM
  67. config TARGET_BOSTON
  68. bool "Support Boston"
  69. select DM
  70. select DM_SERIAL
  71. select OF_CONTROL
  72. select MIPS_CM
  73. select MIPS_L1_CACHE_SHIFT_6
  74. select MIPS_L2_CACHE
  75. select SUPPORTS_BIG_ENDIAN
  76. select SUPPORTS_LITTLE_ENDIAN
  77. select SUPPORTS_CPU_MIPS32_R1
  78. select SUPPORTS_CPU_MIPS32_R2
  79. select SUPPORTS_CPU_MIPS32_R6
  80. select SUPPORTS_CPU_MIPS64_R1
  81. select SUPPORTS_CPU_MIPS64_R2
  82. select SUPPORTS_CPU_MIPS64_R6
  83. config TARGET_XILFPGA
  84. bool "Support Imagination Xilfpga"
  85. select OF_CONTROL
  86. select DM
  87. select DM_SERIAL
  88. select DM_GPIO
  89. select DM_ETH
  90. select SUPPORTS_LITTLE_ENDIAN
  91. select SUPPORTS_CPU_MIPS32_R1
  92. select SUPPORTS_CPU_MIPS32_R2
  93. select MIPS_L1_CACHE_SHIFT_4
  94. help
  95. This supports IMGTEC MIPSfpga platform
  96. endchoice
  97. source "board/dbau1x00/Kconfig"
  98. source "board/imgtec/boston/Kconfig"
  99. source "board/imgtec/malta/Kconfig"
  100. source "board/imgtec/xilfpga/Kconfig"
  101. source "board/micronas/vct/Kconfig"
  102. source "board/pb1x00/Kconfig"
  103. source "board/qemu-mips/Kconfig"
  104. source "arch/mips/mach-ath79/Kconfig"
  105. source "arch/mips/mach-pic32/Kconfig"
  106. if MIPS
  107. choice
  108. prompt "Endianness selection"
  109. help
  110. Some MIPS boards can be configured for either little or big endian
  111. byte order. These modes require different U-Boot images. In general there
  112. is one preferred byteorder for a particular system but some systems are
  113. just as commonly used in the one or the other endianness.
  114. config SYS_BIG_ENDIAN
  115. bool "Big endian"
  116. depends on SUPPORTS_BIG_ENDIAN
  117. config SYS_LITTLE_ENDIAN
  118. bool "Little endian"
  119. depends on SUPPORTS_LITTLE_ENDIAN
  120. endchoice
  121. choice
  122. prompt "CPU selection"
  123. default CPU_MIPS32_R2
  124. config CPU_MIPS32_R1
  125. bool "MIPS32 Release 1"
  126. depends on SUPPORTS_CPU_MIPS32_R1
  127. select 32BIT
  128. help
  129. Choose this option to build an U-Boot for release 1 through 5 of the
  130. MIPS32 architecture.
  131. config CPU_MIPS32_R2
  132. bool "MIPS32 Release 2"
  133. depends on SUPPORTS_CPU_MIPS32_R2
  134. select 32BIT
  135. help
  136. Choose this option to build an U-Boot for release 2 through 5 of the
  137. MIPS32 architecture.
  138. config CPU_MIPS32_R6
  139. bool "MIPS32 Release 6"
  140. depends on SUPPORTS_CPU_MIPS32_R6
  141. select 32BIT
  142. help
  143. Choose this option to build an U-Boot for release 6 or later of the
  144. MIPS32 architecture.
  145. config CPU_MIPS64_R1
  146. bool "MIPS64 Release 1"
  147. depends on SUPPORTS_CPU_MIPS64_R1
  148. select 64BIT
  149. help
  150. Choose this option to build a kernel for release 1 through 5 of the
  151. MIPS64 architecture.
  152. config CPU_MIPS64_R2
  153. bool "MIPS64 Release 2"
  154. depends on SUPPORTS_CPU_MIPS64_R2
  155. select 64BIT
  156. help
  157. Choose this option to build a kernel for release 2 through 5 of the
  158. MIPS64 architecture.
  159. config CPU_MIPS64_R6
  160. bool "MIPS64 Release 6"
  161. depends on SUPPORTS_CPU_MIPS64_R6
  162. select 64BIT
  163. help
  164. Choose this option to build a kernel for release 6 or later of the
  165. MIPS64 architecture.
  166. endchoice
  167. menu "OS boot interface"
  168. config MIPS_BOOT_CMDLINE_LEGACY
  169. bool "Hand over legacy command line to Linux kernel"
  170. default y
  171. help
  172. Enable this option if you want U-Boot to hand over the Yamon-style
  173. command line to the kernel. All bootargs will be prepared as argc/argv
  174. compatible list. The argument count (argc) is stored in register $a0.
  175. The address of the argument list (argv) is stored in register $a1.
  176. config MIPS_BOOT_ENV_LEGACY
  177. bool "Hand over legacy environment to Linux kernel"
  178. default y
  179. help
  180. Enable this option if you want U-Boot to hand over the Yamon-style
  181. environment to the kernel. Information like memory size, initrd
  182. address and size will be prepared as zero-terminated key/value list.
  183. The address of the environment is stored in register $a2.
  184. config MIPS_BOOT_FDT
  185. bool "Hand over a flattened device tree to Linux kernel"
  186. default n
  187. help
  188. Enable this option if you want U-Boot to hand over a flattened
  189. device tree to the kernel. According to UHI register $a0 will be set
  190. to -2 and the FDT address is stored in $a1.
  191. endmenu
  192. config SUPPORTS_BIG_ENDIAN
  193. bool
  194. config SUPPORTS_LITTLE_ENDIAN
  195. bool
  196. config SUPPORTS_CPU_MIPS32_R1
  197. bool
  198. config SUPPORTS_CPU_MIPS32_R2
  199. bool
  200. config SUPPORTS_CPU_MIPS32_R6
  201. bool
  202. config SUPPORTS_CPU_MIPS64_R1
  203. bool
  204. config SUPPORTS_CPU_MIPS64_R2
  205. bool
  206. config SUPPORTS_CPU_MIPS64_R6
  207. bool
  208. config CPU_MIPS32
  209. bool
  210. default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
  211. config CPU_MIPS64
  212. bool
  213. default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
  214. config MIPS_TUNE_4KC
  215. bool
  216. config MIPS_TUNE_14KC
  217. bool
  218. config MIPS_TUNE_24KC
  219. bool
  220. config MIPS_TUNE_34KC
  221. bool
  222. config MIPS_TUNE_74KC
  223. bool
  224. config 32BIT
  225. bool
  226. config 64BIT
  227. bool
  228. config SWAP_IO_SPACE
  229. bool
  230. config SYS_MIPS_CACHE_INIT_RAM_LOAD
  231. bool
  232. config SYS_DCACHE_SIZE
  233. int
  234. default 0
  235. help
  236. The total size of the L1 Dcache, if known at compile time.
  237. config SYS_DCACHE_LINE_SIZE
  238. int
  239. default 0
  240. help
  241. The size of L1 Dcache lines, if known at compile time.
  242. config SYS_ICACHE_SIZE
  243. int
  244. default 0
  245. help
  246. The total size of the L1 ICache, if known at compile time.
  247. config SYS_ICACHE_LINE_SIZE
  248. int
  249. default 0
  250. help
  251. The size of L1 Icache lines, if known at compile time.
  252. config SYS_CACHE_SIZE_AUTO
  253. def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
  254. SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
  255. help
  256. Select this (or let it be auto-selected by not defining any cache
  257. sizes) in order to allow U-Boot to automatically detect the sizes
  258. of caches at runtime. This has a small cost in code size & runtime
  259. so if you know the cache configuration for your system at compile
  260. time it would be beneficial to configure it.
  261. config MIPS_L1_CACHE_SHIFT_4
  262. bool
  263. config MIPS_L1_CACHE_SHIFT_5
  264. bool
  265. config MIPS_L1_CACHE_SHIFT_6
  266. bool
  267. config MIPS_L1_CACHE_SHIFT_7
  268. bool
  269. config MIPS_L1_CACHE_SHIFT
  270. int
  271. default "7" if MIPS_L1_CACHE_SHIFT_7
  272. default "6" if MIPS_L1_CACHE_SHIFT_6
  273. default "5" if MIPS_L1_CACHE_SHIFT_5
  274. default "4" if MIPS_L1_CACHE_SHIFT_4
  275. default "5"
  276. config MIPS_L2_CACHE
  277. bool
  278. help
  279. Select this if your system includes an L2 cache and you want U-Boot
  280. to initialise & maintain it.
  281. config DYNAMIC_IO_PORT_BASE
  282. bool
  283. config MIPS_CM
  284. bool
  285. help
  286. Select this if your system contains a MIPS Coherence Manager and you
  287. wish U-Boot to configure it or make use of it to retrieve system
  288. information such as cache configuration.
  289. config MIPS_CM_BASE
  290. hex
  291. default 0x1fbf8000
  292. help
  293. The physical base address at which to map the MIPS Coherence Manager
  294. Global Configuration Registers (GCRs). This should be set such that
  295. the GCRs occupy a region of the physical address space which is
  296. otherwise unused, or at minimum that software doesn't need to access.
  297. endif
  298. endmenu