mmc.h 30 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based (loosely) on the Linux code
  7. */
  8. #ifndef _MMC_H_
  9. #define _MMC_H_
  10. #include <linux/bitops.h>
  11. #include <linux/list.h>
  12. #include <linux/sizes.h>
  13. #include <linux/compiler.h>
  14. #include <linux/dma-direction.h>
  15. #include <part.h>
  16. struct bd_info;
  17. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  18. #define MMC_SUPPORTS_TUNING
  19. #endif
  20. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  21. #define MMC_SUPPORTS_TUNING
  22. #endif
  23. /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  24. #define SD_VERSION_SD (1U << 31)
  25. #define MMC_VERSION_MMC (1U << 30)
  26. #define MAKE_SDMMC_VERSION(a, b, c) \
  27. ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  28. #define MAKE_SD_VERSION(a, b, c) \
  29. (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  30. #define MAKE_MMC_VERSION(a, b, c) \
  31. (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  32. #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
  33. (((u32)(x) >> 16) & 0xff)
  34. #define EXTRACT_SDMMC_MINOR_VERSION(x) \
  35. (((u32)(x) >> 8) & 0xff)
  36. #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  37. ((u32)(x) & 0xff)
  38. #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
  39. #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
  40. #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
  41. #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
  42. #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
  43. #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
  44. #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
  45. #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
  46. #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
  47. #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
  48. #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
  49. #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
  50. #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
  51. #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
  52. #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
  53. #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
  54. #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
  55. #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
  56. #define MMC_CAP(mode) (1 << mode)
  57. #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  58. #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
  59. #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
  60. #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
  61. #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
  62. #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
  63. #define MMC_CAP_NONREMOVABLE BIT(14)
  64. #define MMC_CAP_NEEDS_POLL BIT(15)
  65. #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
  66. #define MMC_MODE_8BIT BIT(30)
  67. #define MMC_MODE_4BIT BIT(29)
  68. #define MMC_MODE_1BIT BIT(28)
  69. #define MMC_MODE_SPI BIT(27)
  70. #define SD_DATA_4BIT 0x00040000
  71. #define IS_SD(x) ((x)->version & SD_VERSION_SD)
  72. #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
  73. #define MMC_DATA_READ 1
  74. #define MMC_DATA_WRITE 2
  75. #define MMC_CMD_GO_IDLE_STATE 0
  76. #define MMC_CMD_SEND_OP_COND 1
  77. #define MMC_CMD_ALL_SEND_CID 2
  78. #define MMC_CMD_SET_RELATIVE_ADDR 3
  79. #define MMC_CMD_SET_DSR 4
  80. #define MMC_CMD_SWITCH 6
  81. #define MMC_CMD_SELECT_CARD 7
  82. #define MMC_CMD_SEND_EXT_CSD 8
  83. #define MMC_CMD_SEND_CSD 9
  84. #define MMC_CMD_SEND_CID 10
  85. #define MMC_CMD_STOP_TRANSMISSION 12
  86. #define MMC_CMD_SEND_STATUS 13
  87. #define MMC_CMD_SET_BLOCKLEN 16
  88. #define MMC_CMD_READ_SINGLE_BLOCK 17
  89. #define MMC_CMD_READ_MULTIPLE_BLOCK 18
  90. #define MMC_CMD_SEND_TUNING_BLOCK 19
  91. #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  92. #define MMC_CMD_SET_BLOCK_COUNT 23
  93. #define MMC_CMD_WRITE_SINGLE_BLOCK 24
  94. #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
  95. #define MMC_CMD_ERASE_GROUP_START 35
  96. #define MMC_CMD_ERASE_GROUP_END 36
  97. #define MMC_CMD_ERASE 38
  98. #define MMC_CMD_APP_CMD 55
  99. #define MMC_CMD_SPI_READ_OCR 58
  100. #define MMC_CMD_SPI_CRC_ON_OFF 59
  101. #define MMC_CMD_RES_MAN 62
  102. #define MMC_CMD62_ARG1 0xefac62ec
  103. #define MMC_CMD62_ARG2 0xcbaea7
  104. #define SD_CMD_SEND_RELATIVE_ADDR 3
  105. #define SD_CMD_SWITCH_FUNC 6
  106. #define SD_CMD_SEND_IF_COND 8
  107. #define SD_CMD_SWITCH_UHS18V 11
  108. #define SD_CMD_APP_SET_BUS_WIDTH 6
  109. #define SD_CMD_APP_SD_STATUS 13
  110. #define SD_CMD_ERASE_WR_BLK_START 32
  111. #define SD_CMD_ERASE_WR_BLK_END 33
  112. #define SD_CMD_APP_SEND_OP_COND 41
  113. #define SD_CMD_APP_SEND_SCR 51
  114. static inline bool mmc_is_tuning_cmd(uint cmdidx)
  115. {
  116. if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
  117. (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
  118. return true;
  119. return false;
  120. }
  121. /* SCR definitions in different words */
  122. #define SD_HIGHSPEED_BUSY 0x00020000
  123. #define SD_HIGHSPEED_SUPPORTED 0x00020000
  124. #define UHS_SDR12_BUS_SPEED 0
  125. #define HIGH_SPEED_BUS_SPEED 1
  126. #define UHS_SDR25_BUS_SPEED 1
  127. #define UHS_SDR50_BUS_SPEED 2
  128. #define UHS_SDR104_BUS_SPEED 3
  129. #define UHS_DDR50_BUS_SPEED 4
  130. #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
  131. #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
  132. #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
  133. #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
  134. #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
  135. #define OCR_BUSY 0x80000000
  136. #define OCR_HCS 0x40000000
  137. #define OCR_S18R 0x1000000
  138. #define OCR_VOLTAGE_MASK 0x007FFF80
  139. #define OCR_ACCESS_MODE 0x60000000
  140. #define MMC_ERASE_ARG 0x00000000
  141. #define MMC_SECURE_ERASE_ARG 0x80000000
  142. #define MMC_TRIM_ARG 0x00000001
  143. #define MMC_DISCARD_ARG 0x00000003
  144. #define MMC_SECURE_TRIM1_ARG 0x80000001
  145. #define MMC_SECURE_TRIM2_ARG 0x80008000
  146. #define MMC_STATUS_MASK (~0x0206BF7F)
  147. #define MMC_STATUS_SWITCH_ERROR (1 << 7)
  148. #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
  149. #define MMC_STATUS_CURR_STATE (0xf << 9)
  150. #define MMC_STATUS_ERROR (1 << 19)
  151. #define MMC_STATE_PRG (7 << 9)
  152. #define MMC_STATE_TRANS (4 << 9)
  153. #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
  154. #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
  155. #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
  156. #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
  157. #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
  158. #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
  159. #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
  160. #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
  161. #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
  162. #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
  163. #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
  164. #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
  165. #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
  166. #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
  167. #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
  168. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  169. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  170. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  171. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
  172. addressed by index which are
  173. 1 in value field */
  174. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
  175. addressed by index, which are
  176. 1 in value field */
  177. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
  178. #define SD_SWITCH_CHECK 0
  179. #define SD_SWITCH_SWITCH 1
  180. /*
  181. * EXT_CSD fields
  182. */
  183. #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
  184. #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
  185. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  186. #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
  187. #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
  188. #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
  189. #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
  190. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  191. #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
  192. #define EXT_CSD_WR_REL_PARAM 166 /* R */
  193. #define EXT_CSD_WR_REL_SET 167 /* R/W */
  194. #define EXT_CSD_RPMB_MULT 168 /* RO */
  195. #define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */
  196. #define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
  197. #define EXT_CSD_BOOT_WP_STATUS 174 /* R */
  198. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  199. #define EXT_CSD_BOOT_BUS_WIDTH 177
  200. #define EXT_CSD_PART_CONF 179 /* R/W */
  201. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  202. #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
  203. #define EXT_CSD_HS_TIMING 185 /* R/W */
  204. #define EXT_CSD_REV 192 /* RO */
  205. #define EXT_CSD_CARD_TYPE 196 /* RO */
  206. #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
  207. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  208. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  209. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  210. #define EXT_CSD_BOOT_MULT 226 /* RO */
  211. #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
  212. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  213. /*
  214. * EXT_CSD field definitions
  215. */
  216. #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
  217. #define EXT_CSD_CMD_SET_SECURE (1 << 1)
  218. #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
  219. #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
  220. #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
  221. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
  222. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
  223. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  224. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  225. #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
  226. /* SDR mode @1.8V I/O */
  227. #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
  228. /* SDR mode @1.2V I/O */
  229. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  230. EXT_CSD_CARD_TYPE_HS200_1_2V)
  231. #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
  232. #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
  233. #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
  234. EXT_CSD_CARD_TYPE_HS400_1_2V)
  235. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  236. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  237. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  238. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  239. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  240. #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
  241. #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
  242. #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
  243. #define EXT_CSD_TIMING_HS 1 /* HS */
  244. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  245. #define EXT_CSD_TIMING_HS400 3 /* HS400 */
  246. #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
  247. #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
  248. #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
  249. #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
  250. #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
  251. #define EXT_CSD_BOOT_ACK(x) (x << 6)
  252. #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
  253. #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
  254. #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
  255. #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
  256. #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
  257. #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
  258. #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
  259. #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
  260. #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
  261. #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
  262. #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
  263. #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
  264. #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
  265. #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
  266. #define R1_ILLEGAL_COMMAND (1 << 22)
  267. #define R1_APP_CMD (1 << 5)
  268. #define MMC_RSP_PRESENT (1 << 0)
  269. #define MMC_RSP_136 (1 << 1) /* 136 bit response */
  270. #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
  271. #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
  272. #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
  273. #define MMC_RSP_NONE (0)
  274. #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  275. #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
  276. MMC_RSP_BUSY)
  277. #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
  278. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  279. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  280. #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  281. #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  282. #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  283. #define MMCPART_NOAVAILABLE (0xff)
  284. #define PART_ACCESS_MASK (0x7)
  285. #define PART_SUPPORT (0x1)
  286. #define ENHNCD_SUPPORT (0x2)
  287. #define PART_ENH_ATTRIB (0x1f)
  288. #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
  289. #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
  290. #define MMC_QUIRK_RETRY_APP_CMD BIT(2)
  291. enum mmc_voltage {
  292. MMC_SIGNAL_VOLTAGE_000 = 0,
  293. MMC_SIGNAL_VOLTAGE_120 = 1,
  294. MMC_SIGNAL_VOLTAGE_180 = 2,
  295. MMC_SIGNAL_VOLTAGE_330 = 4,
  296. };
  297. #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
  298. MMC_SIGNAL_VOLTAGE_180 |\
  299. MMC_SIGNAL_VOLTAGE_330)
  300. /* Maximum block size for MMC */
  301. #define MMC_MAX_BLOCK_LEN 512
  302. /* The number of MMC physical partitions. These consist of:
  303. * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  304. */
  305. #define MMC_NUM_BOOT_PARTITION 2
  306. #define MMC_PART_RPMB 3 /* RPMB partition number */
  307. /* timing specification used */
  308. #define MMC_TIMING_LEGACY 0
  309. #define MMC_TIMING_MMC_HS 1
  310. #define MMC_TIMING_SD_HS 2
  311. #define MMC_TIMING_UHS_SDR12 3
  312. #define MMC_TIMING_UHS_SDR25 4
  313. #define MMC_TIMING_UHS_SDR50 5
  314. #define MMC_TIMING_UHS_SDR104 6
  315. #define MMC_TIMING_UHS_DDR50 7
  316. #define MMC_TIMING_MMC_DDR52 8
  317. #define MMC_TIMING_MMC_HS200 9
  318. #define MMC_TIMING_MMC_HS400 10
  319. /* Driver model support */
  320. /**
  321. * struct mmc_uclass_priv - Holds information about a device used by the uclass
  322. */
  323. struct mmc_uclass_priv {
  324. struct mmc *mmc;
  325. };
  326. /**
  327. * mmc_get_mmc_dev() - get the MMC struct pointer for a device
  328. *
  329. * Provided that the device is already probed and ready for use, this value
  330. * will be available.
  331. *
  332. * @dev: Device
  333. * @return associated mmc struct pointer if available, else NULL
  334. */
  335. struct mmc *mmc_get_mmc_dev(const struct udevice *dev);
  336. /* End of driver model support */
  337. struct mmc_cid {
  338. unsigned long psn;
  339. unsigned short oid;
  340. unsigned char mid;
  341. unsigned char prv;
  342. unsigned char mdt;
  343. char pnm[7];
  344. };
  345. struct mmc_cmd {
  346. ushort cmdidx;
  347. uint resp_type;
  348. uint cmdarg;
  349. uint response[4];
  350. };
  351. struct mmc_data {
  352. union {
  353. char *dest;
  354. const char *src; /* src buffers don't get written to */
  355. };
  356. uint flags;
  357. uint blocks;
  358. uint blocksize;
  359. };
  360. /* forward decl. */
  361. struct mmc;
  362. #if CONFIG_IS_ENABLED(DM_MMC)
  363. struct dm_mmc_ops {
  364. /**
  365. * deferred_probe() - Some configurations that need to be deferred
  366. * to just before enumerating the device
  367. *
  368. * @dev: Device to init
  369. * @return 0 if Ok, -ve if error
  370. */
  371. int (*deferred_probe)(struct udevice *dev);
  372. /**
  373. * reinit() - Re-initialization to clear old configuration for
  374. * mmc rescan.
  375. *
  376. * @dev: Device to reinit
  377. * @return 0 if Ok, -ve if error
  378. */
  379. int (*reinit)(struct udevice *dev);
  380. /**
  381. * send_cmd() - Send a command to the MMC device
  382. *
  383. * @dev: Device to receive the command
  384. * @cmd: Command to send
  385. * @data: Additional data to send/receive
  386. * @return 0 if OK, -ve on error
  387. */
  388. int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
  389. struct mmc_data *data);
  390. /**
  391. * set_ios() - Set the I/O speed/width for an MMC device
  392. *
  393. * @dev: Device to update
  394. * @return 0 if OK, -ve on error
  395. */
  396. int (*set_ios)(struct udevice *dev);
  397. /**
  398. * get_cd() - See whether a card is present
  399. *
  400. * @dev: Device to check
  401. * @return 0 if not present, 1 if present, -ve on error
  402. */
  403. int (*get_cd)(struct udevice *dev);
  404. /**
  405. * get_wp() - See whether a card has write-protect enabled
  406. *
  407. * @dev: Device to check
  408. * @return 0 if write-enabled, 1 if write-protected, -ve on error
  409. */
  410. int (*get_wp)(struct udevice *dev);
  411. #ifdef MMC_SUPPORTS_TUNING
  412. /**
  413. * execute_tuning() - Start the tuning process
  414. *
  415. * @dev: Device to start the tuning
  416. * @opcode: Command opcode to send
  417. * @return 0 if OK, -ve on error
  418. */
  419. int (*execute_tuning)(struct udevice *dev, uint opcode);
  420. #endif
  421. /**
  422. * wait_dat0() - wait until dat0 is in the target state
  423. * (CLK must be running during the wait)
  424. *
  425. * @dev: Device to check
  426. * @state: target state
  427. * @timeout_us: timeout in us
  428. * @return 0 if dat0 is in the target state, -ve on error
  429. */
  430. int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
  431. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  432. /* set_enhanced_strobe() - set HS400 enhanced strobe */
  433. int (*set_enhanced_strobe)(struct udevice *dev);
  434. #endif
  435. /**
  436. * host_power_cycle - host specific tasks in power cycle sequence
  437. * Called between mmc_power_off() and
  438. * mmc_power_on()
  439. *
  440. * @dev: Device to check
  441. * @return 0 if not present, 1 if present, -ve on error
  442. */
  443. int (*host_power_cycle)(struct udevice *dev);
  444. /**
  445. * get_b_max - get maximum length of single transfer
  446. * Called before reading blocks from the card,
  447. * useful for system which have e.g. DMA limits
  448. * on various memory ranges.
  449. *
  450. * @dev: Device to check
  451. * @dst: Destination buffer in memory
  452. * @blkcnt: Total number of blocks in this transfer
  453. * @return maximum number of blocks for this transfer
  454. */
  455. int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
  456. /**
  457. * hs400_prepare_ddr - prepare to switch to DDR mode
  458. *
  459. * @dev: Device to check
  460. * @return 0 if success, -ve on error
  461. */
  462. int (*hs400_prepare_ddr)(struct udevice *dev);
  463. };
  464. #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
  465. int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  466. struct mmc_data *data);
  467. int dm_mmc_set_ios(struct udevice *dev);
  468. int dm_mmc_get_cd(struct udevice *dev);
  469. int dm_mmc_get_wp(struct udevice *dev);
  470. int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
  471. int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
  472. int dm_mmc_host_power_cycle(struct udevice *dev);
  473. int dm_mmc_deferred_probe(struct udevice *dev);
  474. int dm_mmc_reinit(struct udevice *dev);
  475. int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
  476. /* Transition functions for compatibility */
  477. int mmc_set_ios(struct mmc *mmc);
  478. int mmc_getcd(struct mmc *mmc);
  479. int mmc_getwp(struct mmc *mmc);
  480. int mmc_execute_tuning(struct mmc *mmc, uint opcode);
  481. int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
  482. int mmc_set_enhanced_strobe(struct mmc *mmc);
  483. int mmc_host_power_cycle(struct mmc *mmc);
  484. int mmc_deferred_probe(struct mmc *mmc);
  485. int mmc_reinit(struct mmc *mmc);
  486. int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
  487. int mmc_hs400_prepare_ddr(struct mmc *mmc);
  488. #else
  489. struct mmc_ops {
  490. int (*send_cmd)(struct mmc *mmc,
  491. struct mmc_cmd *cmd, struct mmc_data *data);
  492. int (*set_ios)(struct mmc *mmc);
  493. int (*init)(struct mmc *mmc);
  494. int (*getcd)(struct mmc *mmc);
  495. int (*getwp)(struct mmc *mmc);
  496. int (*host_power_cycle)(struct mmc *mmc);
  497. int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
  498. };
  499. static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
  500. {
  501. return 0;
  502. }
  503. #endif
  504. struct mmc_config {
  505. const char *name;
  506. #if !CONFIG_IS_ENABLED(DM_MMC)
  507. const struct mmc_ops *ops;
  508. #endif
  509. uint host_caps;
  510. uint voltages;
  511. uint f_min;
  512. uint f_max;
  513. uint b_max;
  514. unsigned char part_type;
  515. #ifdef CONFIG_MMC_PWRSEQ
  516. struct udevice *pwr_dev;
  517. #endif
  518. };
  519. struct sd_ssr {
  520. unsigned int au; /* In sectors */
  521. unsigned int erase_timeout; /* In milliseconds */
  522. unsigned int erase_offset; /* In milliseconds */
  523. };
  524. enum bus_mode {
  525. MMC_LEGACY,
  526. MMC_HS,
  527. SD_HS,
  528. MMC_HS_52,
  529. MMC_DDR_52,
  530. UHS_SDR12,
  531. UHS_SDR25,
  532. UHS_SDR50,
  533. UHS_DDR50,
  534. UHS_SDR104,
  535. MMC_HS_200,
  536. MMC_HS_400,
  537. MMC_HS_400_ES,
  538. MMC_MODES_END
  539. };
  540. const char *mmc_mode_name(enum bus_mode mode);
  541. void mmc_dump_capabilities(const char *text, uint caps);
  542. static inline bool mmc_is_mode_ddr(enum bus_mode mode)
  543. {
  544. if (mode == MMC_DDR_52)
  545. return true;
  546. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  547. else if (mode == UHS_DDR50)
  548. return true;
  549. #endif
  550. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  551. else if (mode == MMC_HS_400)
  552. return true;
  553. #endif
  554. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  555. else if (mode == MMC_HS_400_ES)
  556. return true;
  557. #endif
  558. else
  559. return false;
  560. }
  561. #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
  562. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
  563. MMC_CAP(UHS_DDR50))
  564. static inline bool supports_uhs(uint caps)
  565. {
  566. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  567. return (caps & UHS_CAPS) ? true : false;
  568. #else
  569. return false;
  570. #endif
  571. }
  572. /*
  573. * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
  574. * with mmc_get_mmc_dev().
  575. *
  576. * TODO struct mmc should be in mmc_private but it's hard to fix right now
  577. */
  578. struct mmc {
  579. #if !CONFIG_IS_ENABLED(BLK)
  580. struct list_head link;
  581. #endif
  582. const struct mmc_config *cfg; /* provided configuration */
  583. uint version;
  584. void *priv;
  585. uint has_init;
  586. int high_capacity;
  587. bool clk_disable; /* true if the clock can be turned off */
  588. uint bus_width;
  589. uint clock;
  590. uint saved_clock;
  591. enum mmc_voltage signal_voltage;
  592. uint card_caps;
  593. uint host_caps;
  594. uint ocr;
  595. uint dsr;
  596. uint dsr_imp;
  597. uint scr[2];
  598. uint csd[4];
  599. uint cid[4];
  600. ushort rca;
  601. u8 part_support;
  602. u8 part_attr;
  603. u8 wr_rel_set;
  604. u8 part_config;
  605. u8 gen_cmd6_time; /* units: 10 ms */
  606. u8 part_switch_time; /* units: 10 ms */
  607. uint tran_speed;
  608. uint legacy_speed; /* speed for the legacy mode provided by the card */
  609. uint read_bl_len;
  610. #if CONFIG_IS_ENABLED(MMC_WRITE)
  611. uint write_bl_len;
  612. uint erase_grp_size; /* in 512-byte sectors */
  613. #endif
  614. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  615. uint hc_wp_grp_size; /* in 512-byte sectors */
  616. #endif
  617. #if CONFIG_IS_ENABLED(MMC_WRITE)
  618. struct sd_ssr ssr; /* SD status register */
  619. #endif
  620. u64 capacity;
  621. u64 capacity_user;
  622. u64 capacity_boot;
  623. u64 capacity_rpmb;
  624. u64 capacity_gp[4];
  625. #ifndef CONFIG_SPL_BUILD
  626. u64 enh_user_start;
  627. u64 enh_user_size;
  628. #endif
  629. #if !CONFIG_IS_ENABLED(BLK)
  630. struct blk_desc block_dev;
  631. #endif
  632. char op_cond_pending; /* 1 if we are waiting on an op_cond command */
  633. char init_in_progress; /* 1 if we have done mmc_start_init() */
  634. char preinit; /* start init as early as possible */
  635. int ddr_mode;
  636. #if CONFIG_IS_ENABLED(DM_MMC)
  637. struct udevice *dev; /* Device for this MMC controller */
  638. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  639. struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
  640. struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
  641. #endif
  642. #endif
  643. u8 *ext_csd;
  644. u32 cardtype; /* cardtype read from the MMC */
  645. enum mmc_voltage current_voltage;
  646. enum bus_mode selected_mode; /* mode currently used */
  647. enum bus_mode best_mode; /* best mode is the supported mode with the
  648. * highest bandwidth. It may not always be the
  649. * operating mode due to limitations when
  650. * accessing the boot partitions
  651. */
  652. u32 quirks;
  653. u8 hs400_tuning;
  654. };
  655. #if CONFIG_IS_ENABLED(DM_MMC)
  656. #define mmc_to_dev(_mmc) _mmc->dev
  657. #else
  658. #define mmc_to_dev(_mmc) NULL
  659. #endif
  660. struct mmc_hwpart_conf {
  661. struct {
  662. uint enh_start; /* in 512-byte sectors */
  663. uint enh_size; /* in 512-byte sectors, if 0 no enh area */
  664. unsigned wr_rel_change : 1;
  665. unsigned wr_rel_set : 1;
  666. } user;
  667. struct {
  668. uint size; /* in 512-byte sectors */
  669. unsigned enhanced : 1;
  670. unsigned wr_rel_change : 1;
  671. unsigned wr_rel_set : 1;
  672. } gp_part[4];
  673. };
  674. enum mmc_hwpart_conf_mode {
  675. MMC_HWPART_CONF_CHECK,
  676. MMC_HWPART_CONF_SET,
  677. MMC_HWPART_CONF_COMPLETE,
  678. };
  679. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
  680. /**
  681. * mmc_bind() - Set up a new MMC device ready for probing
  682. *
  683. * A child block device is bound with the IF_TYPE_MMC interface type. This
  684. * allows the device to be used with CONFIG_BLK
  685. *
  686. * @dev: MMC device to set up
  687. * @mmc: MMC struct
  688. * @cfg: MMC configuration
  689. * @return 0 if OK, -ve on error
  690. */
  691. int mmc_bind(struct udevice *dev, struct mmc *mmc,
  692. const struct mmc_config *cfg);
  693. void mmc_destroy(struct mmc *mmc);
  694. /**
  695. * mmc_unbind() - Unbind a MMC device's child block device
  696. *
  697. * @dev: MMC device
  698. * @return 0 if OK, -ve on error
  699. */
  700. int mmc_unbind(struct udevice *dev);
  701. int mmc_initialize(struct bd_info *bis);
  702. int mmc_init_device(int num);
  703. int mmc_init(struct mmc *mmc);
  704. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
  705. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  706. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  707. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  708. int mmc_deinit(struct mmc *mmc);
  709. #endif
  710. /**
  711. * mmc_of_parse() - Parse the device tree to get the capabilities of the host
  712. *
  713. * @dev: MMC device
  714. * @cfg: MMC configuration
  715. * @return 0 if OK, -ve on error
  716. */
  717. int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
  718. #ifdef CONFIG_MMC_PWRSEQ
  719. /**
  720. * mmc_pwrseq_get_power() - get a power device from device tree
  721. *
  722. * @dev: MMC device
  723. * @cfg: MMC configuration
  724. * @return 0 if OK, -ve on error
  725. */
  726. int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg);
  727. #endif
  728. int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
  729. /**
  730. * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
  731. *
  732. * @voltage: The mmc_voltage to convert
  733. * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
  734. */
  735. int mmc_voltage_to_mv(enum mmc_voltage voltage);
  736. /**
  737. * mmc_set_clock() - change the bus clock
  738. * @mmc: MMC struct
  739. * @clock: bus frequency in Hz
  740. * @disable: flag indicating if the clock must on or off
  741. * @return 0 if OK, -ve on error
  742. */
  743. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
  744. #define MMC_CLK_ENABLE false
  745. #define MMC_CLK_DISABLE true
  746. struct mmc *find_mmc_device(int dev_num);
  747. int mmc_set_dev(int dev_num);
  748. void print_mmc_devices(char separator);
  749. /**
  750. * get_mmc_num() - get the total MMC device number
  751. *
  752. * @return 0 if there is no MMC device, else the number of devices
  753. */
  754. int get_mmc_num(void);
  755. int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
  756. int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  757. enum mmc_hwpart_conf_mode mode);
  758. #if !CONFIG_IS_ENABLED(DM_MMC)
  759. int mmc_getcd(struct mmc *mmc);
  760. int board_mmc_getcd(struct mmc *mmc);
  761. int mmc_getwp(struct mmc *mmc);
  762. int board_mmc_getwp(struct mmc *mmc);
  763. #endif
  764. int mmc_set_dsr(struct mmc *mmc, u16 val);
  765. /* Function to change the size of boot partition and rpmb partitions */
  766. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  767. unsigned long rpmbsize);
  768. /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
  769. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
  770. /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
  771. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
  772. /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
  773. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
  774. /* Functions to read / write the RPMB partition */
  775. int mmc_rpmb_set_key(struct mmc *mmc, void *key);
  776. int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
  777. int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
  778. unsigned short cnt, unsigned char *key);
  779. int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
  780. unsigned short cnt, unsigned char *key);
  781. /**
  782. * mmc_rpmb_route_frames() - route RPMB data frames
  783. * @mmc Pointer to a MMC device struct
  784. * @req Request data frames
  785. * @reqlen Length of data frames in bytes
  786. * @rsp Supplied buffer for response data frames
  787. * @rsplen Length of supplied buffer for response data frames
  788. *
  789. * The RPMB data frames are routed to/from some external entity, for
  790. * example a Trusted Exectuion Environment in an arm TrustZone protected
  791. * secure world. It's expected that it's the external entity who is in
  792. * control of the RPMB key.
  793. *
  794. * Returns 0 on success, < 0 on error.
  795. */
  796. int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
  797. void *rsp, unsigned long rsplen);
  798. #ifdef CONFIG_CMD_BKOPS_ENABLE
  799. int mmc_set_bkops_enable(struct mmc *mmc);
  800. #endif
  801. /**
  802. * Start device initialization and return immediately; it does not block on
  803. * polling OCR (operation condition register) status. Useful for checking
  804. * the presence of SD/eMMC when no card detect logic is available.
  805. *
  806. * @param mmc Pointer to a MMC device struct
  807. * @return 0 on success, <0 on error.
  808. */
  809. int mmc_get_op_cond(struct mmc *mmc);
  810. /**
  811. * Start device initialization and return immediately; it does not block on
  812. * polling OCR (operation condition register) status. Then you should call
  813. * mmc_init, which would block on polling OCR status and complete the device
  814. * initializatin.
  815. *
  816. * @param mmc Pointer to a MMC device struct
  817. * @return 0 on success, <0 on error.
  818. */
  819. int mmc_start_init(struct mmc *mmc);
  820. /**
  821. * Set preinit flag of mmc device.
  822. *
  823. * This will cause the device to be pre-inited during mmc_initialize(),
  824. * which may save boot time if the device is not accessed until later.
  825. * Some eMMC devices take 200-300ms to init, but unfortunately they
  826. * must be sent a series of commands to even get them to start preparing
  827. * for operation.
  828. *
  829. * @param mmc Pointer to a MMC device struct
  830. * @param preinit preinit flag value
  831. */
  832. void mmc_set_preinit(struct mmc *mmc, int preinit);
  833. #ifdef CONFIG_MMC_SPI
  834. #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
  835. #else
  836. #define mmc_host_is_spi(mmc) 0
  837. #endif
  838. #define mmc_dev(x) ((x)->dev)
  839. void board_mmc_power_init(void);
  840. int board_mmc_init(struct bd_info *bis);
  841. int cpu_mmc_init(struct bd_info *bis);
  842. int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  843. # ifdef CONFIG_SYS_MMC_ENV_PART
  844. extern uint mmc_get_env_part(struct mmc *mmc);
  845. # endif
  846. int mmc_get_env_dev(void);
  847. /* Minimum partition switch timeout in units of 10-milliseconds */
  848. #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
  849. /* Set block count limit because of 16 bit register limit on some hardware*/
  850. #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
  851. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
  852. #endif
  853. /**
  854. * mmc_get_blk_desc() - Get the block descriptor for an MMC device
  855. *
  856. * @mmc: MMC device
  857. * @return block device if found, else NULL
  858. */
  859. struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
  860. /**
  861. * mmc_send_ext_csd() - read the extended CSD register
  862. *
  863. * @mmc: MMC device
  864. * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
  865. * the caller, e.g. using
  866. * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
  867. * Return: 0 for success
  868. */
  869. int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
  870. /**
  871. * mmc_boot_wp() - power on write protect boot partitions
  872. *
  873. * The boot partitions are write protected until the next power cycle.
  874. *
  875. * Return: 0 for success
  876. */
  877. int mmc_boot_wp(struct mmc *mmc);
  878. static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
  879. {
  880. return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  881. }
  882. #endif /* _MMC_H_ */