vsc9953.h 15 KB

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  1. /*
  2. * Copyright 2013, 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. * Driver for the Vitesse VSC9953 L2 Switch
  7. */
  8. #ifndef _VSC9953_H_
  9. #define _VSC9953_H_
  10. #include <config.h>
  11. #include <miiphy.h>
  12. #include <asm/types.h>
  13. #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
  14. #define VSC9953_SYS_OFFSET 0x010000
  15. #define VSC9953_REW_OFFSET 0x030000
  16. #define VSC9953_DEV_GMII_OFFSET 0x100000
  17. #define VSC9953_QSYS_OFFSET 0x200000
  18. #define VSC9953_ANA_OFFSET 0x280000
  19. #define VSC9953_DEVCPU_GCB 0x070000
  20. #define VSC9953_ES0 0x040000
  21. #define VSC9953_IS1 0x050000
  22. #define VSC9953_IS2 0x060000
  23. #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
  24. #define VSC9953_PHY_REGS_OFFST 0x0000AC
  25. /* Macros for vsc9953_chip_regs.soft_rst register */
  26. #define VSC9953_SOFT_SWC_RST_ENA 0x00000001
  27. /* Macros for vsc9953_sys_sys.reset_cfg register */
  28. #define VSC9953_CORE_ENABLE 0x80
  29. #define VSC9953_MEM_ENABLE 0x40
  30. #define VSC9953_MEM_INIT 0x20
  31. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
  32. #define VSC9953_MAC_ENA_CFG 0x00000011
  33. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
  34. #define VSC9953_MAC_MODE_CFG 0x00000011
  35. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
  36. #define VSC9953_MAC_IFG_CFG 0x00000515
  37. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
  38. #define VSC9953_MAC_HDX_CFG 0x00001043
  39. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
  40. #define VSC9953_MAC_MAX_LEN 0x000005ee
  41. /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
  42. #define VSC9953_CLOCK_CFG 0x00000001
  43. #define VSC9953_CLOCK_CFG_1000M 0x00000001
  44. /* Macros for vsc9953_sys_sys.front_port_mode register */
  45. #define VSC9953_FRONT_PORT_MODE 0x00000000
  46. /* Macros for vsc9953_ana_pfc.pfc_cfg register */
  47. #define VSC9953_PFC_FC 0x00000001
  48. #define VSC9953_PFC_FC_QSGMII 0x00000000
  49. /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
  50. #define VSC9953_MAC_FC_CFG 0x04700000
  51. #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
  52. /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
  53. #define VSC9953_PAUSE_CFG 0x001ffffe
  54. /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
  55. #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
  56. /* Macros for vsc9953_sys_sys.stat_cfg register */
  57. #define VSC9953_STAT_CLEAR_RX 0x00000400
  58. #define VSC9953_STAT_CLEAR_TX 0x00000800
  59. #define VSC9953_STAT_CLEAR_DR 0x00001000
  60. /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
  61. #define VSC9953_VCAP_MV_CFG 0x0000ffff
  62. #define VSC9953_VCAP_UPDATE_CTRL 0x01000004
  63. /* Macros for register vsc9953_ana_ana_tables.mac_access register */
  64. #define VSC9953_MAC_CMD_IDLE 0x00000000
  65. #define VSC9953_MAC_CMD_LEARN 0x00000001
  66. #define VSC9953_MAC_CMD_FORGET 0x00000002
  67. #define VSC9953_MAC_CMD_AGE 0x00000003
  68. #define VSC9953_MAC_CMD_NEXT 0x00000004
  69. #define VSC9953_MAC_CMD_READ 0x00000006
  70. #define VSC9953_MAC_CMD_WRITE 0x00000007
  71. #define VSC9953_MAC_CMD_MASK 0x00000007
  72. #define VSC9953_MAC_CMD_VALID 0x00000800
  73. #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
  74. #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
  75. #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
  76. #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
  77. #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
  78. #define VSC9953_MAC_DESTIDX_MASK 0x000001f8
  79. #define VSC9953_MAC_VID_MASK 0x1fff0000
  80. #define VSC9953_MAC_MACH_MASK 0x0000ffff
  81. /* Macros for vsc9953_ana_port.vlan_cfg register */
  82. #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
  83. #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
  84. #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
  85. #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
  86. #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
  87. /* Macros for vsc9953_rew_port.port_vlan_cfg register */
  88. #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
  89. /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
  90. #define VSC9953_ANA_TBL_VID_MASK 0x00000fff
  91. /* Macros for vsc9953_ana_ana_tables.vlan_access register */
  92. #define VSC9953_VLAN_PORT_MASK 0x00001ffc
  93. #define VSC9953_VLAN_CMD_MASK 0x00000003
  94. #define VSC9953_VLAN_CMD_IDLE 0x00000000
  95. #define VSC9953_VLAN_CMD_READ 0x00000001
  96. #define VSC9953_VLAN_CMD_WRITE 0x00000002
  97. #define VSC9953_VLAN_CMD_INIT 0x00000003
  98. /* Macros for vsc9953_ana_port.port_cfg register */
  99. #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
  100. #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
  101. #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
  102. #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
  103. #define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
  104. /* Macros for vsc9953_qsys_sys.switch_port_mode register */
  105. #define VSC9953_PORT_ENA 0x00002000
  106. /* Macros for vsc9953_ana_ana.agen_ctrl register */
  107. #define VSC9953_FID_MASK_ALL 0x00fff000
  108. /* Macros for vsc9953_ana_ana.adv_learn register */
  109. #define VSC9953_VLAN_CHK 0x00000400
  110. /* Macros for vsc9953_ana_ana.auto_age register */
  111. #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
  112. /* Macros for vsc9953_rew_port.port_tag_cfg register */
  113. #define VSC9953_TAG_CFG_MASK 0x00000180
  114. #define VSC9953_TAG_CFG_NONE 0x00000000
  115. #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
  116. #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
  117. #define VSC9953_TAG_CFG_ALL 0x00000180
  118. #define VSC9953_TAG_VID_PVID 0x00000010
  119. /* Macros for vsc9953_ana_ana.anag_efil register */
  120. #define VSC9953_AGE_PORT_EN 0x00080000
  121. #define VSC9953_AGE_PORT_MASK 0x0007c000
  122. #define VSC9953_AGE_VID_EN 0x00002000
  123. #define VSC9953_AGE_VID_MASK 0x00001fff
  124. /* Macros for vsc9953_ana_ana_tables.mach_data register */
  125. #define VSC9953_MACHDATA_VID_MASK 0x1fff0000
  126. /* Macros for vsc9953_ana_common.aggr_cfg register */
  127. #define VSC9953_AC_RND_ENA 0x00000080
  128. #define VSC9953_AC_DMAC_ENA 0x00000040
  129. #define VSC9953_AC_SMAC_ENA 0x00000020
  130. #define VSC9953_AC_IP6_LBL_ENA 0x00000010
  131. #define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
  132. #define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
  133. #define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
  134. #define VSC9953_AC_MASK 0x000000fe
  135. /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
  136. #define VSC9953_PGID_PORT_MASK 0x000003ff
  137. #define VSC9953_MAX_PORTS 10
  138. #define VSC9953_PORT_CHECK(port) \
  139. (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
  140. #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
  141. ( \
  142. (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
  143. ) ? 0 : 1 \
  144. )
  145. #define VSC9953_MAX_VLAN 4096
  146. #define VSC9953_VLAN_CHECK(vid) \
  147. (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
  148. #define VSC9953_DEFAULT_AGE_TIME 300
  149. #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
  150. #define MIIMIND_OPR_PEND 0x00000004
  151. struct vsc9953_mdio_info {
  152. struct vsc9953_mii_mng *regs;
  153. char *name;
  154. };
  155. /* VSC9953 ANA structure */
  156. struct vsc9953_ana_port {
  157. u32 vlan_cfg;
  158. u32 drop_cfg;
  159. u32 qos_cfg;
  160. u32 vcap_cfg;
  161. u32 vcap_s1_key_cfg[3];
  162. u32 vcap_s2_cfg;
  163. u32 qos_pcp_dei_map_cfg[16];
  164. u32 cpu_fwd_cfg;
  165. u32 cpu_fwd_bpdu_cfg;
  166. u32 cpu_fwd_garp_cfg;
  167. u32 cpu_fwd_ccm_cfg;
  168. u32 port_cfg;
  169. u32 pol_cfg;
  170. u32 reserved[34];
  171. };
  172. struct vsc9953_ana_pol {
  173. u32 pol_pir_cfg;
  174. u32 pol_cir_cfg;
  175. u32 pol_mode_cfg;
  176. u32 pol_pir_state;
  177. u32 pol_cir_state;
  178. u32 reserved1[3];
  179. };
  180. struct vsc9953_ana_ana_tables {
  181. u32 entry_lim[11];
  182. u32 an_moved;
  183. u32 mach_data;
  184. u32 macl_data;
  185. u32 mac_access;
  186. u32 mact_indx;
  187. u32 vlan_access;
  188. u32 vlan_tidx;
  189. };
  190. struct vsc9953_ana_ana {
  191. u32 adv_learn;
  192. u32 vlan_mask;
  193. u32 reserved;
  194. u32 anag_efil;
  195. u32 an_events;
  196. u32 storm_limit_burst;
  197. u32 storm_limit_cfg[4];
  198. u32 isolated_prts;
  199. u32 community_ports;
  200. u32 auto_age;
  201. u32 mac_options;
  202. u32 learn_disc;
  203. u32 agen_ctrl;
  204. u32 mirror_ports;
  205. u32 emirror_ports;
  206. u32 flooding;
  207. u32 flooding_ipmc;
  208. u32 sflow_cfg[11];
  209. u32 port_mode[12];
  210. };
  211. #define PGID_DST_START 0
  212. #define PGID_AGGR_START 64
  213. #define PGID_SRC_START 80
  214. struct vsc9953_ana_pgid {
  215. u32 port_grp_id[91];
  216. };
  217. struct vsc9953_ana_pfc {
  218. u32 pfc_cfg;
  219. u32 reserved1[15];
  220. };
  221. struct vsc9953_ana_pol_misc {
  222. u32 pol_flowc[10];
  223. u32 reserved1[17];
  224. u32 pol_hyst;
  225. };
  226. struct vsc9953_ana_common {
  227. u32 aggr_cfg;
  228. u32 cpuq_cfg;
  229. u32 cpuq_8021_cfg;
  230. u32 dscp_cfg;
  231. u32 dscp_rewr_cfg;
  232. u32 vcap_rng_type_cfg;
  233. u32 vcap_rng_val_cfg;
  234. u32 discard_cfg;
  235. u32 fid_cfg;
  236. };
  237. struct vsc9953_analyzer {
  238. struct vsc9953_ana_port port[11];
  239. u32 reserved1[9536];
  240. struct vsc9953_ana_pol pol[164];
  241. struct vsc9953_ana_ana_tables ana_tables;
  242. u32 reserved2[14];
  243. struct vsc9953_ana_ana ana;
  244. u32 reserved3[21];
  245. struct vsc9953_ana_pgid port_id_tbl;
  246. u32 reserved4[549];
  247. struct vsc9953_ana_pfc pfc[10];
  248. struct vsc9953_ana_pol_misc pol_misc;
  249. u32 reserved5[196];
  250. struct vsc9953_ana_common common;
  251. };
  252. /* END VSC9953 ANA structure t*/
  253. /* VSC9953 DEV_GMII structure */
  254. struct vsc9953_dev_gmii_port_mode {
  255. u32 clock_cfg;
  256. u32 port_misc;
  257. u32 reserved1;
  258. u32 eee_cfg;
  259. };
  260. struct vsc9953_dev_gmii_mac_cfg_status {
  261. u32 mac_ena_cfg;
  262. u32 mac_mode_cfg;
  263. u32 mac_maxlen_cfg;
  264. u32 mac_tags_cfg;
  265. u32 mac_adv_chk_cfg;
  266. u32 mac_ifg_cfg;
  267. u32 mac_hdx_cfg;
  268. u32 mac_fc_mac_low_cfg;
  269. u32 mac_fc_mac_high_cfg;
  270. u32 mac_sticky;
  271. };
  272. struct vsc9953_dev_gmii {
  273. struct vsc9953_dev_gmii_port_mode port_mode;
  274. struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
  275. };
  276. /* END VSC9953 DEV_GMII structure */
  277. /* VSC9953 QSYS structure */
  278. struct vsc9953_qsys_hsch {
  279. u32 cir_cfg;
  280. u32 reserved1;
  281. u32 se_cfg;
  282. u32 se_dwrr_cfg[8];
  283. u32 cir_state;
  284. u32 reserved2[20];
  285. };
  286. struct vsc9953_qsys_sys {
  287. u32 port_mode[12];
  288. u32 switch_port_mode[11];
  289. u32 stat_cnt_cfg;
  290. u32 eee_cfg[10];
  291. u32 eee_thrs;
  292. u32 igr_no_sharing;
  293. u32 egr_no_sharing;
  294. u32 sw_status[11];
  295. u32 ext_cpu_cfg;
  296. u32 cpu_group_map;
  297. u32 reserved1[23];
  298. };
  299. struct vsc9953_qsys_qos_cfg {
  300. u32 red_profile[16];
  301. u32 res_qos_mode;
  302. };
  303. struct vsc9953_qsys_drop_cfg {
  304. u32 egr_drop_mode;
  305. };
  306. struct vsc9953_qsys_mmgt {
  307. u32 eq_cntrl;
  308. u32 reserved1;
  309. };
  310. struct vsc9953_qsys_hsch_misc {
  311. u32 hsch_misc_cfg;
  312. u32 reserved1[546];
  313. };
  314. struct vsc9953_qsys_res_ctrl {
  315. u32 res_cfg;
  316. u32 res_stat;
  317. };
  318. struct vsc9953_qsys_reg {
  319. struct vsc9953_qsys_hsch hsch[108];
  320. struct vsc9953_qsys_sys sys;
  321. struct vsc9953_qsys_qos_cfg qos_cfg;
  322. struct vsc9953_qsys_drop_cfg drop_cfg;
  323. struct vsc9953_qsys_mmgt mmgt;
  324. struct vsc9953_qsys_hsch_misc hsch_misc;
  325. struct vsc9953_qsys_res_ctrl res_ctrl[1024];
  326. };
  327. /* END VSC9953 QSYS structure */
  328. /* VSC9953 SYS structure */
  329. struct vsc9953_rx_cntrs {
  330. u32 c_rx_oct;
  331. u32 c_rx_uc;
  332. u32 c_rx_mc;
  333. u32 c_rx_bc;
  334. u32 c_rx_short;
  335. u32 c_rx_frag;
  336. u32 c_rx_jabber;
  337. u32 c_rx_crc;
  338. u32 c_rx_symbol_err;
  339. u32 c_rx_sz_64;
  340. u32 c_rx_sz_65_127;
  341. u32 c_rx_sz_128_255;
  342. u32 c_rx_sz_256_511;
  343. u32 c_rx_sz_512_1023;
  344. u32 c_rx_sz_1024_1526;
  345. u32 c_rx_sz_jumbo;
  346. u32 c_rx_pause;
  347. u32 c_rx_control;
  348. u32 c_rx_long;
  349. u32 c_rx_cat_drop;
  350. u32 c_rx_red_prio_0;
  351. u32 c_rx_red_prio_1;
  352. u32 c_rx_red_prio_2;
  353. u32 c_rx_red_prio_3;
  354. u32 c_rx_red_prio_4;
  355. u32 c_rx_red_prio_5;
  356. u32 c_rx_red_prio_6;
  357. u32 c_rx_red_prio_7;
  358. u32 c_rx_yellow_prio_0;
  359. u32 c_rx_yellow_prio_1;
  360. u32 c_rx_yellow_prio_2;
  361. u32 c_rx_yellow_prio_3;
  362. u32 c_rx_yellow_prio_4;
  363. u32 c_rx_yellow_prio_5;
  364. u32 c_rx_yellow_prio_6;
  365. u32 c_rx_yellow_prio_7;
  366. u32 c_rx_green_prio_0;
  367. u32 c_rx_green_prio_1;
  368. u32 c_rx_green_prio_2;
  369. u32 c_rx_green_prio_3;
  370. u32 c_rx_green_prio_4;
  371. u32 c_rx_green_prio_5;
  372. u32 c_rx_green_prio_6;
  373. u32 c_rx_green_prio_7;
  374. u32 reserved[20];
  375. };
  376. struct vsc9953_tx_cntrs {
  377. u32 c_tx_oct;
  378. u32 c_tx_uc;
  379. u32 c_tx_mc;
  380. u32 c_tx_bc;
  381. u32 c_tx_col;
  382. u32 c_tx_drop;
  383. u32 c_tx_pause;
  384. u32 c_tx_sz_64;
  385. u32 c_tx_sz_65_127;
  386. u32 c_tx_sz_128_255;
  387. u32 c_tx_sz_256_511;
  388. u32 c_tx_sz_512_1023;
  389. u32 c_tx_sz_1024_1526;
  390. u32 c_tx_sz_jumbo;
  391. u32 c_tx_yellow_prio_0;
  392. u32 c_tx_yellow_prio_1;
  393. u32 c_tx_yellow_prio_2;
  394. u32 c_tx_yellow_prio_3;
  395. u32 c_tx_yellow_prio_4;
  396. u32 c_tx_yellow_prio_5;
  397. u32 c_tx_yellow_prio_6;
  398. u32 c_tx_yellow_prio_7;
  399. u32 c_tx_green_prio_0;
  400. u32 c_tx_green_prio_1;
  401. u32 c_tx_green_prio_2;
  402. u32 c_tx_green_prio_3;
  403. u32 c_tx_green_prio_4;
  404. u32 c_tx_green_prio_5;
  405. u32 c_tx_green_prio_6;
  406. u32 c_tx_green_prio_7;
  407. u32 c_tx_aged;
  408. u32 reserved[33];
  409. };
  410. struct vsc9953_drop_cntrs {
  411. u32 c_dr_local;
  412. u32 c_dr_tail;
  413. u32 c_dr_yellow_prio_0;
  414. u32 c_dr_yellow_prio_1;
  415. u32 c_dr_yellow_prio_2;
  416. u32 c_dr_yellow_prio_3;
  417. u32 c_dr_yellow_prio_4;
  418. u32 c_dr_yellow_prio_5;
  419. u32 c_dr_yellow_prio_6;
  420. u32 c_dr_yellow_prio_7;
  421. u32 c_dr_green_prio_0;
  422. u32 c_dr_green_prio_1;
  423. u32 c_dr_green_prio_2;
  424. u32 c_dr_green_prio_3;
  425. u32 c_dr_green_prio_4;
  426. u32 c_dr_green_prio_5;
  427. u32 c_dr_green_prio_6;
  428. u32 c_dr_green_prio_7;
  429. u32 reserved[46];
  430. };
  431. struct vsc9953_sys_stat {
  432. struct vsc9953_rx_cntrs rx_cntrs;
  433. struct vsc9953_tx_cntrs tx_cntrs;
  434. struct vsc9953_drop_cntrs drop_cntrs;
  435. u32 reserved1[6];
  436. };
  437. struct vsc9953_sys_sys {
  438. u32 reset_cfg;
  439. u32 reserved1;
  440. u32 vlan_etype_cfg;
  441. u32 port_mode[12];
  442. u32 front_port_mode[10];
  443. u32 frame_aging;
  444. u32 stat_cfg;
  445. u32 reserved2[50];
  446. };
  447. struct vsc9953_sys_pause_cfg {
  448. u32 pause_cfg[11];
  449. u32 pause_tot_cfg;
  450. u32 tail_drop_level[11];
  451. u32 tot_tail_drop_lvl;
  452. u32 mac_fc_cfg[10];
  453. };
  454. struct vsc9953_sys_mmgt {
  455. u16 free_cnt;
  456. };
  457. struct vsc9953_system_reg {
  458. struct vsc9953_sys_stat stat;
  459. struct vsc9953_sys_sys sys;
  460. struct vsc9953_sys_pause_cfg pause_cfg;
  461. struct vsc9953_sys_mmgt mmgt;
  462. };
  463. /* END VSC9953 SYS structure */
  464. /* VSC9953 REW structure */
  465. struct vsc9953_rew_port {
  466. u32 port_vlan_cfg;
  467. u32 port_tag_cfg;
  468. u32 port_port_cfg;
  469. u32 port_dscp_cfg;
  470. u32 port_pcp_dei_qos_map_cfg[16];
  471. u32 reserved[12];
  472. };
  473. struct vsc9953_rew_common {
  474. u32 reserve[4];
  475. u32 dscp_remap_dp1_cfg[64];
  476. u32 dscp_remap_cfg[64];
  477. };
  478. struct vsc9953_rew_reg {
  479. struct vsc9953_rew_port port[12];
  480. struct vsc9953_rew_common common;
  481. };
  482. /* END VSC9953 REW structure */
  483. /* VSC9953 DEVCPU_GCB structure */
  484. struct vsc9953_chip_regs {
  485. u32 chipd_id;
  486. u32 gpr;
  487. u32 soft_rst;
  488. };
  489. struct vsc9953_gpio {
  490. u32 gpio_out_set[10];
  491. u32 gpio_out_clr[10];
  492. u32 gpio_out[10];
  493. u32 gpio_in[10];
  494. };
  495. struct vsc9953_mii_mng {
  496. u32 miimstatus;
  497. u32 reserved1;
  498. u32 miimcmd;
  499. u32 miimdata;
  500. u32 miimcfg;
  501. u32 miimscan_0;
  502. u32 miimscan_1;
  503. u32 miiscan_lst_rslts;
  504. u32 miiscan_lst_rslts_valid;
  505. };
  506. struct vsc9953_mii_read_scan {
  507. u32 mii_scan_results_sticky[2];
  508. };
  509. struct vsc9953_devcpu_gcb {
  510. struct vsc9953_chip_regs chip_regs;
  511. struct vsc9953_gpio gpio;
  512. struct vsc9953_mii_mng mii_mng[2];
  513. struct vsc9953_mii_read_scan mii_read_scan;
  514. };
  515. /* END VSC9953 DEVCPU_GCB structure */
  516. /* VSC9953 IS* structure */
  517. struct vsc9953_vcap_core_cfg {
  518. u32 vcap_update_ctrl;
  519. u32 vcap_mv_cfg;
  520. };
  521. struct vsc9953_vcap {
  522. struct vsc9953_vcap_core_cfg vcap_core_cfg;
  523. };
  524. /* END VSC9953 IS* structure */
  525. #define VSC9953_PORT_INFO_INITIALIZER(idx) \
  526. { \
  527. .enabled = 0, \
  528. .phyaddr = 0, \
  529. .index = idx, \
  530. .phy_regs = NULL, \
  531. .enet_if = PHY_INTERFACE_MODE_NONE, \
  532. .bus = NULL, \
  533. .phydev = NULL, \
  534. }
  535. /* Structure to describe a VSC9953 port */
  536. struct vsc9953_port_info {
  537. u8 enabled;
  538. u8 phyaddr;
  539. int index;
  540. void *phy_regs;
  541. phy_interface_t enet_if;
  542. struct mii_dev *bus;
  543. struct phy_device *phydev;
  544. };
  545. /* Structure to describe a VSC9953 switch */
  546. struct vsc9953_info {
  547. struct vsc9953_port_info port[VSC9953_MAX_PORTS];
  548. };
  549. void vsc9953_init(bd_t *bis);
  550. void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
  551. void vsc9953_port_info_set_phy_address(int port_no, int address);
  552. void vsc9953_port_enable(int port_no);
  553. void vsc9953_port_disable(int port_no);
  554. void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
  555. #endif /* _VSC9953_H_ */