atmel_nand.c 39 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  8. *
  9. * Add Programmable Multibit ECC support for various AT91 SoC
  10. * (C) Copyright 2012 ATMEL, Hong Xu
  11. */
  12. #include <common.h>
  13. #include <log.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/gpio.h>
  16. #include <dm/device_compat.h>
  17. #include <dm/devres.h>
  18. #include <linux/bitops.h>
  19. #include <linux/bug.h>
  20. #include <linux/delay.h>
  21. #include <malloc.h>
  22. #include <nand.h>
  23. #include <watchdog.h>
  24. #include <linux/mtd/nand_ecc.h>
  25. #ifdef CONFIG_ATMEL_NAND_HWECC
  26. /* Register access macros */
  27. #define ecc_readl(add, reg) \
  28. readl(add + ATMEL_ECC_##reg)
  29. #define ecc_writel(add, reg, value) \
  30. writel((value), add + ATMEL_ECC_##reg)
  31. #include "atmel_nand_ecc.h" /* Hardware ECC registers */
  32. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  33. #ifdef CONFIG_SPL_BUILD
  34. #undef CONFIG_SYS_NAND_ONFI_DETECTION
  35. #endif
  36. struct atmel_nand_host {
  37. struct pmecc_regs __iomem *pmecc;
  38. struct pmecc_errloc_regs __iomem *pmerrloc;
  39. void __iomem *pmecc_rom_base;
  40. u8 pmecc_corr_cap;
  41. u16 pmecc_sector_size;
  42. u32 pmecc_index_table_offset;
  43. u32 pmecc_version;
  44. int pmecc_bytes_per_sector;
  45. int pmecc_sector_number;
  46. int pmecc_degree; /* Degree of remainders */
  47. int pmecc_cw_len; /* Length of codeword */
  48. /* lookup table for alpha_to and index_of */
  49. void __iomem *pmecc_alpha_to;
  50. void __iomem *pmecc_index_of;
  51. /* data for pmecc computation */
  52. int16_t *pmecc_smu;
  53. int16_t *pmecc_partial_syn;
  54. int16_t *pmecc_si;
  55. int16_t *pmecc_lmu; /* polynomal order */
  56. int *pmecc_mu;
  57. int *pmecc_dmu;
  58. int *pmecc_delta;
  59. };
  60. static struct atmel_nand_host pmecc_host;
  61. static struct nand_ecclayout atmel_pmecc_oobinfo;
  62. /*
  63. * Return number of ecc bytes per sector according to sector size and
  64. * correction capability
  65. *
  66. * Following table shows what at91 PMECC supported:
  67. * Correction Capability Sector_512_bytes Sector_1024_bytes
  68. * ===================== ================ =================
  69. * 2-bits 4-bytes 4-bytes
  70. * 4-bits 7-bytes 7-bytes
  71. * 8-bits 13-bytes 14-bytes
  72. * 12-bits 20-bytes 21-bytes
  73. * 24-bits 39-bytes 42-bytes
  74. * 32-bits 52-bytes 56-bytes
  75. */
  76. static int pmecc_get_ecc_bytes(int cap, int sector_size)
  77. {
  78. int m = 12 + sector_size / 512;
  79. return (m * cap + 7) / 8;
  80. }
  81. static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  82. int oobsize, int ecc_len)
  83. {
  84. int i;
  85. layout->eccbytes = ecc_len;
  86. /* ECC will occupy the last ecc_len bytes continuously */
  87. for (i = 0; i < ecc_len; i++)
  88. layout->eccpos[i] = oobsize - ecc_len + i;
  89. layout->oobfree[0].offset = 2;
  90. layout->oobfree[0].length =
  91. oobsize - ecc_len - layout->oobfree[0].offset;
  92. }
  93. static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
  94. {
  95. int table_size;
  96. table_size = host->pmecc_sector_size == 512 ?
  97. PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
  98. /* the ALPHA lookup table is right behind the INDEX lookup table. */
  99. return host->pmecc_rom_base + host->pmecc_index_table_offset +
  100. table_size * sizeof(int16_t);
  101. }
  102. static void pmecc_data_free(struct atmel_nand_host *host)
  103. {
  104. free(host->pmecc_partial_syn);
  105. free(host->pmecc_si);
  106. free(host->pmecc_lmu);
  107. free(host->pmecc_smu);
  108. free(host->pmecc_mu);
  109. free(host->pmecc_dmu);
  110. free(host->pmecc_delta);
  111. }
  112. static int pmecc_data_alloc(struct atmel_nand_host *host)
  113. {
  114. const int cap = host->pmecc_corr_cap;
  115. int size;
  116. size = (2 * cap + 1) * sizeof(int16_t);
  117. host->pmecc_partial_syn = malloc(size);
  118. host->pmecc_si = malloc(size);
  119. host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
  120. host->pmecc_smu = malloc((cap + 2) * size);
  121. size = (cap + 1) * sizeof(int);
  122. host->pmecc_mu = malloc(size);
  123. host->pmecc_dmu = malloc(size);
  124. host->pmecc_delta = malloc(size);
  125. if (host->pmecc_partial_syn &&
  126. host->pmecc_si &&
  127. host->pmecc_lmu &&
  128. host->pmecc_smu &&
  129. host->pmecc_mu &&
  130. host->pmecc_dmu &&
  131. host->pmecc_delta)
  132. return 0;
  133. /* error happened */
  134. pmecc_data_free(host);
  135. return -ENOMEM;
  136. }
  137. static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
  138. {
  139. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  140. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  141. int i;
  142. uint32_t value;
  143. /* Fill odd syndromes */
  144. for (i = 0; i < host->pmecc_corr_cap; i++) {
  145. value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
  146. if (i & 1)
  147. value >>= 16;
  148. value &= 0xffff;
  149. host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
  150. }
  151. }
  152. static void pmecc_substitute(struct mtd_info *mtd)
  153. {
  154. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  155. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  156. int16_t __iomem *alpha_to = host->pmecc_alpha_to;
  157. int16_t __iomem *index_of = host->pmecc_index_of;
  158. int16_t *partial_syn = host->pmecc_partial_syn;
  159. const int cap = host->pmecc_corr_cap;
  160. int16_t *si;
  161. int i, j;
  162. /* si[] is a table that holds the current syndrome value,
  163. * an element of that table belongs to the field
  164. */
  165. si = host->pmecc_si;
  166. memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
  167. /* Computation 2t syndromes based on S(x) */
  168. /* Odd syndromes */
  169. for (i = 1; i < 2 * cap; i += 2) {
  170. for (j = 0; j < host->pmecc_degree; j++) {
  171. if (partial_syn[i] & (0x1 << j))
  172. si[i] = readw(alpha_to + i * j) ^ si[i];
  173. }
  174. }
  175. /* Even syndrome = (Odd syndrome) ** 2 */
  176. for (i = 2, j = 1; j <= cap; i = ++j << 1) {
  177. if (si[j] == 0) {
  178. si[i] = 0;
  179. } else {
  180. int16_t tmp;
  181. tmp = readw(index_of + si[j]);
  182. tmp = (tmp * 2) % host->pmecc_cw_len;
  183. si[i] = readw(alpha_to + tmp);
  184. }
  185. }
  186. }
  187. /*
  188. * This function defines a Berlekamp iterative procedure for
  189. * finding the value of the error location polynomial.
  190. * The input is si[], initialize by pmecc_substitute().
  191. * The output is smu[][].
  192. *
  193. * This function is written according to chip datasheet Chapter:
  194. * Find the Error Location Polynomial Sigma(x) of Section:
  195. * Programmable Multibit ECC Control (PMECC).
  196. */
  197. static void pmecc_get_sigma(struct mtd_info *mtd)
  198. {
  199. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  200. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  201. int16_t *lmu = host->pmecc_lmu;
  202. int16_t *si = host->pmecc_si;
  203. int *mu = host->pmecc_mu;
  204. int *dmu = host->pmecc_dmu; /* Discrepancy */
  205. int *delta = host->pmecc_delta; /* Delta order */
  206. int cw_len = host->pmecc_cw_len;
  207. const int16_t cap = host->pmecc_corr_cap;
  208. const int num = 2 * cap + 1;
  209. int16_t __iomem *index_of = host->pmecc_index_of;
  210. int16_t __iomem *alpha_to = host->pmecc_alpha_to;
  211. int i, j, k;
  212. uint32_t dmu_0_count, tmp;
  213. int16_t *smu = host->pmecc_smu;
  214. /* index of largest delta */
  215. int ro;
  216. int largest;
  217. int diff;
  218. /* Init the Sigma(x) */
  219. memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
  220. dmu_0_count = 0;
  221. /* First Row */
  222. /* Mu */
  223. mu[0] = -1;
  224. smu[0] = 1;
  225. /* discrepancy set to 1 */
  226. dmu[0] = 1;
  227. /* polynom order set to 0 */
  228. lmu[0] = 0;
  229. /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
  230. delta[0] = -1;
  231. /* Second Row */
  232. /* Mu */
  233. mu[1] = 0;
  234. /* Sigma(x) set to 1 */
  235. smu[num] = 1;
  236. /* discrepancy set to S1 */
  237. dmu[1] = si[1];
  238. /* polynom order set to 0 */
  239. lmu[1] = 0;
  240. /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
  241. delta[1] = 0;
  242. for (i = 1; i <= cap; i++) {
  243. mu[i + 1] = i << 1;
  244. /* Begin Computing Sigma (Mu+1) and L(mu) */
  245. /* check if discrepancy is set to 0 */
  246. if (dmu[i] == 0) {
  247. dmu_0_count++;
  248. tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
  249. if ((cap - (lmu[i] >> 1) - 1) & 0x1)
  250. tmp += 2;
  251. else
  252. tmp += 1;
  253. if (dmu_0_count == tmp) {
  254. for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
  255. smu[(cap + 1) * num + j] =
  256. smu[i * num + j];
  257. lmu[cap + 1] = lmu[i];
  258. return;
  259. }
  260. /* copy polynom */
  261. for (j = 0; j <= lmu[i] >> 1; j++)
  262. smu[(i + 1) * num + j] = smu[i * num + j];
  263. /* copy previous polynom order to the next */
  264. lmu[i + 1] = lmu[i];
  265. } else {
  266. ro = 0;
  267. largest = -1;
  268. /* find largest delta with dmu != 0 */
  269. for (j = 0; j < i; j++) {
  270. if ((dmu[j]) && (delta[j] > largest)) {
  271. largest = delta[j];
  272. ro = j;
  273. }
  274. }
  275. /* compute difference */
  276. diff = (mu[i] - mu[ro]);
  277. /* Compute degree of the new smu polynomial */
  278. if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
  279. lmu[i + 1] = lmu[i];
  280. else
  281. lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
  282. /* Init smu[i+1] with 0 */
  283. for (k = 0; k < num; k++)
  284. smu[(i + 1) * num + k] = 0;
  285. /* Compute smu[i+1] */
  286. for (k = 0; k <= lmu[ro] >> 1; k++) {
  287. int16_t a, b, c;
  288. if (!(smu[ro * num + k] && dmu[i]))
  289. continue;
  290. a = readw(index_of + dmu[i]);
  291. b = readw(index_of + dmu[ro]);
  292. c = readw(index_of + smu[ro * num + k]);
  293. tmp = a + (cw_len - b) + c;
  294. a = readw(alpha_to + tmp % cw_len);
  295. smu[(i + 1) * num + (k + diff)] = a;
  296. }
  297. for (k = 0; k <= lmu[i] >> 1; k++)
  298. smu[(i + 1) * num + k] ^= smu[i * num + k];
  299. }
  300. /* End Computing Sigma (Mu+1) and L(mu) */
  301. /* In either case compute delta */
  302. delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
  303. /* Do not compute discrepancy for the last iteration */
  304. if (i >= cap)
  305. continue;
  306. for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
  307. tmp = 2 * (i - 1);
  308. if (k == 0) {
  309. dmu[i + 1] = si[tmp + 3];
  310. } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
  311. int16_t a, b, c;
  312. a = readw(index_of +
  313. smu[(i + 1) * num + k]);
  314. b = si[2 * (i - 1) + 3 - k];
  315. c = readw(index_of + b);
  316. tmp = a + c;
  317. tmp %= cw_len;
  318. dmu[i + 1] = readw(alpha_to + tmp) ^
  319. dmu[i + 1];
  320. }
  321. }
  322. }
  323. }
  324. static int pmecc_err_location(struct mtd_info *mtd)
  325. {
  326. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  327. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  328. const int cap = host->pmecc_corr_cap;
  329. const int num = 2 * cap + 1;
  330. int sector_size = host->pmecc_sector_size;
  331. int err_nbr = 0; /* number of error */
  332. int roots_nbr; /* number of roots */
  333. int i;
  334. uint32_t val;
  335. int16_t *smu = host->pmecc_smu;
  336. int timeout = PMECC_MAX_TIMEOUT_US;
  337. pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
  338. for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
  339. pmecc_writel(host->pmerrloc, sigma[i],
  340. smu[(cap + 1) * num + i]);
  341. err_nbr++;
  342. }
  343. val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
  344. if (sector_size == 1024)
  345. val |= PMERRLOC_ELCFG_SECTOR_1024;
  346. pmecc_writel(host->pmerrloc, elcfg, val);
  347. pmecc_writel(host->pmerrloc, elen,
  348. sector_size * 8 + host->pmecc_degree * cap);
  349. while (--timeout) {
  350. if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
  351. break;
  352. WATCHDOG_RESET();
  353. udelay(1);
  354. }
  355. if (!timeout) {
  356. dev_err(mtd->dev,
  357. "Timeout to calculate PMECC error location\n");
  358. return -1;
  359. }
  360. roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
  361. >> 8;
  362. /* Number of roots == degree of smu hence <= cap */
  363. if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
  364. return err_nbr - 1;
  365. /* Number of roots does not match the degree of smu
  366. * unable to correct error */
  367. return -1;
  368. }
  369. static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
  370. int sector_num, int extra_bytes, int err_nbr)
  371. {
  372. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  373. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  374. int i = 0;
  375. int byte_pos, bit_pos, sector_size, pos;
  376. uint32_t tmp;
  377. uint8_t err_byte;
  378. sector_size = host->pmecc_sector_size;
  379. while (err_nbr) {
  380. tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
  381. byte_pos = tmp / 8;
  382. bit_pos = tmp % 8;
  383. if (byte_pos >= (sector_size + extra_bytes))
  384. BUG(); /* should never happen */
  385. if (byte_pos < sector_size) {
  386. err_byte = *(buf + byte_pos);
  387. *(buf + byte_pos) ^= (1 << bit_pos);
  388. pos = sector_num * host->pmecc_sector_size + byte_pos;
  389. dev_dbg(mtd->dev,
  390. "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
  391. pos, bit_pos, err_byte, *(buf + byte_pos));
  392. } else {
  393. /* Bit flip in OOB area */
  394. tmp = sector_num * host->pmecc_bytes_per_sector
  395. + (byte_pos - sector_size);
  396. err_byte = ecc[tmp];
  397. ecc[tmp] ^= (1 << bit_pos);
  398. pos = tmp + nand_chip->ecc.layout->eccpos[0];
  399. dev_dbg(mtd->dev,
  400. "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
  401. pos, bit_pos, err_byte, ecc[tmp]);
  402. }
  403. i++;
  404. err_nbr--;
  405. }
  406. return;
  407. }
  408. static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
  409. u8 *ecc)
  410. {
  411. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  412. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  413. int i, err_nbr;
  414. u8 *buf_pos, *ecc_pos;
  415. for (i = 0; i < host->pmecc_sector_number; i++) {
  416. err_nbr = 0;
  417. if (pmecc_stat & 0x1) {
  418. buf_pos = buf + i * host->pmecc_sector_size;
  419. pmecc_gen_syndrome(mtd, i);
  420. pmecc_substitute(mtd);
  421. pmecc_get_sigma(mtd);
  422. err_nbr = pmecc_err_location(mtd);
  423. if (err_nbr >= 0) {
  424. pmecc_correct_data(mtd, buf_pos, ecc, i,
  425. host->pmecc_bytes_per_sector,
  426. err_nbr);
  427. } else if (host->pmecc_version < PMECC_VERSION_SAMA5D4) {
  428. ecc_pos = ecc + i * host->pmecc_bytes_per_sector;
  429. err_nbr = nand_check_erased_ecc_chunk(
  430. buf_pos, host->pmecc_sector_size,
  431. ecc_pos, host->pmecc_bytes_per_sector,
  432. NULL, 0, host->pmecc_corr_cap);
  433. }
  434. if (err_nbr < 0) {
  435. dev_err(mtd->dev, "PMECC: Too many errors\n");
  436. mtd->ecc_stats.failed++;
  437. return -EBADMSG;
  438. }
  439. mtd->ecc_stats.corrected += err_nbr;
  440. }
  441. pmecc_stat >>= 1;
  442. }
  443. return 0;
  444. }
  445. static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
  446. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  447. {
  448. struct atmel_nand_host *host = nand_get_controller_data(chip);
  449. int eccsize = chip->ecc.size;
  450. uint8_t *oob = chip->oob_poi;
  451. uint32_t *eccpos = chip->ecc.layout->eccpos;
  452. uint32_t stat;
  453. int timeout = PMECC_MAX_TIMEOUT_US;
  454. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  455. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  456. pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
  457. & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
  458. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  459. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
  460. chip->read_buf(mtd, buf, eccsize);
  461. chip->read_buf(mtd, oob, mtd->oobsize);
  462. while (--timeout) {
  463. if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
  464. break;
  465. WATCHDOG_RESET();
  466. udelay(1);
  467. }
  468. if (!timeout) {
  469. dev_err(mtd->dev, "Timeout to read PMECC page\n");
  470. return -1;
  471. }
  472. stat = pmecc_readl(host->pmecc, isr);
  473. if (stat != 0)
  474. if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
  475. return -EBADMSG;
  476. return 0;
  477. }
  478. static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
  479. struct nand_chip *chip, const uint8_t *buf,
  480. int oob_required, int page)
  481. {
  482. struct atmel_nand_host *host = nand_get_controller_data(chip);
  483. uint32_t *eccpos = chip->ecc.layout->eccpos;
  484. int i, j;
  485. int timeout = PMECC_MAX_TIMEOUT_US;
  486. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  487. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  488. pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
  489. PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
  490. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  491. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
  492. chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
  493. while (--timeout) {
  494. if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
  495. break;
  496. WATCHDOG_RESET();
  497. udelay(1);
  498. }
  499. if (!timeout) {
  500. dev_err(mtd->dev,
  501. "Timeout to read PMECC status, fail to write PMECC in oob\n");
  502. goto out;
  503. }
  504. for (i = 0; i < host->pmecc_sector_number; i++) {
  505. for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
  506. int pos;
  507. pos = i * host->pmecc_bytes_per_sector + j;
  508. chip->oob_poi[eccpos[pos]] =
  509. pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
  510. }
  511. }
  512. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  513. out:
  514. return 0;
  515. }
  516. static void atmel_pmecc_core_init(struct mtd_info *mtd)
  517. {
  518. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  519. struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
  520. uint32_t val = 0;
  521. struct nand_ecclayout *ecc_layout;
  522. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  523. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  524. switch (host->pmecc_corr_cap) {
  525. case 2:
  526. val = PMECC_CFG_BCH_ERR2;
  527. break;
  528. case 4:
  529. val = PMECC_CFG_BCH_ERR4;
  530. break;
  531. case 8:
  532. val = PMECC_CFG_BCH_ERR8;
  533. break;
  534. case 12:
  535. val = PMECC_CFG_BCH_ERR12;
  536. break;
  537. case 24:
  538. val = PMECC_CFG_BCH_ERR24;
  539. break;
  540. case 32:
  541. val = PMECC_CFG_BCH_ERR32;
  542. break;
  543. }
  544. if (host->pmecc_sector_size == 512)
  545. val |= PMECC_CFG_SECTOR512;
  546. else if (host->pmecc_sector_size == 1024)
  547. val |= PMECC_CFG_SECTOR1024;
  548. switch (host->pmecc_sector_number) {
  549. case 1:
  550. val |= PMECC_CFG_PAGE_1SECTOR;
  551. break;
  552. case 2:
  553. val |= PMECC_CFG_PAGE_2SECTORS;
  554. break;
  555. case 4:
  556. val |= PMECC_CFG_PAGE_4SECTORS;
  557. break;
  558. case 8:
  559. val |= PMECC_CFG_PAGE_8SECTORS;
  560. break;
  561. }
  562. val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
  563. | PMECC_CFG_AUTO_DISABLE);
  564. pmecc_writel(host->pmecc, cfg, val);
  565. ecc_layout = nand_chip->ecc.layout;
  566. pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
  567. pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
  568. pmecc_writel(host->pmecc, eaddr,
  569. ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
  570. /* See datasheet about PMECC Clock Control Register */
  571. pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
  572. pmecc_writel(host->pmecc, idr, 0xff);
  573. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  574. }
  575. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  576. /*
  577. * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
  578. * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
  579. * ONFI ECC parameters.
  580. * @host: point to an atmel_nand_host structure.
  581. * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
  582. * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
  583. * @chip: point to an nand_chip structure.
  584. * @cap: store the ONFI ECC correct bits capbility
  585. * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
  586. *
  587. * Return 0 if success. otherwise return the error code.
  588. */
  589. static int pmecc_choose_ecc(struct atmel_nand_host *host,
  590. struct nand_chip *chip,
  591. int *cap, int *sector_size)
  592. {
  593. /* Get ECC requirement from ONFI parameters */
  594. *cap = *sector_size = 0;
  595. if (chip->onfi_version) {
  596. *cap = chip->ecc_strength_ds;
  597. *sector_size = chip->ecc_step_ds;
  598. pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
  599. *cap, *sector_size);
  600. }
  601. if (*cap == 0 && *sector_size == 0) {
  602. /* Non-ONFI compliant */
  603. dev_info(chip->mtd.dev,
  604. "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
  605. *cap = 2;
  606. *sector_size = 512;
  607. }
  608. /* If head file doesn't specify then use the one in ONFI parameters */
  609. if (host->pmecc_corr_cap == 0) {
  610. /* use the most fitable ecc bits (the near bigger one ) */
  611. if (*cap <= 2)
  612. host->pmecc_corr_cap = 2;
  613. else if (*cap <= 4)
  614. host->pmecc_corr_cap = 4;
  615. else if (*cap <= 8)
  616. host->pmecc_corr_cap = 8;
  617. else if (*cap <= 12)
  618. host->pmecc_corr_cap = 12;
  619. else if (*cap <= 24)
  620. host->pmecc_corr_cap = 24;
  621. else
  622. #ifdef CONFIG_SAMA5D2
  623. host->pmecc_corr_cap = 32;
  624. #else
  625. host->pmecc_corr_cap = 24;
  626. #endif
  627. }
  628. if (host->pmecc_sector_size == 0) {
  629. /* use the most fitable sector size (the near smaller one ) */
  630. if (*sector_size >= 1024)
  631. host->pmecc_sector_size = 1024;
  632. else if (*sector_size >= 512)
  633. host->pmecc_sector_size = 512;
  634. else
  635. return -EINVAL;
  636. }
  637. return 0;
  638. }
  639. #endif
  640. #if defined(NO_GALOIS_TABLE_IN_ROM)
  641. static uint16_t *pmecc_galois_table;
  642. static inline int deg(unsigned int poly)
  643. {
  644. /* polynomial degree is the most-significant bit index */
  645. return fls(poly) - 1;
  646. }
  647. static int build_gf_tables(int mm, unsigned int poly,
  648. int16_t *index_of, int16_t *alpha_to)
  649. {
  650. unsigned int i, x = 1;
  651. const unsigned int k = 1 << deg(poly);
  652. unsigned int nn = (1 << mm) - 1;
  653. /* primitive polynomial must be of degree m */
  654. if (k != (1u << mm))
  655. return -EINVAL;
  656. for (i = 0; i < nn; i++) {
  657. alpha_to[i] = x;
  658. index_of[x] = i;
  659. if (i && (x == 1))
  660. /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
  661. return -EINVAL;
  662. x <<= 1;
  663. if (x & k)
  664. x ^= poly;
  665. }
  666. alpha_to[nn] = 1;
  667. index_of[0] = 0;
  668. return 0;
  669. }
  670. static uint16_t *create_lookup_table(int sector_size)
  671. {
  672. int degree = (sector_size == 512) ?
  673. PMECC_GF_DIMENSION_13 :
  674. PMECC_GF_DIMENSION_14;
  675. unsigned int poly = (sector_size == 512) ?
  676. PMECC_GF_13_PRIMITIVE_POLY :
  677. PMECC_GF_14_PRIMITIVE_POLY;
  678. int table_size = (sector_size == 512) ?
  679. PMECC_INDEX_TABLE_SIZE_512 :
  680. PMECC_INDEX_TABLE_SIZE_1024;
  681. int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
  682. if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
  683. return NULL;
  684. return (uint16_t *)addr;
  685. }
  686. #endif
  687. static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
  688. struct mtd_info *mtd)
  689. {
  690. struct atmel_nand_host *host;
  691. int cap, sector_size;
  692. host = &pmecc_host;
  693. nand_set_controller_data(nand, host);
  694. nand->ecc.mode = NAND_ECC_HW;
  695. nand->ecc.calculate = NULL;
  696. nand->ecc.correct = NULL;
  697. nand->ecc.hwctl = NULL;
  698. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  699. host->pmecc_corr_cap = host->pmecc_sector_size = 0;
  700. #ifdef CONFIG_PMECC_CAP
  701. host->pmecc_corr_cap = CONFIG_PMECC_CAP;
  702. #endif
  703. #ifdef CONFIG_PMECC_SECTOR_SIZE
  704. host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
  705. #endif
  706. /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
  707. * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
  708. * from ONFI.
  709. */
  710. if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
  711. dev_err(mtd->dev,
  712. "Required ECC %d bits in %d bytes not supported!\n",
  713. cap, sector_size);
  714. return -EINVAL;
  715. }
  716. if (cap > host->pmecc_corr_cap)
  717. dev_info(mtd->dev,
  718. "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
  719. host->pmecc_corr_cap, cap);
  720. if (sector_size < host->pmecc_sector_size)
  721. dev_info(mtd->dev,
  722. "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
  723. host->pmecc_sector_size, sector_size);
  724. #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
  725. host->pmecc_corr_cap = CONFIG_PMECC_CAP;
  726. host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
  727. #endif
  728. cap = host->pmecc_corr_cap;
  729. sector_size = host->pmecc_sector_size;
  730. /* TODO: need check whether cap & sector_size is validate */
  731. #if defined(NO_GALOIS_TABLE_IN_ROM)
  732. /*
  733. * As pmecc_rom_base is the begin of the gallois field table, So the
  734. * index offset just set as 0.
  735. */
  736. host->pmecc_index_table_offset = 0;
  737. #else
  738. if (host->pmecc_sector_size == 512)
  739. host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
  740. else
  741. host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
  742. #endif
  743. pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
  744. cap, sector_size);
  745. host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
  746. host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
  747. ATMEL_BASE_PMERRLOC;
  748. #if defined(NO_GALOIS_TABLE_IN_ROM)
  749. pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
  750. if (!pmecc_galois_table) {
  751. dev_err(mtd->dev, "out of memory\n");
  752. return -ENOMEM;
  753. }
  754. host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
  755. #else
  756. host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
  757. #endif
  758. /* ECC is calculated for the whole page (1 step) */
  759. nand->ecc.size = mtd->writesize;
  760. /* set ECC page size and oob layout */
  761. switch (mtd->writesize) {
  762. case 2048:
  763. case 4096:
  764. case 8192:
  765. host->pmecc_degree = (sector_size == 512) ?
  766. PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
  767. host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
  768. host->pmecc_sector_number = mtd->writesize / sector_size;
  769. host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
  770. cap, sector_size);
  771. host->pmecc_alpha_to = pmecc_get_alpha_to(host);
  772. host->pmecc_index_of = host->pmecc_rom_base +
  773. host->pmecc_index_table_offset;
  774. nand->ecc.steps = 1;
  775. nand->ecc.bytes = host->pmecc_bytes_per_sector *
  776. host->pmecc_sector_number;
  777. if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
  778. dev_err(mtd->dev,
  779. "too large eccpos entries. max support ecc.bytes is %d\n",
  780. MTD_MAX_ECCPOS_ENTRIES_LARGE);
  781. return -EINVAL;
  782. }
  783. if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
  784. dev_err(mtd->dev, "No room for ECC bytes\n");
  785. return -EINVAL;
  786. }
  787. pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
  788. mtd->oobsize,
  789. nand->ecc.bytes);
  790. nand->ecc.layout = &atmel_pmecc_oobinfo;
  791. break;
  792. case 512:
  793. case 1024:
  794. /* TODO */
  795. dev_err(mtd->dev,
  796. "Unsupported page size for PMECC, use Software ECC\n");
  797. default:
  798. /* page size not handled by HW ECC */
  799. /* switching back to soft ECC */
  800. nand->ecc.mode = NAND_ECC_SOFT;
  801. nand->ecc.read_page = NULL;
  802. nand->ecc.postpad = 0;
  803. nand->ecc.prepad = 0;
  804. nand->ecc.bytes = 0;
  805. return 0;
  806. }
  807. /* Allocate data for PMECC computation */
  808. if (pmecc_data_alloc(host)) {
  809. dev_err(mtd->dev,
  810. "Cannot allocate memory for PMECC computation!\n");
  811. return -ENOMEM;
  812. }
  813. nand->options |= NAND_NO_SUBPAGE_WRITE;
  814. nand->ecc.read_page = atmel_nand_pmecc_read_page;
  815. nand->ecc.write_page = atmel_nand_pmecc_write_page;
  816. nand->ecc.strength = cap;
  817. /* Check the PMECC ip version */
  818. host->pmecc_version = pmecc_readl(host->pmerrloc, version);
  819. dev_dbg(mtd->dev, "PMECC IP version is: %x\n", host->pmecc_version);
  820. atmel_pmecc_core_init(mtd);
  821. return 0;
  822. }
  823. #else
  824. /* oob layout for large page size
  825. * bad block info is on bytes 0 and 1
  826. * the bytes have to be consecutives to avoid
  827. * several NAND_CMD_RNDOUT during read
  828. */
  829. static struct nand_ecclayout atmel_oobinfo_large = {
  830. .eccbytes = 4,
  831. .eccpos = {60, 61, 62, 63},
  832. .oobfree = {
  833. {2, 58}
  834. },
  835. };
  836. /* oob layout for small page size
  837. * bad block info is on bytes 4 and 5
  838. * the bytes have to be consecutives to avoid
  839. * several NAND_CMD_RNDOUT during read
  840. */
  841. static struct nand_ecclayout atmel_oobinfo_small = {
  842. .eccbytes = 4,
  843. .eccpos = {0, 1, 2, 3},
  844. .oobfree = {
  845. {6, 10}
  846. },
  847. };
  848. /*
  849. * Calculate HW ECC
  850. *
  851. * function called after a write
  852. *
  853. * mtd: MTD block structure
  854. * dat: raw data (unused)
  855. * ecc_code: buffer for ECC
  856. */
  857. static int atmel_nand_calculate(struct mtd_info *mtd,
  858. const u_char *dat, unsigned char *ecc_code)
  859. {
  860. unsigned int ecc_value;
  861. /* get the first 2 ECC bytes */
  862. ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
  863. ecc_code[0] = ecc_value & 0xFF;
  864. ecc_code[1] = (ecc_value >> 8) & 0xFF;
  865. /* get the last 2 ECC bytes */
  866. ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
  867. ecc_code[2] = ecc_value & 0xFF;
  868. ecc_code[3] = (ecc_value >> 8) & 0xFF;
  869. return 0;
  870. }
  871. /*
  872. * HW ECC read page function
  873. *
  874. * mtd: mtd info structure
  875. * chip: nand chip info structure
  876. * buf: buffer to store read data
  877. * oob_required: caller expects OOB data read to chip->oob_poi
  878. */
  879. static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  880. uint8_t *buf, int oob_required, int page)
  881. {
  882. int eccsize = chip->ecc.size;
  883. int eccbytes = chip->ecc.bytes;
  884. uint32_t *eccpos = chip->ecc.layout->eccpos;
  885. uint8_t *p = buf;
  886. uint8_t *oob = chip->oob_poi;
  887. uint8_t *ecc_pos;
  888. int stat;
  889. /* read the page */
  890. chip->read_buf(mtd, p, eccsize);
  891. /* move to ECC position if needed */
  892. if (eccpos[0] != 0) {
  893. /* This only works on large pages
  894. * because the ECC controller waits for
  895. * NAND_CMD_RNDOUTSTART after the
  896. * NAND_CMD_RNDOUT.
  897. * anyway, for small pages, the eccpos[0] == 0
  898. */
  899. chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
  900. mtd->writesize + eccpos[0], -1);
  901. }
  902. /* the ECC controller needs to read the ECC just after the data */
  903. ecc_pos = oob + eccpos[0];
  904. chip->read_buf(mtd, ecc_pos, eccbytes);
  905. /* check if there's an error */
  906. stat = chip->ecc.correct(mtd, p, oob, NULL);
  907. if (stat < 0)
  908. mtd->ecc_stats.failed++;
  909. else
  910. mtd->ecc_stats.corrected += stat;
  911. /* get back to oob start (end of page) */
  912. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
  913. /* read the oob */
  914. chip->read_buf(mtd, oob, mtd->oobsize);
  915. return 0;
  916. }
  917. /*
  918. * HW ECC Correction
  919. *
  920. * function called after a read
  921. *
  922. * mtd: MTD block structure
  923. * dat: raw data read from the chip
  924. * read_ecc: ECC from the chip (unused)
  925. * isnull: unused
  926. *
  927. * Detect and correct a 1 bit error for a page
  928. */
  929. static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
  930. u_char *read_ecc, u_char *isnull)
  931. {
  932. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  933. unsigned int ecc_status;
  934. unsigned int ecc_word, ecc_bit;
  935. /* get the status from the Status Register */
  936. ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
  937. /* if there's no error */
  938. if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
  939. return 0;
  940. /* get error bit offset (4 bits) */
  941. ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
  942. /* get word address (12 bits) */
  943. ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
  944. ecc_word >>= 4;
  945. /* if there are multiple errors */
  946. if (ecc_status & ATMEL_ECC_MULERR) {
  947. /* check if it is a freshly erased block
  948. * (filled with 0xff) */
  949. if ((ecc_bit == ATMEL_ECC_BITADDR)
  950. && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
  951. /* the block has just been erased, return OK */
  952. return 0;
  953. }
  954. /* it doesn't seems to be a freshly
  955. * erased block.
  956. * We can't correct so many errors */
  957. dev_warn(mtd->dev,
  958. "multiple errors detected. Unable to correct.\n");
  959. return -EBADMSG;
  960. }
  961. /* if there's a single bit error : we can correct it */
  962. if (ecc_status & ATMEL_ECC_ECCERR) {
  963. /* there's nothing much to do here.
  964. * the bit error is on the ECC itself.
  965. */
  966. dev_warn(mtd->dev,
  967. "one bit error on ECC code. Nothing to correct\n");
  968. return 0;
  969. }
  970. dev_warn(mtd->dev,
  971. "one bit error on data. (word offset in the page : 0x%x bit offset : 0x%x)\n",
  972. ecc_word, ecc_bit);
  973. /* correct the error */
  974. if (nand_chip->options & NAND_BUSWIDTH_16) {
  975. /* 16 bits words */
  976. ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
  977. } else {
  978. /* 8 bits words */
  979. dat[ecc_word] ^= (1 << ecc_bit);
  980. }
  981. dev_warn(mtd->dev, "error corrected\n");
  982. return 1;
  983. }
  984. /*
  985. * Enable HW ECC : unused on most chips
  986. */
  987. static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
  988. {
  989. }
  990. int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
  991. {
  992. nand->ecc.mode = NAND_ECC_HW;
  993. nand->ecc.calculate = atmel_nand_calculate;
  994. nand->ecc.correct = atmel_nand_correct;
  995. nand->ecc.hwctl = atmel_nand_hwctl;
  996. nand->ecc.read_page = atmel_nand_read_page;
  997. nand->ecc.bytes = 4;
  998. nand->ecc.strength = 4;
  999. if (nand->ecc.mode == NAND_ECC_HW) {
  1000. /* ECC is calculated for the whole page (1 step) */
  1001. nand->ecc.size = mtd->writesize;
  1002. /* set ECC page size and oob layout */
  1003. switch (mtd->writesize) {
  1004. case 512:
  1005. nand->ecc.layout = &atmel_oobinfo_small;
  1006. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1007. ATMEL_ECC_PAGESIZE_528);
  1008. break;
  1009. case 1024:
  1010. nand->ecc.layout = &atmel_oobinfo_large;
  1011. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1012. ATMEL_ECC_PAGESIZE_1056);
  1013. break;
  1014. case 2048:
  1015. nand->ecc.layout = &atmel_oobinfo_large;
  1016. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1017. ATMEL_ECC_PAGESIZE_2112);
  1018. break;
  1019. case 4096:
  1020. nand->ecc.layout = &atmel_oobinfo_large;
  1021. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1022. ATMEL_ECC_PAGESIZE_4224);
  1023. break;
  1024. default:
  1025. /* page size not handled by HW ECC */
  1026. /* switching back to soft ECC */
  1027. nand->ecc.mode = NAND_ECC_SOFT;
  1028. nand->ecc.calculate = NULL;
  1029. nand->ecc.correct = NULL;
  1030. nand->ecc.hwctl = NULL;
  1031. nand->ecc.read_page = NULL;
  1032. nand->ecc.postpad = 0;
  1033. nand->ecc.prepad = 0;
  1034. nand->ecc.bytes = 0;
  1035. break;
  1036. }
  1037. }
  1038. return 0;
  1039. }
  1040. #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
  1041. #endif /* CONFIG_ATMEL_NAND_HWECC */
  1042. static void at91_nand_hwcontrol(struct mtd_info *mtd,
  1043. int cmd, unsigned int ctrl)
  1044. {
  1045. struct nand_chip *this = mtd_to_nand(mtd);
  1046. if (ctrl & NAND_CTRL_CHANGE) {
  1047. ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  1048. IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
  1049. | CONFIG_SYS_NAND_MASK_CLE);
  1050. if (ctrl & NAND_CLE)
  1051. IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
  1052. if (ctrl & NAND_ALE)
  1053. IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
  1054. #ifdef CONFIG_SYS_NAND_ENABLE_PIN
  1055. at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
  1056. !(ctrl & NAND_NCE));
  1057. #endif
  1058. this->IO_ADDR_W = (void *) IO_ADDR_W;
  1059. }
  1060. if (cmd != NAND_CMD_NONE)
  1061. writeb(cmd, this->IO_ADDR_W);
  1062. }
  1063. #ifdef CONFIG_SYS_NAND_READY_PIN
  1064. static int at91_nand_ready(struct mtd_info *mtd)
  1065. {
  1066. return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
  1067. }
  1068. #endif
  1069. #ifdef CONFIG_SPL_BUILD
  1070. /* The following code is for SPL */
  1071. static struct mtd_info *mtd;
  1072. static struct nand_chip nand_chip;
  1073. static int nand_command(int block, int page, uint32_t offs, u8 cmd)
  1074. {
  1075. struct nand_chip *this = mtd_to_nand(mtd);
  1076. int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  1077. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  1078. unsigned int ctrl) = this->cmd_ctrl;
  1079. while (!this->dev_ready(mtd))
  1080. ;
  1081. if (cmd == NAND_CMD_READOOB) {
  1082. offs += CONFIG_SYS_NAND_PAGE_SIZE;
  1083. cmd = NAND_CMD_READ0;
  1084. }
  1085. hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1086. if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
  1087. offs >>= 1;
  1088. hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1089. hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
  1090. hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
  1091. hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
  1092. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  1093. hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
  1094. #endif
  1095. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1096. hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1097. hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1098. while (!this->dev_ready(mtd))
  1099. ;
  1100. return 0;
  1101. }
  1102. static int nand_is_bad_block(int block)
  1103. {
  1104. struct nand_chip *this = mtd_to_nand(mtd);
  1105. nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
  1106. if (this->options & NAND_BUSWIDTH_16) {
  1107. if (readw(this->IO_ADDR_R) != 0xffff)
  1108. return 1;
  1109. } else {
  1110. if (readb(this->IO_ADDR_R) != 0xff)
  1111. return 1;
  1112. }
  1113. return 0;
  1114. }
  1115. #ifdef CONFIG_SPL_NAND_ECC
  1116. static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  1117. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  1118. CONFIG_SYS_NAND_ECCSIZE)
  1119. #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  1120. static int nand_read_page(int block, int page, void *dst)
  1121. {
  1122. struct nand_chip *this = mtd_to_nand(mtd);
  1123. u_char ecc_calc[ECCTOTAL];
  1124. u_char ecc_code[ECCTOTAL];
  1125. u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  1126. int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  1127. int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  1128. int eccsteps = ECCSTEPS;
  1129. int i;
  1130. uint8_t *p = dst;
  1131. nand_command(block, page, 0, NAND_CMD_READ0);
  1132. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1133. if (this->ecc.mode != NAND_ECC_SOFT)
  1134. this->ecc.hwctl(mtd, NAND_ECC_READ);
  1135. this->read_buf(mtd, p, eccsize);
  1136. this->ecc.calculate(mtd, p, &ecc_calc[i]);
  1137. }
  1138. this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  1139. for (i = 0; i < ECCTOTAL; i++)
  1140. ecc_code[i] = oob_data[nand_ecc_pos[i]];
  1141. eccsteps = ECCSTEPS;
  1142. p = dst;
  1143. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1144. this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1145. return 0;
  1146. }
  1147. int spl_nand_erase_one(int block, int page)
  1148. {
  1149. struct nand_chip *this = mtd_to_nand(mtd);
  1150. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  1151. unsigned int ctrl) = this->cmd_ctrl;
  1152. int page_addr;
  1153. if (nand_chip.select_chip)
  1154. nand_chip.select_chip(mtd, 0);
  1155. page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  1156. hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1157. /* Row address */
  1158. hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1159. hwctrl(mtd, ((page_addr >> 8) & 0xff),
  1160. NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1161. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  1162. /* One more address cycle for devices > 128MiB */
  1163. hwctrl(mtd, (page_addr >> 16) & 0x0f,
  1164. NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1165. #endif
  1166. hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1167. while (!this->dev_ready(mtd))
  1168. ;
  1169. nand_deselect();
  1170. return 0;
  1171. }
  1172. #else
  1173. static int nand_read_page(int block, int page, void *dst)
  1174. {
  1175. struct nand_chip *this = mtd_to_nand(mtd);
  1176. nand_command(block, page, 0, NAND_CMD_READ0);
  1177. atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
  1178. return 0;
  1179. }
  1180. #endif /* CONFIG_SPL_NAND_ECC */
  1181. int at91_nand_wait_ready(struct mtd_info *mtd)
  1182. {
  1183. struct nand_chip *this = mtd_to_nand(mtd);
  1184. udelay(this->chip_delay);
  1185. return 1;
  1186. }
  1187. int board_nand_init(struct nand_chip *nand)
  1188. {
  1189. int ret = 0;
  1190. nand->ecc.mode = NAND_ECC_SOFT;
  1191. #ifdef CONFIG_SYS_NAND_DBW_16
  1192. nand->options = NAND_BUSWIDTH_16;
  1193. nand->read_buf = nand_read_buf16;
  1194. #else
  1195. nand->read_buf = nand_read_buf;
  1196. #endif
  1197. nand->cmd_ctrl = at91_nand_hwcontrol;
  1198. #ifdef CONFIG_SYS_NAND_READY_PIN
  1199. nand->dev_ready = at91_nand_ready;
  1200. #else
  1201. nand->dev_ready = at91_nand_wait_ready;
  1202. #endif
  1203. nand->chip_delay = 20;
  1204. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1205. nand->bbt_options |= NAND_BBT_USE_FLASH;
  1206. #endif
  1207. #ifdef CONFIG_ATMEL_NAND_HWECC
  1208. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  1209. ret = atmel_pmecc_nand_init_params(nand, mtd);
  1210. #endif
  1211. #endif
  1212. return ret;
  1213. }
  1214. void nand_init(void)
  1215. {
  1216. mtd = nand_to_mtd(&nand_chip);
  1217. mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
  1218. mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
  1219. nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1220. nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1221. board_nand_init(&nand_chip);
  1222. #ifdef CONFIG_SPL_NAND_ECC
  1223. if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
  1224. nand_chip.ecc.calculate = nand_calculate_ecc;
  1225. nand_chip.ecc.correct = nand_correct_data;
  1226. }
  1227. #endif
  1228. if (nand_chip.select_chip)
  1229. nand_chip.select_chip(mtd, 0);
  1230. }
  1231. void nand_deselect(void)
  1232. {
  1233. if (nand_chip.select_chip)
  1234. nand_chip.select_chip(mtd, -1);
  1235. }
  1236. #include "nand_spl_loaders.c"
  1237. #else
  1238. #ifndef CONFIG_SYS_NAND_BASE_LIST
  1239. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  1240. #endif
  1241. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  1242. static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
  1243. int atmel_nand_chip_init(int devnum, ulong base_addr)
  1244. {
  1245. int ret;
  1246. struct nand_chip *nand = &nand_chip[devnum];
  1247. struct mtd_info *mtd = nand_to_mtd(nand);
  1248. nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
  1249. #ifdef CONFIG_NAND_ECC_BCH
  1250. nand->ecc.mode = NAND_ECC_SOFT_BCH;
  1251. #else
  1252. nand->ecc.mode = NAND_ECC_SOFT;
  1253. #endif
  1254. #ifdef CONFIG_SYS_NAND_DBW_16
  1255. nand->options = NAND_BUSWIDTH_16;
  1256. #endif
  1257. nand->cmd_ctrl = at91_nand_hwcontrol;
  1258. #ifdef CONFIG_SYS_NAND_READY_PIN
  1259. nand->dev_ready = at91_nand_ready;
  1260. #endif
  1261. nand->chip_delay = 75;
  1262. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1263. nand->bbt_options |= NAND_BBT_USE_FLASH;
  1264. #endif
  1265. ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
  1266. if (ret)
  1267. return ret;
  1268. #ifdef CONFIG_ATMEL_NAND_HWECC
  1269. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  1270. ret = atmel_pmecc_nand_init_params(nand, mtd);
  1271. #else
  1272. ret = atmel_hwecc_nand_init_param(nand, mtd);
  1273. #endif
  1274. if (ret)
  1275. return ret;
  1276. #endif
  1277. ret = nand_scan_tail(mtd);
  1278. if (!ret)
  1279. nand_register(devnum, mtd);
  1280. return ret;
  1281. }
  1282. void board_nand_init(void)
  1283. {
  1284. int i;
  1285. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  1286. if (atmel_nand_chip_init(i, base_addr[i]))
  1287. log_err("atmel_nand: Fail to initialize #%d chip", i);
  1288. }
  1289. #endif /* CONFIG_SPL_BUILD */