pm9261.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
  7. * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <vsprintf.h>
  12. #include <asm/global_data.h>
  13. #include <linux/sizes.h>
  14. #include <asm/io.h>
  15. #include <asm/gpio.h>
  16. #include <asm/arch/at91sam9_smc.h>
  17. #include <asm/arch/at91_common.h>
  18. #include <asm/arch/at91_rstc.h>
  19. #include <asm/arch/at91_matrix.h>
  20. #include <asm/arch/clk.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/mach-types.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* ------------------------------------------------------------------------- */
  25. /*
  26. * Miscelaneous platform dependent initialisations
  27. */
  28. #ifdef CONFIG_CMD_NAND
  29. static void pm9261_nand_hw_init(void)
  30. {
  31. unsigned long csa;
  32. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  33. struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  34. /* Enable CS3 */
  35. csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
  36. writel(csa, &matrix->csa);
  37. /* Configure SMC CS3 for NAND/SmartMedia */
  38. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  39. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  40. &smc->cs[3].setup);
  41. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  42. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  43. &smc->cs[3].pulse);
  44. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  45. &smc->cs[3].cycle);
  46. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  47. AT91_SMC_MODE_EXNW_DISABLE |
  48. #ifdef CONFIG_SYS_NAND_DBW_16
  49. AT91_SMC_MODE_DBW_16 |
  50. #else /* CONFIG_SYS_NAND_DBW_8 */
  51. AT91_SMC_MODE_DBW_8 |
  52. #endif
  53. AT91_SMC_MODE_TDF_CYCLE(2),
  54. &smc->cs[3].mode);
  55. at91_periph_clk_enable(ATMEL_ID_PIOA);
  56. at91_periph_clk_enable(ATMEL_ID_PIOC);
  57. /* Configure RDY/BSY */
  58. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  59. /* Enable NandFlash */
  60. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  61. at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
  62. at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
  63. }
  64. #endif
  65. int board_early_init_f(void)
  66. {
  67. return 0;
  68. }
  69. int board_init(void)
  70. {
  71. /* arch number of PM9261-Board */
  72. gd->bd->bi_arch_number = MACH_TYPE_PM9261;
  73. /* adress of boot parameters */
  74. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  75. #ifdef CONFIG_CMD_NAND
  76. pm9261_nand_hw_init();
  77. #endif
  78. #ifdef CONFIG_DRIVER_DM9000
  79. pm9261_dm9000_hw_init();
  80. #endif
  81. return 0;
  82. }
  83. int dram_init(void)
  84. {
  85. /* dram_init must store complete ramsize in gd->ram_size */
  86. gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
  87. PHYS_SDRAM_SIZE);
  88. return 0;
  89. }
  90. int dram_init_banksize(void)
  91. {
  92. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  93. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  94. return 0;
  95. }
  96. #ifdef CONFIG_DISPLAY_BOARDINFO
  97. int checkboard (void)
  98. {
  99. char buf[32];
  100. printf ("Board : Ronetix PM9261\n");
  101. printf ("Crystal frequency: %8s MHz\n",
  102. strmhz(buf, get_main_clk_rate()));
  103. printf ("CPU clock : %8s MHz\n",
  104. strmhz(buf, get_cpu_clk_rate()));
  105. printf ("Master clock : %8s MHz\n",
  106. strmhz(buf, get_mck_clk_rate()));
  107. return 0;
  108. }
  109. #endif