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- // SPDX-License-Identifier: GPL-2.0+
- /*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
- * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- */
- #include <common.h>
- #include <init.h>
- #include <vsprintf.h>
- #include <asm/global_data.h>
- #include <linux/sizes.h>
- #include <asm/io.h>
- #include <asm/gpio.h>
- #include <asm/arch/at91sam9_smc.h>
- #include <asm/arch/at91_common.h>
- #include <asm/arch/at91_rstc.h>
- #include <asm/arch/at91_matrix.h>
- #include <asm/arch/clk.h>
- #include <asm/arch/gpio.h>
- #include <asm/mach-types.h>
- DECLARE_GLOBAL_DATA_PTR;
- /* ------------------------------------------------------------------------- */
- /*
- * Miscelaneous platform dependent initialisations
- */
- #ifdef CONFIG_CMD_NAND
- static void pm9261_nand_hw_init(void)
- {
- unsigned long csa;
- struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
- struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- /* Enable CS3 */
- csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
- writel(csa, &matrix->csa);
- /* Configure SMC CS3 for NAND/SmartMedia */
- writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
- AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
- &smc->cs[3].setup);
- writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
- AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
- &smc->cs[3].pulse);
- writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
- &smc->cs[3].cycle);
- writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
- AT91_SMC_MODE_EXNW_DISABLE |
- #ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_MODE_DBW_16 |
- #else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_MODE_DBW_8 |
- #endif
- AT91_SMC_MODE_TDF_CYCLE(2),
- &smc->cs[3].mode);
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- /* Configure RDY/BSY */
- gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
- /* Enable NandFlash */
- gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
- }
- #endif
- int board_early_init_f(void)
- {
- return 0;
- }
- int board_init(void)
- {
- /* arch number of PM9261-Board */
- gd->bd->bi_arch_number = MACH_TYPE_PM9261;
- /* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- #ifdef CONFIG_CMD_NAND
- pm9261_nand_hw_init();
- #endif
- #ifdef CONFIG_DRIVER_DM9000
- pm9261_dm9000_hw_init();
- #endif
- return 0;
- }
- int dram_init(void)
- {
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- PHYS_SDRAM_SIZE);
- return 0;
- }
- int dram_init_banksize(void)
- {
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
- return 0;
- }
- #ifdef CONFIG_DISPLAY_BOARDINFO
- int checkboard (void)
- {
- char buf[32];
- printf ("Board : Ronetix PM9261\n");
- printf ("Crystal frequency: %8s MHz\n",
- strmhz(buf, get_main_clk_rate()));
- printf ("CPU clock : %8s MHz\n",
- strmhz(buf, get_cpu_clk_rate()));
- printf ("Master clock : %8s MHz\n",
- strmhz(buf, get_mck_clk_rate()));
- return 0;
- }
- #endif
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