sama5d3_xplained.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Atmel Corporation
  4. * Bo Shen <voice.shen@atmel.com>
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <asm/global_data.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/sama5d3_smc.h>
  11. #include <asm/arch/at91_common.h>
  12. #include <asm/arch/at91_rstc.h>
  13. #include <asm/arch/gpio.h>
  14. #include <asm/arch/clk.h>
  15. #include <debug_uart.h>
  16. #include <spl.h>
  17. #include <asm/arch/atmel_mpddrc.h>
  18. #include <asm/arch/at91_wdt.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. extern void at91_pda_detect(void);
  21. #ifdef CONFIG_NAND_ATMEL
  22. void sama5d3_xplained_nand_hw_init(void)
  23. {
  24. struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  25. at91_periph_clk_enable(ATMEL_ID_SMC);
  26. /* Configure SMC CS3 for NAND/SmartMedia */
  27. writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
  28. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
  29. &smc->cs[3].setup);
  30. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  31. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
  32. &smc->cs[3].pulse);
  33. writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
  34. &smc->cs[3].cycle);
  35. writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
  36. AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
  37. AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
  38. AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  39. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  40. AT91_SMC_MODE_EXNW_DISABLE |
  41. #ifdef CONFIG_SYS_NAND_DBW_16
  42. AT91_SMC_MODE_DBW_16 |
  43. #else /* CONFIG_SYS_NAND_DBW_8 */
  44. AT91_SMC_MODE_DBW_8 |
  45. #endif
  46. AT91_SMC_MODE_TDF_CYCLE(3),
  47. &smc->cs[3].mode);
  48. }
  49. #endif
  50. #ifdef CONFIG_CMD_USB
  51. static void sama5d3_xplained_usb_hw_init(void)
  52. {
  53. at91_set_pio_output(AT91_PIO_PORTE, 3, 0);
  54. at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
  55. }
  56. #endif
  57. #ifdef CONFIG_GENERIC_ATMEL_MCI
  58. static void sama5d3_xplained_mci0_hw_init(void)
  59. {
  60. at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* MCI0 Power */
  61. }
  62. #endif
  63. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  64. void board_debug_uart_init(void)
  65. {
  66. at91_seriald_hw_init();
  67. }
  68. #endif
  69. #ifdef CONFIG_BOARD_LATE_INIT
  70. int board_late_init(void)
  71. {
  72. at91_pda_detect();
  73. return 0;
  74. }
  75. #endif
  76. #ifdef CONFIG_BOARD_EARLY_INIT_F
  77. int board_early_init_f(void)
  78. {
  79. #ifdef CONFIG_DEBUG_UART
  80. debug_uart_init();
  81. #endif
  82. return 0;
  83. }
  84. #endif
  85. int board_init(void)
  86. {
  87. /* adress of boot parameters */
  88. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  89. #ifdef CONFIG_NAND_ATMEL
  90. sama5d3_xplained_nand_hw_init();
  91. #endif
  92. #ifdef CONFIG_CMD_USB
  93. sama5d3_xplained_usb_hw_init();
  94. #endif
  95. #ifdef CONFIG_GENERIC_ATMEL_MCI
  96. sama5d3_xplained_mci0_hw_init();
  97. #endif
  98. return 0;
  99. }
  100. int dram_init(void)
  101. {
  102. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  103. CONFIG_SYS_SDRAM_SIZE);
  104. return 0;
  105. }
  106. /* SPL */
  107. #ifdef CONFIG_SPL_BUILD
  108. void spl_board_init(void)
  109. {
  110. #ifdef CONFIG_SD_BOOT
  111. #ifdef CONFIG_GENERIC_ATMEL_MCI
  112. sama5d3_xplained_mci0_hw_init();
  113. #endif
  114. #elif CONFIG_NAND_BOOT
  115. sama5d3_xplained_nand_hw_init();
  116. #endif
  117. }
  118. #ifdef CONFIG_SPL_OS_BOOT
  119. int spl_start_uboot(void)
  120. {
  121. return 0;
  122. }
  123. #endif
  124. static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
  125. {
  126. ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  127. ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  128. ATMEL_MPDDRC_CR_NR_ROW_14 |
  129. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  130. ATMEL_MPDDRC_CR_ENRDM_ON |
  131. ATMEL_MPDDRC_CR_NB_8BANKS |
  132. ATMEL_MPDDRC_CR_NDQS_DISABLED |
  133. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  134. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  135. /*
  136. * As the DDR2-SDRAm device requires a refresh time is 7.8125us
  137. * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
  138. */
  139. ddr2->rtr = 0x411;
  140. ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
  141. 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
  142. 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
  143. 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
  144. 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
  145. 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
  146. 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
  147. 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
  148. ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
  149. 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
  150. 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
  151. 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
  152. ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
  153. 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
  154. 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
  155. 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
  156. 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
  157. }
  158. void mem_init(void)
  159. {
  160. struct atmel_mpddrc_config ddr2;
  161. ddr2_conf(&ddr2);
  162. /* Enable MPDDR clock */
  163. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  164. at91_system_clk_enable(AT91_PMC_DDR);
  165. /* DDRAM2 Controller initialize */
  166. ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
  167. }
  168. void at91_pmc_init(void)
  169. {
  170. u32 tmp;
  171. tmp = AT91_PMC_PLLAR_29 |
  172. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  173. AT91_PMC_PLLXR_MUL(43) |
  174. AT91_PMC_PLLXR_DIV(1);
  175. at91_plla_init(tmp);
  176. at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
  177. tmp = AT91_PMC_MCKR_MDIV_4 |
  178. AT91_PMC_MCKR_CSS_PLLA;
  179. at91_mck_init(tmp);
  180. }
  181. #endif