vct.h 5.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
  4. */
  5. /*
  6. * This file contains the configuration parameters for the VCT board
  7. * family:
  8. *
  9. * vct_premium
  10. * vct_premium_small
  11. * vct_premium_onenand
  12. * vct_premium_onenand_small
  13. * vct_platinum
  14. * vct_platinum_small
  15. * vct_platinum_onenand
  16. * vct_platinum_onenand_small
  17. * vct_platinumavc
  18. * vct_platinumavc_small
  19. * vct_platinumavc_onenand
  20. * vct_platinumavc_onenand_small
  21. */
  22. #ifndef __CONFIG_H
  23. #define __CONFIG_H
  24. #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
  25. #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
  26. #define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
  27. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  28. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  29. #define CONFIG_SYS_MALLOC_LEN (1 << 20)
  30. #define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
  31. #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
  32. #if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
  33. #define CONFIG_VCT_NOR
  34. #endif
  35. /*
  36. * UART
  37. */
  38. #ifdef CONFIG_VCT_PLATINUMAVC
  39. #define UART_1_BASE 0xBDC30000
  40. #else
  41. #define UART_1_BASE 0xBF89C000
  42. #endif
  43. #define CONFIG_SYS_NS16550_SERIAL
  44. #define CONFIG_SYS_NS16550_REG_SIZE -4
  45. #define CONFIG_SYS_NS16550_COM1 UART_1_BASE
  46. #define CONFIG_SYS_NS16550_CLK 921600
  47. /*
  48. * SDRAM
  49. */
  50. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  51. #define CONFIG_SYS_MBYTES_SDRAM 128
  52. #define CONFIG_SYS_MEMTEST_START 0x80200000
  53. #define CONFIG_SYS_MEMTEST_END 0x80400000
  54. #define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
  55. #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
  56. #define CONFIG_NET_RETRY_COUNT 20
  57. #endif
  58. /*
  59. * Commands
  60. */
  61. #if defined(CONFIG_CMD_USB)
  62. /*
  63. * USB/EHCI
  64. */
  65. #define CONFIG_USB_EHCI_VCT /* on VCT platform */
  66. #define CONFIG_EHCI_MMIO_BIG_ENDIAN
  67. #define CONFIG_EHCI_DESC_BIG_ENDIAN
  68. #define CONFIG_EHCI_IS_TDI
  69. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
  70. #endif /* CONFIG_CMD_USB */
  71. /*
  72. * BOOTP options
  73. */
  74. #define CONFIG_BOOTP_BOOTFILESIZE
  75. /*
  76. * Miscellaneous configurable options
  77. */
  78. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  79. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  80. /*
  81. * FLASH and environment organization
  82. */
  83. #if defined(CONFIG_VCT_NOR)
  84. #define CONFIG_FLASH_NOT_MEM_MAPPED
  85. /*
  86. * We need special accessor functions for the CFI FLASH driver. This
  87. * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
  88. */
  89. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  90. /*
  91. * For the non-memory-mapped NOR FLASH, we need to define the
  92. * NOR FLASH area. This can't be detected via the addr2info()
  93. * function, since we check for flash access in the very early
  94. * U-Boot code, before the NOR FLASH is detected.
  95. */
  96. #define CONFIG_FLASH_BASE 0xb0000000
  97. #define CONFIG_FLASH_END 0xbfffffff
  98. /*
  99. * CFI driver settings
  100. */
  101. #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
  102. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
  103. #define CONFIG_SYS_FLASH_BASE 0xb0000000
  104. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  105. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  106. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  107. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  108. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  109. #ifdef CONFIG_ENV_IS_IN_FLASH
  110. #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
  111. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
  112. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  113. /* Address and size of Redundant Environment Sector */
  114. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  115. #endif /* CONFIG_ENV_IS_IN_FLASH */
  116. #endif /* CONFIG_VCT_NOR */
  117. #if defined(CONFIG_VCT_ONENAND)
  118. #define CONFIG_USE_ONENAND_BOARD_INIT
  119. #define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
  120. #define CONFIG_SYS_FLASH_BASE 0x00000000
  121. #define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
  122. #define CONFIG_ENV_SIZE (128 << 10) /* erase size */
  123. #endif /* CONFIG_VCT_ONENAND */
  124. /*
  125. * I2C/EEPROM
  126. */
  127. #define CONFIG_SYS_I2C
  128. #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  129. #define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
  130. #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
  131. /*
  132. * Software (bit-bang) I2C driver configuration
  133. */
  134. #define CONFIG_SYS_GPIO_I2C_SCL 11
  135. #define CONFIG_SYS_GPIO_I2C_SDA 10
  136. #ifndef __ASSEMBLY__
  137. int vct_gpio_dir(int pin, int dir);
  138. void vct_gpio_set(int pin, int val);
  139. int vct_gpio_get(int pin);
  140. #endif
  141. #define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
  142. #define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
  143. #define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
  144. #define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
  145. #define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
  146. #define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
  147. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  148. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  149. /* CAT24WC32 */
  150. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
  151. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
  152. /* 32 byte page write mode using*/
  153. /* last 5 bits of the address */
  154. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  155. #define CONFIG_BOOTCOMMAND "run test3"
  156. /*
  157. * UBI configuration
  158. */
  159. /*
  160. * We need a small, stripped down image to fit into the first 128k OneNAND
  161. * erase block (gzipped). This image only needs basic commands for FLASH
  162. * (NOR/OneNAND) usage and Linux kernel booting.
  163. */
  164. #if defined(CONFIG_VCT_SMALL_IMAGE)
  165. #undef CONFIG_SYS_I2C_SOFT
  166. #undef CONFIG_SOURCE
  167. #undef CONFIG_TIMESTAMP
  168. #endif /* CONFIG_VCT_SMALL_IMAGE */
  169. #endif /* __CONFIG_H */