m53menlo.h 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Menlosystems M53Menlo configuration
  4. * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
  5. * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
  6. */
  7. #ifndef __M53MENLO_CONFIG_H__
  8. #define __M53MENLO_CONFIG_H__
  9. #include <asm/arch/imx-regs.h>
  10. #define CONFIG_REVISION_TAG
  11. #define CONFIG_SYS_FSL_CLK
  12. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  13. /*
  14. * Memory configurations
  15. */
  16. #define PHYS_SDRAM_1 CSD0_BASE_ADDR
  17. #define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
  18. #define PHYS_SDRAM_2 CSD1_BASE_ADDR
  19. #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
  20. #define PHYS_SDRAM_SIZE (gd->ram_size)
  21. #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
  22. #define CONFIG_SYS_MEMTEST_START 0x70000000
  23. #define CONFIG_SYS_MEMTEST_END 0x8ff00000
  24. #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
  25. #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
  26. #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
  27. #define CONFIG_SYS_INIT_SP_OFFSET \
  28. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  29. #define CONFIG_SYS_INIT_SP_ADDR \
  30. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  31. /*
  32. * U-Boot general configurations
  33. */
  34. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  35. #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  36. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  37. /* Boot argument buffer size */
  38. /*
  39. * Serial Driver
  40. */
  41. #define CONFIG_MXC_UART
  42. #define CONFIG_MXC_UART_BASE UART1_BASE
  43. /*
  44. * MMC Driver
  45. */
  46. #ifdef CONFIG_CMD_MMC
  47. #define CONFIG_SYS_FSL_ESDHC_ADDR 0
  48. #define CONFIG_SYS_FSL_ESDHC_NUM 1
  49. #endif
  50. /*
  51. * NAND
  52. */
  53. #define CONFIG_ENV_SIZE (16 * 1024)
  54. #ifdef CONFIG_CMD_NAND
  55. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  56. #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
  57. #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
  58. #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
  59. #define CONFIG_SYS_NAND_LARGEPAGE
  60. #define CONFIG_MXC_NAND_HWECC
  61. /* Environment is in NAND */
  62. #define CONFIG_ENV_SECT_SIZE (128 * 1024)
  63. #define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE)
  64. #define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */
  65. #define CONFIG_ENV_OFFSET_REDUND \
  66. (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
  67. #endif
  68. /*
  69. * Ethernet on SOC (FEC)
  70. */
  71. #ifdef CONFIG_CMD_NET
  72. #define CONFIG_FEC_MXC
  73. #define IMX_FEC_BASE FEC_BASE_ADDR
  74. #define CONFIG_FEC_MXC_PHYADDR 0x0
  75. #define CONFIG_MII
  76. #define CONFIG_DISCOVER_PHY
  77. #define CONFIG_FEC_XCV_TYPE RMII
  78. #define CONFIG_ETHPRIME "FEC0"
  79. #endif
  80. /*
  81. * I2C
  82. */
  83. #ifdef CONFIG_CMD_I2C
  84. #define CONFIG_SYS_I2C
  85. #define CONFIG_SYS_I2C_MXC
  86. #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  87. #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  88. #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  89. #define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */
  90. #endif
  91. /*
  92. * RTC
  93. */
  94. #ifdef CONFIG_CMD_DATE
  95. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  96. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  97. #endif
  98. /*
  99. * USB
  100. */
  101. #ifdef CONFIG_CMD_USB
  102. #define CONFIG_MXC_USB_PORT 1
  103. #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  104. #define CONFIG_MXC_USB_FLAGS 0
  105. #endif
  106. /*
  107. * SATA
  108. */
  109. #ifdef CONFIG_CMD_SATA
  110. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  111. #define CONFIG_DWC_AHSATA_PORT_ID 0
  112. #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR
  113. #define CONFIG_LBA48
  114. #endif
  115. /*
  116. * LCD
  117. */
  118. #define CONFIG_VIDEO_BMP_RLE8
  119. #define CONFIG_VIDEO_BMP_GZIP
  120. #define CONFIG_SPLASH_SCREEN
  121. #define CONFIG_SPLASHIMAGE_GUARD
  122. #define CONFIG_SPLASH_SCREEN_ALIGN
  123. #define CONFIG_BMP_16BPP
  124. #define CONFIG_VIDEO_LOGO
  125. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
  126. /* LVDS display */
  127. #define CONFIG_SYS_LDB_CLOCK 33260000
  128. #define CONFIG_IMX_VIDEO_SKIP
  129. #define CONFIG_SPLASH_SOURCE
  130. /* IIM Fuses */
  131. #define CONFIG_FSL_IIM
  132. /* Watchdog */
  133. /*
  134. * Boot Linux
  135. */
  136. #define CONFIG_CMDLINE_TAG
  137. #define CONFIG_INITRD_TAG
  138. #define CONFIG_REVISION_TAG
  139. #define CONFIG_SETUP_MEMORY_TAGS
  140. #define CONFIG_BOOTFILE "boot/fitImage"
  141. #define CONFIG_LOADADDR 0x70800000
  142. #define CONFIG_BOOTCOMMAND "run mmc_mmc"
  143. #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  144. /*
  145. * NAND SPL
  146. */
  147. #define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
  148. #define CONFIG_SPL_PAD_TO 0x8000
  149. #define CONFIG_SPL_STACK 0x70004000
  150. #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
  151. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  152. #define CONFIG_SYS_NAND_OOBSIZE 64
  153. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  154. #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
  155. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
  156. /*
  157. * Extra Environments
  158. */
  159. #define CONFIG_HOSTNAME "m53menlo"
  160. #define CONFIG_EXTRA_ENV_SETTINGS \
  161. "consdev=ttymxc0\0" \
  162. "baudrate=115200\0" \
  163. "bootscript=boot.scr\0" \
  164. "mmcdev=0\0" \
  165. "mmcpart=1\0" \
  166. "rootpath=/srv/\0" \
  167. "kernel_addr_r=0x72000000\0" \
  168. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  169. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  170. "netdev=eth0\0" \
  171. "splashsource=mmc_fs\0" \
  172. "splashfile=boot/usplash.bmp.gz\0" \
  173. "splashimage=0x88000000\0" \
  174. "splashpos=m,m\0" \
  175. "stdout=serial,vidconsole\0" \
  176. "stderr=serial,vidconsole\0" \
  177. "addcons=" \
  178. "setenv bootargs ${bootargs} " \
  179. "console=${consdev},${baudrate}\0" \
  180. "addip=" \
  181. "setenv bootargs ${bootargs} " \
  182. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  183. ":${hostname}:${netdev}:off\0" \
  184. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  185. "addmisc=" \
  186. "setenv bootargs ${bootargs} ${miscargs}\0" \
  187. "addargs=run addcons addmisc addmtd\0" \
  188. "mmcload=" \
  189. "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \
  190. "${kernel_addr_r} ${bootfile}\0" \
  191. "miscargs=nohlt panic=1\0" \
  192. "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \
  193. "rootwait\0" \
  194. "mmc_mmc=" \
  195. "run mmcload mmcargs addargs ; " \
  196. "bootm ${kernel_addr_r}\0" \
  197. "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
  198. "net_nfs=" \
  199. "run netload nfsargs addip addargs ; " \
  200. "bootm ${kernel_addr_r}\0" \
  201. "nfsargs=" \
  202. "setenv bootargs root=/dev/nfs rw " \
  203. "nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \
  204. "try_bootscript=" \
  205. "mmc rescan;" \
  206. "if test -e mmc 0:1 ${bootscript} ; then " \
  207. "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \
  208. "then ; " \
  209. "echo Running bootscript... ; " \
  210. "source ${kernel_addr_r} ; " \
  211. "fi ; " \
  212. "fi\0"
  213. #if defined(CONFIG_SPL_BUILD)
  214. #undef CONFIG_WATCHDOG
  215. #define CONFIG_HW_WATCHDOG
  216. #endif
  217. #endif /* __M53MENLO_CONFIG_H__ */